diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/quick | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/quick')
50 files changed, 17609 insertions, 17301 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index a85398f56..59ee1a74c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2452265 # Simulator instruction rate (inst/s) -host_op_rate 2452264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70524991939 # Simulator tick rate (ticks/s) -host_mem_usage 374768 # Number of bytes of host memory used -host_seconds 26.51 # Real time elapsed on the host +host_inst_rate 2397277 # Simulator instruction rate (inst/s) +host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68943602925 # Simulator tick rate (ticks/s) +host_mem_usage 377676 # Number of bytes of host memory used +host_seconds 27.11 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 763584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68173952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 763584 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 869824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065218 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 408474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36469170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 408474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465306 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 408474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40660828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -737,20 +737,20 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999684 # number of replacements +system.l2c.tags.replacements 999687 # number of replacements system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use -system.l2c.tags.total_refs 4588619 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064734 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.309639 # Average number of references to valid blocks. +system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55911.037805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4939.570238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.759225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.853135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075372 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy @@ -761,8 +761,8 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 # system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 49101323 # Number of tag accesses -system.l2c.tags.data_accesses 49101323 # Number of data accesses +system.l2c.tags.tag_accesses 46365678 # Number of tag accesses +system.l2c.tags.data_accesses 46365678 # Number of data accesses system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits system.l2c.Writeback_hits::total 777520 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits @@ -774,22 +774,22 @@ system.l2c.SCUpgradeReq_hits::total 50 # nu system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 606993 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986545 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 606993 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910322 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606993 # number of overall hits +system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits system.l2c.overall_hits::cpu0.data 738161 # number of overall hits system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910322 # number of overall hits +system.l2c.overall_hits::total 1910319 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses @@ -799,22 +799,22 @@ system.l2c.SCUpgradeReq_misses::total 2285 # nu system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11931 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13591 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11931 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066177 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11931 # number of overall misses +system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses system.l2c.overall_misses::cpu1.data 12102 # number of overall misses -system.l2c.overall_misses::total 1066177 # number of overall misses +system.l2c.overall_misses::total 1066180 # number of overall misses system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) @@ -851,22 +851,22 @@ system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # mi system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019277 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013589 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358198 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019277 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358198 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -879,49 +879,55 @@ system.l2c.writebacks::writebacks 80913 # nu system.l2c.writebacks::total 80913 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948863 # Transaction distribution +system.membus.trans_dist::ReadResp 948866 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution system.membus.trans_dist::Writeback 122433 # Transaction distribution -system.membus.trans_dist::CleanEvict 922490 # Transaction distribution +system.membus.trans_dist::CleanEvict 917961 # Transaction distribution system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution system.membus.trans_dist::ReadExReq 126472 # Transaction distribution system.membus.trans_dist::ReadExResp 124247 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941414 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3178369 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3222443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3347604 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369280 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73455442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76124178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2210194 # Request fanout histogram +system.membus.snoop_fanout::samples 2205834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2210194 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2210194 # Request fanout histogram +system.membus.snoop_fanout::total 2205834 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2204578 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution @@ -929,30 +935,30 @@ system.toL2Bus.trans_dist::ReadExReq 295246 # Tr system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450155 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143095 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1705094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5410979 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41895 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 6099689 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.006841 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.082430 # Request fanout histogram +system.toL2Bus.snoops 1083281 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 6057958 99.32% 99.32% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41731 0.68% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 6099689 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 60a4f6e98..34e6d6348 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2495393 # Simulator instruction rate (inst/s) -host_op_rate 2495392 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76033049021 # Simulator tick rate (ticks/s) -host_mem_usage 371696 # Number of bytes of host memory used -host_seconds 24.06 # Real time elapsed on the host +host_inst_rate 2390951 # Simulator instruction rate (inst/s) +host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72850763127 # Simulator tick rate (ticks/s) +host_mem_usage 374092 # Number of bytes of host memory used +host_seconds 25.11 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -338,9 +338,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 992219 # number of replacements system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4561879 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.314315 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor @@ -356,8 +356,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48768396 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48768396 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits @@ -429,36 +429,42 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks system.cpu.l2cache.writebacks::total 74334 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2128840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163286 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8923355 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5984570 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.006972 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.083208 # Request fanout histogram +system.cpu.toL2Bus.snoops 1075788 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5942844 99.30% 99.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 0.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5984570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -561,7 +567,7 @@ system.membus.trans_dist::ReadResp 948374 # Tr system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution system.membus.trans_dist::Writeback 115846 # Transaction distribution -system.membus.trans_dist::CleanEvict 918371 # Transaction distribution +system.membus.trans_dist::CleanEvict 917156 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution system.membus.trans_dist::ReadExReq 116946 # Transaction distribution @@ -570,11 +576,11 @@ system.membus.trans_dist::ReadSharedReq 941190 # Tr system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3108719 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3142763 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3267901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) @@ -582,17 +588,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2151059 # Request fanout histogram +system.membus.snoop_fanout::samples 2150005 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2151059 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2151059 # Request fanout histogram +system.membus.snoop_fanout::total 2150005 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 67605a567..69fe46592 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962608 # Number of seconds simulated -sim_ticks 1962608482500 # Number of ticks simulated -final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.982585 # Number of seconds simulated +sim_ticks 1982585357000 # Number of ticks simulated +final_tick 1982585357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019388 # Simulator instruction rate (inst/s) -host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32859851956 # Simulator tick rate (ticks/s) -host_mem_usage 375280 # Number of bytes of host memory used -host_seconds 59.73 # Real time elapsed on the host -sim_insts 60884587 # Number of instructions simulated -sim_ops 60884587 # Number of ops (including micro ops) simulated +host_inst_rate 1043358 # Simulator instruction rate (inst/s) +host_op_rate 1043358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33918612914 # Simulator tick rate (ticks/s) +host_mem_usage 377952 # Number of bytes of host memory used +host_seconds 58.45 # Real time elapsed on the host +sim_insts 60985541 # Number of instructions simulated +sim_ops 60985541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 804544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24689088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 59456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 522432 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory -system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26076480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 804544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 59456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7738240 # Number of bytes written to this memory +system.physmem.bytes_written::total 7738240 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12571 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8163 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406729 # Number of read requests accepted -system.physmem.writeReqs 120393 # Number of write requests accepted -system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 407445 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120910 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120910 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 405805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12452976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13152765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29989 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 435795 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3903106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3903106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3903106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 405805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12452976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17055871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407445 # Number of read requests accepted +system.physmem.writeReqs 120910 # Number of write requests accepted +system.physmem.readBursts 407445 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120910 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26068672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue +system.physmem.bytesWritten 7736640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26076480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7738240 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25025 # Per bank write bursts -system.physmem.perBankRdBursts::1 25421 # Per bank write bursts -system.physmem.perBankRdBursts::2 25447 # Per bank write bursts -system.physmem.perBankRdBursts::3 24899 # Per bank write bursts -system.physmem.perBankRdBursts::4 25181 # Per bank write bursts -system.physmem.perBankRdBursts::5 25235 # Per bank write bursts -system.physmem.perBankRdBursts::6 25799 # Per bank write bursts -system.physmem.perBankRdBursts::7 25539 # Per bank write bursts -system.physmem.perBankRdBursts::8 25681 # Per bank write bursts -system.physmem.perBankRdBursts::9 25348 # Per bank write bursts -system.physmem.perBankRdBursts::10 25259 # Per bank write bursts -system.physmem.perBankRdBursts::11 25592 # Per bank write bursts -system.physmem.perBankRdBursts::12 25653 # Per bank write bursts -system.physmem.perBankRdBursts::13 25554 # Per bank write bursts -system.physmem.perBankRdBursts::14 25887 # Per bank write bursts -system.physmem.perBankRdBursts::15 25094 # Per bank write bursts -system.physmem.perBankWrBursts::0 7701 # Per bank write bursts -system.physmem.perBankWrBursts::1 7641 # Per bank write bursts -system.physmem.perBankWrBursts::2 7454 # Per bank write bursts -system.physmem.perBankWrBursts::3 6926 # Per bank write bursts -system.physmem.perBankWrBursts::4 7165 # Per bank write bursts -system.physmem.perBankWrBursts::5 7117 # Per bank write bursts -system.physmem.perBankWrBursts::6 7626 # Per bank write bursts -system.physmem.perBankWrBursts::7 7252 # Per bank write bursts -system.physmem.perBankWrBursts::8 7527 # Per bank write bursts -system.physmem.perBankWrBursts::9 7238 # Per bank write bursts -system.physmem.perBankWrBursts::10 7225 # Per bank write bursts -system.physmem.perBankWrBursts::11 7418 # Per bank write bursts -system.physmem.perBankWrBursts::12 7843 # Per bank write bursts -system.physmem.perBankWrBursts::13 8207 # Per bank write bursts -system.physmem.perBankWrBursts::14 8447 # Per bank write bursts -system.physmem.perBankWrBursts::15 7584 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48696 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25232 # Per bank write bursts +system.physmem.perBankRdBursts::1 25377 # Per bank write bursts +system.physmem.perBankRdBursts::2 25433 # Per bank write bursts +system.physmem.perBankRdBursts::3 24853 # Per bank write bursts +system.physmem.perBankRdBursts::4 25156 # Per bank write bursts +system.physmem.perBankRdBursts::5 25421 # Per bank write bursts +system.physmem.perBankRdBursts::6 25501 # Per bank write bursts +system.physmem.perBankRdBursts::7 25341 # Per bank write bursts +system.physmem.perBankRdBursts::8 25248 # Per bank write bursts +system.physmem.perBankRdBursts::9 25578 # Per bank write bursts +system.physmem.perBankRdBursts::10 25745 # Per bank write bursts +system.physmem.perBankRdBursts::11 25922 # Per bank write bursts +system.physmem.perBankRdBursts::12 25991 # Per bank write bursts +system.physmem.perBankRdBursts::13 25558 # Per bank write bursts +system.physmem.perBankRdBursts::14 25312 # Per bank write bursts +system.physmem.perBankRdBursts::15 25655 # Per bank write bursts +system.physmem.perBankWrBursts::0 7850 # Per bank write bursts +system.physmem.perBankWrBursts::1 7774 # Per bank write bursts +system.physmem.perBankWrBursts::2 7467 # Per bank write bursts +system.physmem.perBankWrBursts::3 6887 # Per bank write bursts +system.physmem.perBankWrBursts::4 7102 # Per bank write bursts +system.physmem.perBankWrBursts::5 7345 # Per bank write bursts +system.physmem.perBankWrBursts::6 7434 # Per bank write bursts +system.physmem.perBankWrBursts::7 7145 # Per bank write bursts +system.physmem.perBankWrBursts::8 7156 # Per bank write bursts +system.physmem.perBankWrBursts::9 7306 # Per bank write bursts +system.physmem.perBankWrBursts::10 7741 # Per bank write bursts +system.physmem.perBankWrBursts::11 8153 # Per bank write bursts +system.physmem.perBankWrBursts::12 8257 # Per bank write bursts +system.physmem.perBankWrBursts::13 7909 # Per bank write bursts +system.physmem.perBankWrBursts::14 7539 # Per bank write bursts +system.physmem.perBankWrBursts::15 7820 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 1962561950500 # Total gap between requests +system.physmem.numWrRetry 21 # Number of times write queue was full causing retry +system.physmem.totGap 1982577992500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406729 # Read request sizes (log2) +system.physmem.readPktSize::6 407445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120393 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120910 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,181 +158,177 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 500.345036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 302.441164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.330516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16348 24.20% 24.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12278 18.17% 42.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5298 7.84% 50.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3150 4.66% 54.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2433 3.60% 58.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4298 6.36% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1531 2.27% 67.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2195 3.25% 70.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20033 29.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67564 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5409 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.303198 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2854.593157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5406 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads -system.physmem.totQLat 2204423500 # Total ticks spent queuing -system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5409 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5409 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.348863 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.981514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.757339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4806 88.85% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 190 3.51% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 24 0.44% 92.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 50 0.92% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 37 0.68% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.11% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 18 0.33% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 42 0.78% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 29 0.54% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.06% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 162 3.00% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 4 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.07% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 10 0.18% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::312-319 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5409 # Writes before turning the bus around for reads +system.physmem.totQLat 2792890500 # Total ticks spent queuing +system.physmem.totMemAccLat 10430196750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6856.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25606.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing -system.physmem.readRowHits 363741 # Number of row buffer hits during reads -system.physmem.writeRowHits 96228 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes -system.physmem.avgGap 3723164.56 # Average gap between requests -system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.630269 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states -system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 363877 # Number of row buffer hits during reads +system.physmem.writeRowHits 96767 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes +system.physmem.avgGap 3752359.67 # Average gap between requests +system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 243303480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132754875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578049200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382345920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72929786580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1125575674500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1330334513115 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.011108 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1872213779250 # Time in different power states +system.physmem_0.memoryStateTime::REF 66202760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 44165427000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.683332 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states -system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states +system.physmem_1.actEnergy 267480360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145946625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1599070200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 400988880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74043413820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124598800250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1330548298695 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.118945 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1870589115500 # Time in different power states +system.physmem_1.memoryStateTime::REF 66202760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45790077000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7500026 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 7416955 # DTB read hits +system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5074087 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.read_accesses 490672 # DTB read accesses +system.cpu0.dtb.write_hits 5004564 # DTB write hits +system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12574113 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.write_accesses 187451 # DTB write accesses +system.cpu0.dtb.data_hits 12421519 # DTB hits +system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3504450 # ITB hits +system.cpu0.dtb.data_accesses 678123 # DTB accesses +system.cpu0.itb.fetch_hits 3482641 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3508321 # ITB accesses +system.cpu0.itb.fetch_accesses 3486512 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -345,91 +341,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923838721 # number of cpu cycles simulated +system.cpu0.numCycles 3964851833 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47783493 # Number of instructions committed -system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses -system.cpu0.num_func_calls 1203861 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44315744 # number of integer instructions -system.cpu0.num_fp_insts 211234 # number of float instructions -system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written -system.cpu0.num_mem_refs 12614351 # number of memory refs -system.cpu0.num_load_insts 7527207 # Number of load instructions -system.cpu0.num_store_insts 5087144 # Number of store instructions -system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles -system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles -system.cpu0.Branches 7204257 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction -system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction -system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction -system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47325532 # Number of instructions committed +system.cpu0.committedOps 47325532 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43895499 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 207106 # Number of float alu accesses +system.cpu0.num_func_calls 1185742 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5567031 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43895499 # number of integer instructions +system.cpu0.num_fp_insts 207106 # number of float instructions +system.cpu0.num_int_register_reads 60349527 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32725613 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 100583 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 102386 # number of times the floating registers were written +system.cpu0.num_mem_refs 12461430 # number of memory refs +system.cpu0.num_load_insts 7443904 # Number of load instructions +system.cpu0.num_store_insts 5017526 # Number of store instructions +system.cpu0.num_idle_cycles 3700363584.987226 # Number of idle cycles +system.cpu0.num_busy_cycles 264488248.012774 # Number of busy cycles +system.cpu0.not_idle_fraction 0.066708 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.933292 # Percentage of idle cycles +system.cpu0.Branches 7135463 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2703242 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31183402 65.88% 71.59% # Class of executed instruction +system.cpu0.op_class::IntMult 51823 0.11% 71.70% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25571 0.05% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.76% # Class of executed instruction +system.cpu0.op_class::MemRead 7617030 16.09% 87.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 5023630 10.61% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 727776 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47792093 # Class of executed instruction +system.cpu0.op_class::total 47334130 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6807 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 162813 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55930 40.12% 40.12% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1978 1.42% 41.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80947 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139423 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55420 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1978 1.75% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54986 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 112952 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1904955657000 96.09% 96.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92166000 0.00% 96.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 765642500 0.04% 96.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 319863500 0.02% 96.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 76292557500 3.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1982425886500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990881 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679284 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810139 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -461,124 +457,124 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 523 0.35% 0.35% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3026 2.05% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132550 89.80% 92.24% # number of callpals executed +system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::rti 4327 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 150081 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches +system.cpu0.kern.callpal::total 147613 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6866 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1282 -system.cpu0.kern.mode_good::user 1282 +system.cpu0.kern.mode_good::kernel 1281 +system.cpu0.kern.mode_good::user 1281 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186572 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314472 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1977675856500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3900112000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3073 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1181794 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51530574 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51530574 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6418852 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6418852 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4665452 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4665452 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140662 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140662 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148383 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148383 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11084304 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11084304 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11084304 # number of overall hits -system.cpu0.dcache.overall_hits::total 11084304 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 939259 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 939259 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251797 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251797 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13671 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13671 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5399 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5399 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1191056 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1191056 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1191056 # number of overall misses -system.cpu0.dcache.overall_misses::total 1191056 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 28901225000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 28901225000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10875412500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10875412500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47710000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 47710000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 39776637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 39776637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 39776637500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 39776637500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7358111 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7358111 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4917249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4917249 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154333 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154333 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153782 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153782 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12275360 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12275360 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12275360 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12275360 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127649 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127649 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051207 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051207 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035108 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035108 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097028 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097028 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097028 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097028 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # average overall miss latency +system.cpu0.kern.swap_context 3027 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1172695 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.333942 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11237582 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1173114 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.579275 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 143226500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333942 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50910847 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50910847 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6343242 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6343242 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4601243 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4601243 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138155 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138155 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145460 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 145460 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10944485 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10944485 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10944485 # number of overall hits +system.cpu0.dcache.overall_hits::total 10944485 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 934191 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 934191 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 249028 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 249028 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5734 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5734 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1183219 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1183219 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1183219 # number of overall misses +system.cpu0.dcache.overall_misses::total 1183219 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42879044000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42879044000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16797420000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16797420000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151036000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 151036000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 96889000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 96889000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 59676464000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 59676464000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 59676464000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 59676464000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277433 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7277433 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850271 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4850271 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151733 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 151733 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151194 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 151194 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12127704 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12127704 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12127704 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12127704 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128368 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128368 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051343 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051343 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089486 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037925 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037925 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097563 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097563 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097563 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097563 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45899.654353 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 45899.654353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67451.933116 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67451.933116 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11123.582265 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11123.582265 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16897.279386 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16897.279386 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50435.687730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50435.687730 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,126 +583,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 679941 # number of writebacks -system.cpu0.dcache.writebacks::total 679941 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939259 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939259 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251797 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251797 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13671 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13671 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5399 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191056 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1191056 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191056 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1191056 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10829 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17939 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27961966000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27961966000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10623615500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10623615500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136697000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136697000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42311000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42311000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38585581500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38585581500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38585581500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38585581500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1492228000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1492228000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2319869500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2319869500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3812097500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3812097500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127649 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127649 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 672708 # number of writebacks +system.cpu0.dcache.writebacks::total 672708 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934191 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 934191 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249028 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249028 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5734 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5734 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1183219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183219 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1183219 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41944853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41944853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16548392000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16548392000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137458000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137458000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58493245000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 58493245000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58493245000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 58493245000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1488672000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1488672000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2316060500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2316060500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3804732500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3804732500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128368 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089486 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097563 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097563 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44899.654353 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44899.654353 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66451.933116 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66451.933116 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10123.582265 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10123.582265 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15897.279386 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15897.279386 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210086.367485 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210086.367485 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214768.221439 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214768.221439 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212911.723559 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212911.723559 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 700401 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.179347 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 686863 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.493433 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 46646633 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 687375 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.861987 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 58997592500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.493433 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989245 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.989245 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits -system.cpu0.icache.overall_hits::total 47091062 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses -system.cpu0.icache.overall_misses::total 701031 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48021627 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48021627 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 46646633 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46646633 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46646633 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46646633 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46646633 # number of overall hits +system.cpu0.icache.overall_hits::total 46646633 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687497 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687497 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687497 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687497 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687497 # number of overall misses +system.cpu0.icache.overall_misses::total 687497 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10629492500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10629492500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10629492500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10629492500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10629492500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10629492500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47334130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47334130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47334130 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47334130 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47334130 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47334130 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15461.147467 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15461.147467 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15461.147467 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15461.147467 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -715,51 +711,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 701031 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 701031 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 701031 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 701031 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 701031 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 701031 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9316608000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9316608000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9316608000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9316608000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9316608000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9316608000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687497 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687497 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687497 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687497 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687497 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687497 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9941995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9941995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9941995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9941995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9941995500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9941995500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14461.147467 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2409623 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_hits 2508569 # DTB read hits +system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1749165 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.read_accesses 239364 # DTB read accesses +system.cpu1.dtb.write_hits 1828737 # DTB write hits +system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4158788 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.write_accesses 105248 # DTB write accesses +system.cpu1.dtb.data_hits 4337306 # DTB hits +system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1960477 # ITB hits +system.cpu1.dtb.data_accesses 344612 # DTB accesses +system.cpu1.itb.fetch_hits 1989876 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1961693 # ITB accesses +system.cpu1.itb.fetch_accesses 1991092 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -772,87 +768,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3925216965 # number of cpu cycles simulated +system.cpu1.numCycles 3965170714 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13101094 # Number of instructions committed -system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses -system.cpu1.num_func_calls 409417 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12083765 # number of integer instructions -system.cpu1.num_fp_insts 172106 # number of float instructions -system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written -system.cpu1.num_mem_refs 4182249 # number of memory refs -system.cpu1.num_load_insts 2423870 # Number of load instructions -system.cpu1.num_store_insts 1758379 # Number of store instructions -system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles -system.cpu1.Branches 1864071 # Number of branches fetched -system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction -system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction +system.cpu1.committedInsts 13660009 # Number of instructions committed +system.cpu1.committedOps 13660009 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12598388 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 178445 # Number of float alu accesses +system.cpu1.num_func_calls 429702 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1355296 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12598388 # number of integer instructions +system.cpu1.num_fp_insts 178445 # number of float instructions +system.cpu1.num_int_register_reads 17340989 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9240436 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 93179 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 95134 # number of times the floating registers were written +system.cpu1.num_mem_refs 4361445 # number of memory refs +system.cpu1.num_load_insts 2523214 # Number of load instructions +system.cpu1.num_store_insts 1838231 # Number of store instructions +system.cpu1.num_idle_cycles 3912374881.998026 # Number of idle cycles +system.cpu1.num_busy_cycles 52795832.001973 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013315 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986685 # Percentage of idle cycles +system.cpu1.Branches 1945174 # Number of branches fetched +system.cpu1.op_class::No_OpClass 733210 5.37% 5.37% # Class of executed instruction +system.cpu1.op_class::IntAlu 8079835 59.13% 64.50% # Class of executed instruction +system.cpu1.op_class::IntMult 22791 0.17% 64.67% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.67% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14367 0.11% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::MemRead 2597857 19.01% 83.80% # Class of executed instruction +system.cpu1.op_class::MemWrite 1839254 13.46% 97.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 374073 2.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13104456 # Class of executed instruction +system.cpu1.op_class::total 13663373 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2868 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 81018 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27534 38.52% 38.52% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 523 0.73% 42.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41447 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71475 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26667 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 523 0.95% 52.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26144 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55305 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1912303307000 96.46% 96.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705769500 0.04% 96.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 367699000 0.02% 96.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 69207844500 3.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1982584620000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968512 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.630781 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.773767 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -868,124 +864,124 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2064 2.79% 3.38% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed -system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65156 88.12% 91.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed +system.cpu1.kern.callpal::rti 3824 5.17% 99.76% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71137 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches -system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 889 -system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 424 -system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73942 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2112 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 911 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 447 +system.cpu1.kern.mode_switch_good::kernel 0.431345 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1986 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 165381 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.153030 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.331454 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 19415818500 0.98% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1728972000 0.09% 1.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1961439827500 98.93% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2065 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 173710 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.751289 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4161033 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 174222 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.883511 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90304766500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.751289 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940920 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940920 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1632527 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48591 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48591 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50409 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50409 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3878271 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3878271 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3878271 # number of overall hits -system.cpu1.dcache.overall_hits::total 3878271 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 117597 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 117597 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62279 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62279 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8857 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8857 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5813 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5813 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 179876 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 179876 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 179876 # number of overall misses -system.cpu1.dcache.overall_misses::total 179876 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1425631000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1425631000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1255840500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1255840500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80743500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1694806 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57448 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57448 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56222 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56222 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4058147 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4058147 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4058147 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4058147 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049759 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049759 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036747 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 17592927 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 17592927 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2337017 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2337017 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1705874 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1705874 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50407 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 50407 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53062 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 53062 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4042891 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4042891 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4042891 # number of overall hits +system.cpu1.dcache.overall_hits::total 4042891 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 123430 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 123430 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 65652 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 65652 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9249 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9249 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6101 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6101 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 189082 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 189082 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 189082 # number of overall misses +system.cpu1.dcache.overall_misses::total 189082 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1554368000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1554368000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1876323500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1876323500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84244000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84244000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 98989500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 98989500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3430691500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3430691500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3430691500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3430691500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2460447 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2460447 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1771526 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1771526 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59656 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 59656 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59163 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4231973 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4231973 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4231973 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4231973 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050166 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050166 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.037060 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.037060 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155039 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155039 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103122 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103122 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044679 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044679 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044679 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044679 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12593.113506 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12593.113506 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28579.837629 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28579.837629 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.444156 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.444156 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16225.127028 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16225.127028 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18143.934907 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18143.934907 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -994,128 +990,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 113645 # number of writebacks -system.cpu1.dcache.writebacks::total 113645 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117597 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 117597 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62279 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62279 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8857 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8857 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5813 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5813 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 179876 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 179876 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 179876 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 179876 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 119711 # number of writebacks +system.cpu1.dcache.writebacks::total 119711 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123430 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 123430 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65652 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 65652 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9249 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9249 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6101 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6101 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 189082 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 189082 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 189082 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 189082 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3347 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1430938000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1430938000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810671500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1810671500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74995000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74995000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 92888500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 92888500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3241609500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3241609500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3241609500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3241609500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23714500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 747400000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 747400000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 771114500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 771114500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050166 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037060 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037060 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155039 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155039 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103122 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103122 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044679 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044679 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11593.113506 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11593.113506 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27579.837629 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27579.837629 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.444156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.444156 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15225.127028 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15225.127028 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200970.338983 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 200970.338983 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223304.451748 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 223304.451748 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222543.867244 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222543.867244 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 313887 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 331160 # number of replacements +system.cpu1.icache.tags.tagsinuse 442.919388 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13331662 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 331672 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.195319 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1976558526500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.919388 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865077 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.865077 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 31 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits -system.cpu1.icache.overall_hits::total 12790016 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses -system.cpu1.icache.overall_misses::total 314441 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13995086 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13995086 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13331662 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13331662 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13331662 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13331662 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13331662 # number of overall hits +system.cpu1.icache.overall_hits::total 13331662 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 331712 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 331712 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 331712 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 331712 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 331712 # number of overall misses +system.cpu1.icache.overall_misses::total 331712 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4531331500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4531331500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4531331500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4531331500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4531331500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4531331500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13663374 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13663374 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13663374 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13663374 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13663374 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13663374 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024277 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024277 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024277 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024277 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024277 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024277 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13660.438875 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13660.438875 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13660.438875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13660.438875 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1124,30 +1120,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331712 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 331712 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 331712 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 331712 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 331712 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 331712 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4199619500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4199619500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4199619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4199619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4199619500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4199619500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024277 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024277 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024277 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12660.438875 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1161,45 +1157,45 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55595 # Transaction distribution -system.iobus.trans_dist::WriteResp 55595 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7379 # Transaction distribution +system.iobus.trans_dist::ReadResp 7379 # Transaction distribution +system.iobus.trans_dist::WriteReq 55683 # Transaction distribution +system.iobus.trans_dist::WriteResp 55683 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42670 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 82499 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2744123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13414000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1209,9 +1205,9 @@ system.iobus.reqLayer22.occupancy 155000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2454000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1219,52 +1215,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215099489 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28539000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.566806 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1775098751000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.566806 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035425 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035425 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses -system.iocache.demand_misses::total 174 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 174 # number of overall misses -system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22127883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22127883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428057606 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5428057606 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22127883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22127883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22127883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22127883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1273,40 +1269,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126445.045714 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126445.045714 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130632.884241 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130632.884241 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126445.045714 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126445.045714 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 18.333333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13044883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13044883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2830447616 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2830447616 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13044883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13044883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13044883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13044883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13377883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13377883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350457606 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350457606 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13377883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13377883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13377883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13377883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1315,195 +1311,195 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76445.045714 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80632.884241 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80632.884241 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341250 # number of replacements -system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use -system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35905885 # Number of tag accesses -system.l2c.tags.data_accesses 35905885 # Number of data accesses -system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits -system.l2c.Writeback_hits::total 793586 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits +system.l2c.tags.replacements 341926 # number of replacements +system.l2c.tags.tagsinuse 65167.982973 # Cycle average of tags in use +system.l2c.tags.total_refs 3685196 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.056049 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 12918028000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 54774.174056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.572445 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5374.369214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 120.511186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 38.356073 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.835788 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.082006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001839 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000585 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994385 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 516 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6300 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52705 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35906123 # Number of tag accesses +system.l2c.tags.data_accesses 35906123 # Number of data accesses +system.l2c.Writeback_hits::writebacks 792419 # number of Writeback hits +system.l2c.Writeback_hits::total 792419 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 557 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 39 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126818 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 46992 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173810 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 688011 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 313935 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1001946 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 665063 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 108615 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 773678 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 688011 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 791881 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 313935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155607 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949434 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 688011 # number of overall hits -system.l2c.overall_hits::cpu0.data 791881 # number of overall hits -system.l2c.overall_hits::cpu1.inst 313935 # number of overall hits -system.l2c.overall_hits::cpu1.data 155607 # number of overall hits -system.l2c.overall_hits::total 1949434 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2935 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4668 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 882 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 893 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1775 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115542 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6588 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122130 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 12999 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 505 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 271618 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 236 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 271854 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 12999 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387160 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6824 # number of demand (read+write) misses -system.l2c.demand_misses::total 407488 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941009 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764482 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.865350 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959544 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974816 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967136 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480915 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139213 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415606 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291677 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260159 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172987 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172987 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71556.285811 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71793.694690 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71646.178010 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71034.054054 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71513.455328 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71274.271845 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117140.858485 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121861.139369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117443.057297 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121479.185185 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113999.243205 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 119537.091988 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114006.107541 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197585.944115 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188466.101695 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197436.563021 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203268.082344 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 211804.152973 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205289.894558 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201014.941242 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 211009.379509 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202638.129834 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 292720 # Transaction distribution -system.membus.trans_dist::WriteReq 14043 # Transaction distribution -system.membus.trans_dist::WriteResp 14043 # Transaction distribution -system.membus.trans_dist::Writeback 120393 # Transaction distribution -system.membus.trans_dist::CleanEvict 261901 # Transaction distribution -system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution -system.membus.trans_dist::ReadExReq 122456 # Transaction distribution -system.membus.trans_dist::ReadExResp 121630 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution +system.membus.trans_dist::ReadReq 7204 # Transaction distribution +system.membus.trans_dist::ReadResp 292756 # Transaction distribution +system.membus.trans_dist::WriteReq 14131 # Transaction distribution +system.membus.trans_dist::WriteResp 14131 # Transaction distribution +system.membus.trans_dist::Writeback 120910 # Transaction distribution +system.membus.trans_dist::CleanEvict 262059 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16821 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11772 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7147 # Transaction distribution +system.membus.trans_dist::ReadExReq 123180 # Transaction distribution +system.membus.trans_dist::ReadExResp 122316 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285552 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42670 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1235830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1360657 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82499 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31156480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31238979 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21449 # Total snoops (count) -system.membus.snoop_fanout::samples 880387 # Request fanout histogram +system.membus.pkt_size::total 33897219 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22736 # Total snoops (count) +system.membus.snoop_fanout::samples 883364 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 883364 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 880387 # Request fanout histogram -system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 883364 # Request fanout histogram +system.membus.reqLayer0.occupancy 40609000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1325313892 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2193032106 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69837727 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 4790600 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2395468 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361643 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1180 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107021 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 913350 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1503335 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17046 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11835 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28881 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297634 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297634 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019209 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1080623 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 480853 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1918193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544327 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867106 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539630 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6869256 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43998144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118001405 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21229504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604166 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201833219 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 484490 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5237304 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.138719 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.345885 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4511205 86.14% 86.14% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 725687 13.86% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 408 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5237304 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3205453497 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1031366757 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1802104925 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 498533066 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 293884764 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5922aa080..2decdfb20 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922397 # Number of seconds simulated -sim_ticks 1922397182500 # Number of ticks simulated -final_tick 1922397182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.941266 # Number of seconds simulated +sim_ticks 1941266487500 # Number of ticks simulated +final_tick 1941266487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1085217 # Simulator instruction rate (inst/s) -host_op_rate 1085217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37124537063 # Simulator tick rate (ticks/s) -host_mem_usage 372212 # Number of bytes of host memory used -host_seconds 51.78 # Real time elapsed on the host -sim_insts 56195121 # Number of instructions simulated -sim_ops 56195121 # Number of ops (including micro ops) simulated +host_inst_rate 1056307 # Simulator instruction rate (inst/s) +host_op_rate 1056307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36524098946 # Simulator tick rate (ticks/s) +host_mem_usage 374096 # Number of bytes of host memory used +host_seconds 53.15 # Real time elapsed on the host +sim_insts 56143021 # Number of instructions simulated +sim_ops 56143021 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 848768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 848832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24855488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25707776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 848768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7409088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7409088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388407 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25705280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 848832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7407552 # Number of bytes written to this memory +system.physmem.bytes_written::total 7407552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13263 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388367 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401684 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115767 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115767 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 441515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12930756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13372770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441515 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3854088 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3854088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 441515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12930756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17226858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401684 # Number of read requests accepted -system.physmem.writeReqs 115767 # Number of write requests accepted -system.physmem.readBursts 401684 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115767 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25700352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7407168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25707776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7409088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 401645 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115743 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115743 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 437257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12803749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13241500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 437257 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3815835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3815835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 437257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12803749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17057335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401645 # Number of read requests accepted +system.physmem.writeReqs 115743 # Number of write requests accepted +system.physmem.readBursts 401645 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115743 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25697728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 7406016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25705280 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7407552 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25233 # Per bank write bursts -system.physmem.perBankRdBursts::1 25641 # Per bank write bursts -system.physmem.perBankRdBursts::2 25574 # Per bank write bursts -system.physmem.perBankRdBursts::3 25503 # Per bank write bursts -system.physmem.perBankRdBursts::4 24973 # Per bank write bursts -system.physmem.perBankRdBursts::5 24969 # Per bank write bursts -system.physmem.perBankRdBursts::6 24206 # Per bank write bursts -system.physmem.perBankRdBursts::7 24501 # Per bank write bursts -system.physmem.perBankRdBursts::8 25169 # Per bank write bursts -system.physmem.perBankRdBursts::9 24770 # Per bank write bursts -system.physmem.perBankRdBursts::10 25259 # Per bank write bursts -system.physmem.perBankRdBursts::11 24898 # Per bank write bursts -system.physmem.perBankRdBursts::12 24500 # Per bank write bursts -system.physmem.perBankRdBursts::13 25360 # Per bank write bursts -system.physmem.perBankRdBursts::14 25653 # Per bank write bursts -system.physmem.perBankRdBursts::15 25359 # Per bank write bursts -system.physmem.perBankWrBursts::0 7624 # Per bank write bursts -system.physmem.perBankWrBursts::1 7642 # Per bank write bursts -system.physmem.perBankWrBursts::2 7864 # Per bank write bursts -system.physmem.perBankWrBursts::3 7542 # Per bank write bursts -system.physmem.perBankWrBursts::4 7123 # Per bank write bursts -system.physmem.perBankWrBursts::5 6988 # Per bank write bursts -system.physmem.perBankWrBursts::6 6319 # Per bank write bursts -system.physmem.perBankWrBursts::7 6328 # Per bank write bursts -system.physmem.perBankWrBursts::8 7314 # Per bank write bursts -system.physmem.perBankWrBursts::9 6525 # Per bank write bursts -system.physmem.perBankWrBursts::10 7109 # Per bank write bursts -system.physmem.perBankWrBursts::11 6927 # Per bank write bursts -system.physmem.perBankWrBursts::12 7069 # Per bank write bursts -system.physmem.perBankWrBursts::13 7821 # Per bank write bursts -system.physmem.perBankWrBursts::14 7867 # Per bank write bursts -system.physmem.perBankWrBursts::15 7675 # Per bank write bursts +system.physmem.perBankRdBursts::0 25168 # Per bank write bursts +system.physmem.perBankRdBursts::1 25510 # Per bank write bursts +system.physmem.perBankRdBursts::2 25518 # Per bank write bursts +system.physmem.perBankRdBursts::3 25527 # Per bank write bursts +system.physmem.perBankRdBursts::4 25065 # Per bank write bursts +system.physmem.perBankRdBursts::5 24960 # Per bank write bursts +system.physmem.perBankRdBursts::6 24241 # Per bank write bursts +system.physmem.perBankRdBursts::7 24604 # Per bank write bursts +system.physmem.perBankRdBursts::8 25078 # Per bank write bursts +system.physmem.perBankRdBursts::9 24653 # Per bank write bursts +system.physmem.perBankRdBursts::10 25359 # Per bank write bursts +system.physmem.perBankRdBursts::11 24824 # Per bank write bursts +system.physmem.perBankRdBursts::12 24407 # Per bank write bursts +system.physmem.perBankRdBursts::13 25357 # Per bank write bursts +system.physmem.perBankRdBursts::14 25770 # Per bank write bursts +system.physmem.perBankRdBursts::15 25486 # Per bank write bursts +system.physmem.perBankWrBursts::0 7561 # Per bank write bursts +system.physmem.perBankWrBursts::1 7519 # Per bank write bursts +system.physmem.perBankWrBursts::2 7810 # Per bank write bursts +system.physmem.perBankWrBursts::3 7560 # Per bank write bursts +system.physmem.perBankWrBursts::4 7221 # Per bank write bursts +system.physmem.perBankWrBursts::5 6978 # Per bank write bursts +system.physmem.perBankWrBursts::6 6351 # Per bank write bursts +system.physmem.perBankWrBursts::7 6424 # Per bank write bursts +system.physmem.perBankWrBursts::8 7248 # Per bank write bursts +system.physmem.perBankWrBursts::9 6410 # Per bank write bursts +system.physmem.perBankWrBursts::10 7207 # Per bank write bursts +system.physmem.perBankWrBursts::11 6855 # Per bank write bursts +system.physmem.perBankWrBursts::12 6980 # Per bank write bursts +system.physmem.perBankWrBursts::13 7819 # Per bank write bursts +system.physmem.perBankWrBursts::14 7982 # Per bank write bursts +system.physmem.perBankWrBursts::15 7794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 1922385313500 # Total gap between requests +system.physmem.numWrRetry 23 # Number of times write queue was full causing retry +system.physmem.totGap 1941254508500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401684 # Read request sizes (log2) +system.physmem.readPktSize::6 401645 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115767 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401554 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115743 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401513 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,195 +148,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 514.603333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 307.690032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.700723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15764 24.50% 24.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11265 17.51% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5118 7.96% 49.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3016 4.69% 54.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2317 3.60% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1789 2.78% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1464 2.28% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1374 2.14% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22229 34.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64336 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.750735 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2955.508201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5096 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64921 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.908104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.461658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.215984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15228 23.46% 23.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11644 17.94% 41.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4997 7.70% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2980 4.59% 53.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2446 3.77% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4228 6.51% 63.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1452 2.24% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19883 30.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64921 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5102 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.697570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2954.645683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5099 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5099 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5099 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.697980 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.062005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.025558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4477 87.80% 87.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 19 0.37% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 190 3.73% 91.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 14 0.27% 92.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 27 0.53% 92.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 1.04% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.27% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.06% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.12% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.16% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.04% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.20% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.08% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 16 0.31% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 21 0.41% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 18 0.35% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 148 2.90% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.24% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.06% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.10% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 4 0.08% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 5 0.10% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 5 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5099 # Writes before turning the bus around for reads -system.physmem.totQLat 2147063750 # Total ticks spent queuing -system.physmem.totMemAccLat 9676463750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5346.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5102 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5102 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.681105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.154688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.203626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4492 88.04% 88.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 201 3.94% 91.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 29 0.57% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 48 0.94% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 38 0.74% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.12% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.22% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 38 0.74% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 34 0.67% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.02% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 159 3.12% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.10% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 8 0.16% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.08% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5102 # Writes before turning the bus around for reads +system.physmem.totQLat 2705942000 # Total ticks spent queuing +system.physmem.totMemAccLat 10234573250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6739.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24096.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25489.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing -system.physmem.readRowHits 359411 # Number of row buffer hits during reads -system.physmem.writeRowHits 93558 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes -system.physmem.avgGap 3715106.00 # Average gap between requests -system.physmem.pageHitRate 87.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236030760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128786625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564680000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372146400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64059295815 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097244171000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289166540360 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.604667 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1825128497250 # Time in different power states -system.physmem_0.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing +system.physmem.readRowHits 358859 # Number of row buffer hits during reads +system.physmem.writeRowHits 93466 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.75 # Row buffer hit rate for writes +system.physmem.avgGap 3752028.47 # Average gap between requests +system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239349600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130597500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1564625400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 372107520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 71640444015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101913691250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302654485925 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.035450 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832853481750 # Time in different power states +system.physmem_0.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33072782750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43583902000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250349400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136599375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567550400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377829360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65774789190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1095739352250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289407899735 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.730219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1822618194250 # Time in different power states -system.physmem_1.memoryStateTime::REF 64192960000 # Time in different power states +system.physmem_1.actEnergy 251453160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 137201625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567285200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 377751600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72584952255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101085183500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302797497980 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.109115 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831469435000 # Time in different power states +system.physmem_1.memoryStateTime::REF 64822940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35583085750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 44967962500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066440 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9058452 # DTB read hits +system.cpu.dtb.read_misses 10327 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6357400 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728858 # DTB read accesses +system.cpu.dtb.write_hits 6353129 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15423840 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15411581 # DTB hits +system.cpu.dtb.data_misses 11470 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973902 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020790 # DTB accesses +system.cpu.itb.fetch_hits 4975133 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978899 # ITB accesses +system.cpu.itb.fetch_accesses 4980143 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -349,37 +333,37 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3844794365 # number of cpu cycles simulated +system.cpu.numCycles 3882532975 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195121 # Number of instructions committed -system.cpu.committedOps 56195121 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066883 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483708 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469750 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066883 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71341331 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530727 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15476411 # number of memory refs -system.cpu.num_load_insts 9103258 # Number of load instructions -system.cpu.num_store_insts 6373153 # Number of store instructions -system.cpu.num_idle_cycles 3587818415.000134 # Number of idle cycles -system.cpu.num_busy_cycles 256975949.999866 # Number of busy cycles -system.cpu.not_idle_fraction 0.066837 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933163 # Percentage of idle cycles -system.cpu.Branches 8423975 # Number of branches fetched -system.cpu.op_class::No_OpClass 3201032 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36240615 64.48% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61007 0.11% 70.28% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.committedInsts 56143021 # Number of instructions committed +system.cpu.committedOps 56143021 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52016582 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1482534 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6465507 # number of instructions that are conditional controls +system.cpu.num_int_insts 52016582 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71267420 # number of times the integer registers were read +system.cpu.num_int_register_writes 38489507 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15464199 # number of memory refs +system.cpu.num_load_insts 9095305 # Number of load instructions +system.cpu.num_store_insts 6368894 # Number of store instructions +system.cpu.num_idle_cycles 3584401371.998154 # Number of idle cycles +system.cpu.num_busy_cycles 298131603.001846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076788 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923212 # Percentage of idle cycles +system.cpu.Branches 8418668 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199011 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36202225 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61032 0.11% 70.27% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction @@ -402,34 +386,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9330336 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6379227 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953006 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9322424 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6374975 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56206940 # Class of executed instruction +system.cpu.op_class::total 56154858 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211964 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74896 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73529 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212043 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74906 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106248 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183220 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73539 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73529 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149121 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858096797000 96.66% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 92317000 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 743733500 0.04% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 63463601000 3.30% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1922396448500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73539 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149144 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860736112500 95.85% 95.85% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92522000 0.00% 95.86% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 746030500 0.04% 95.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79691088500 4.11% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1941265753500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692253 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814086 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692145 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814016 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -465,113 +449,113 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175955 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175993 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192899 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu.kern.callpal::total 192944 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5907 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323509 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323345 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46413360000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5233781000 0.27% 2.69% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1870749305500 97.31% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390740 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14051600 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391252 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099968 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392117 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 48524962500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5595783500 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887145005500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1390004 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.973850 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14040102 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390516 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.097045 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 143374500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.973850 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999949 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999949 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63162665 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63162665 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816092 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816092 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853262 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853262 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669354 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669354 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669354 # number of overall hits -system.cpu.dcache.overall_hits::total 13669354 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069466 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069466 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304560 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304560 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374026 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374026 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374026 # number of overall misses -system.cpu.dcache.overall_misses::total 1374026 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30729736500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11677039000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228891000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42406775500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42406775500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42406775500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8885558 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157822 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043380 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043380 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043380 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043380 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28733.719913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28733.719913 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38340.684923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38340.684923 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.660404 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30863.153608 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63112993 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63112993 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7808536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7808536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5849272 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5849272 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199252 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199252 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13657808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13657808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13657808 # number of overall hits +system.cpu.dcache.overall_hits::total 13657808 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069028 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069028 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304257 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304257 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17249 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17249 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373285 # number of overall misses +system.cpu.dcache.overall_misses::total 1373285 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44750637500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17613913000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62364550500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62364550500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62364550500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8877564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6153529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200274 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199252 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15031093 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15031093 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15031093 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15031093 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120419 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049444 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086127 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091363 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091363 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091363 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091363 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41861.052751 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41861.052751 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57891.562068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57891.562068 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13479.448084 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45412.678723 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,120 +564,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835293 # number of writebacks -system.cpu.dcache.writebacks::total 835293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304560 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29660270500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11372479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11372479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 211647000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 211647000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41032749500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41032749500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41032749500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41032749500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450110500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450110500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2049565500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2049565500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3499676000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3499676000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120360 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120360 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27733.719913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27733.719913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37340.684923 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37340.684923 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12273.660404 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12273.660404 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.154401 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212390.207254 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212390.207254 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211078.166466 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211078.166466 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43681609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43681609500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17309656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17309656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215258000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215258000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60991265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 60991265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60991265500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 60991265500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450109500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450109500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2050243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2050243500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3500353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3500353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049444 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049444 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091363 # 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average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.010101 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.010101 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212394.436963 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212394.436963 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211080.805644 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211080.805644 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 55225516 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929183 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.434488 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 58555927500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 506.358595 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.988982 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.988982 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # 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number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929343 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929343 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929343 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929343 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929343 # number of overall misses +system.cpu.icache.overall_misses::total 929343 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13682743000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13682743000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13682743000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13682743000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13682743000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13682743000 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125211.424805 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125211.424805 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -845,125 +829,131 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74255 # number of writebacks -system.cpu.l2cache.writebacks::total 74255 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74231 # number of writebacks +system.cpu.l2cache.writebacks::total 74231 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 280 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 280 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116823 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116823 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13262 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13262 # 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number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 364500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 364500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7775812500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7775812500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 929982000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 929982000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16967384500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16967384500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 929982000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24743197000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25673179000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 929982000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24743197000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25673179000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363485500 # 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number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 922500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 922500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13715906000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13715906000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1604809000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1604809000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30996582000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30996582000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1604809000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44712488000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46317297000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1604809000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44712488000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46317297000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363484500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363484500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1939234000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1939234000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302718500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302718500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014276 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250273 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250273 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173286 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173286 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 28038.461538 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 28038.461538 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66560.630184 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66560.630184 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70123.812396 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62386.053446 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.154401 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200890.207254 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199160.193004 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199160.193004 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383901 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014272 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173296 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173296 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117432.712889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120998.944432 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113975.202144 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.010101 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200894.436963 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199162.907797 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199162.907797 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4638553 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2318842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1135 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1135 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 951075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1744381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 950299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1744757 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304543 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 928977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929343 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086450 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2786015 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205333 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6991348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59453248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142553556 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 202006804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419801 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5075497 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.082676 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.275393 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787117 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4203130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6990247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142457836 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201934508 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419768 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5074727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029056 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4655873 91.73% 91.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 419624 8.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5070439 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4288 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5075497 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3168054500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5074727 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3166927500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1393465500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394014500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098643000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2097540500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -979,9 +969,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 51202 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51205 # Transaction distribution +system.iobus.trans_dist::WriteResp 51205 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -993,11 +983,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1009,11 +999,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4773000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1035,23 +1025,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216066756 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215085744 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342844 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.339381 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756461860000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342844 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083928 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083928 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1774103808000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.339381 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083711 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083711 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1065,14 +1055,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21632883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21632883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907244873 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907244873 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21632883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21632883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21632883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21632883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21913883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21913883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427871861 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5427871861 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21913883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21913883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21913883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21913883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1089,14 +1079,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125045.566474 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125045.566474 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118098.885084 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118098.885084 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125045.566474 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126669.843931 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126669.843931 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130628.414059 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130628.414059 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126669.843931 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1115,14 +1105,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12982883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12982883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829644873 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12982883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12982883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12982883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13263883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13263883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350271861 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13263883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13263883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13263883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1131,59 +1121,59 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75045.566474 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68098.885084 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76669.843931 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80628.414059 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292339 # Transaction distribution -system.membus.trans_dist::WriteReq 9650 # Transaction distribution -system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115767 # Transaction distribution -system.membus.trans_dist::CleanEvict 261512 # Transaction distribution +system.membus.trans_dist::ReadResp 292325 # Transaction distribution +system.membus.trans_dist::WriteReq 9653 # Transaction distribution +system.membus.trans_dist::WriteResp 9653 # Transaction distribution +system.membus.trans_dist::Writeback 115743 # Transaction distribution +system.membus.trans_dist::CleanEvict 261495 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116704 # Transaction distribution -system.membus.trans_dist::ReadExResp 116704 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285409 # Transaction distribution +system.membus.trans_dist::ReadExReq 116679 # Transaction distribution +system.membus.trans_dist::ReadExResp 116679 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285395 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139625 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172785 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172672 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30503700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1297489 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499692 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33161428 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33157420 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837831 # Request fanout histogram +system.membus.snoop_fanout::samples 837762 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837831 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837762 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837831 # Request fanout histogram -system.membus.reqLayer0.occupancy 30056000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837762 # Request fanout histogram +system.membus.reqLayer0.occupancy 30061000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1285352189 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1285186893 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143948368 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143459620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72076390 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69854947 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 80deda855..14fab3b83 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 714694 # Simulator instruction rate (inst/s) -host_op_rate 870026 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13935517761 # Simulator tick rate (ticks/s) -host_mem_usage 573808 # Number of bytes of host memory used -host_seconds 199.77 # Real time elapsed on the host +host_inst_rate 1159279 # Simulator instruction rate (inst/s) +host_op_rate 1411237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22604281025 # Simulator tick rate (ticks/s) +host_mem_usage 628452 # Number of bytes of host memory used +host_seconds 123.16 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,9 +403,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor @@ -428,8 +428,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits @@ -535,12 +535,18 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks system.cpu.l2cache.writebacks::total 101949 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -548,28 +554,28 @@ system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Tr system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram +system.cpu.toL2Bus.snoops 182974 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -678,7 +684,7 @@ system.membus.trans_dist::ReadResp 74202 # Tr system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::Writeback 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -692,9 +698,9 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -746,13 +752,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index b13c4e56a..6c9ee9f79 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,66 +4,70 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1155692 # Simulator instruction rate (inst/s) -host_op_rate 1408193 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22061708570 # Simulator tick rate (ticks/s) -host_mem_usage 584036 # Number of bytes of host memory used -host_seconds 127.05 # Real time elapsed on the host +host_inst_rate 1151168 # Simulator instruction rate (inst/s) +host_op_rate 1402682 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21975358508 # Simulator tick rate (ticks/s) +host_mem_usage 637292 # Number of bytes of host memory used +host_seconds 127.55 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1090916 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9418084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146388 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1083988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1095972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9418276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 148052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1084052 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11740912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1090916 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146388 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1237304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8475264 # Number of bytes written to this memory +system.physmem.bytes_read::total 11747952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1095972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 148052 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1244024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8467328 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8492828 # Number of bytes written to this memory +system.physmem.bytes_written::total 8484892 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147677 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147680 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16959 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192600 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132426 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192710 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132302 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136817 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136693 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 389210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3360128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 391014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3360196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386762 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4188852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3023754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4191364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 391014 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3020923 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3030020 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3023754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3027189 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3020923 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3366380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 391014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3366448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386776 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7218873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7218553 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -367,8 +371,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511204 # number of writebacks -system.cpu0.dcache.writebacks::total 511204 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511149 # number of writebacks +system.cpu0.dcache.writebacks::total 511149 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use @@ -427,9 +431,9 @@ system.cpu0.l2cache.prefetcher.pfRemovedFull 0 system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 252605 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3093887 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.total_refs 3066089 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.510039 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.406624 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor @@ -454,13 +458,13 @@ system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582 system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 60120327 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 60120327 # Number of data accesses +system.cpu0.l2cache.tags.tag_accesses 59674327 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59674327 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511204 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511204 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::writebacks 511149 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511149 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits @@ -505,8 +509,8 @@ system.cpu0.l2cache.overall_misses::total 348765 # n system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511204 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511204 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511149 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511149 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses) @@ -558,15 +562,21 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192999 # number of writebacks -system.cpu0.l2cache.writebacks::total 192999 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192992 # number of writebacks +system.cpu0.l2cache.writebacks::total 192992 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720205 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860284 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 118049 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 117943 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511204 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1292017 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511149 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1264197 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution @@ -574,28 +584,28 @@ system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # T system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348291 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402034 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395204 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5791961 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5764086 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887684 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80884164 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152063428 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 327822 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4022806 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.061160 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.239623 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152059908 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 522626 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4217611 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.044172 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.205599 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3776773 93.88% 93.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 246033 6.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031417 95.59% 95.59% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 186088 4.41% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 106 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4022806 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4217611 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -873,8 +883,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120813 # number of writebacks -system.cpu1.dcache.writebacks::total 120813 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120812 # number of writebacks +system.cpu1.dcache.writebacks::total 120812 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use @@ -932,9 +942,9 @@ system.cpu1.l2cache.prefetcher.pfRemovedFull 0 system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 48465 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1307502 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.total_refs 1296358 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.648137 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.472151 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor @@ -957,13 +967,13 @@ system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338 system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24723530 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24723530 # Number of data accesses +system.cpu1.l2cache.tags.tag_accesses 24545002 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24545002 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120813 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120813 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::writebacks 120812 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120812 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits @@ -1008,8 +1018,8 @@ system.cpu1.l2cache.overall_misses::total 131449 # n system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120813 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120813 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120812 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120812 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) @@ -1061,15 +1071,21 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32917 # number of writebacks -system.cpu1.l2cache.writebacks::total 32917 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32915 # number of writebacks +system.cpu1.l2cache.writebacks::total 32915 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533423 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773258 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 88765 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 88649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 116 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120813 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 594498 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120812 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 583341 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution @@ -1077,28 +1093,28 @@ system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # T system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571497 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778746 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776513 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2368937 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2357779 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873326 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873262 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56440062 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 568500 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2040956 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.248991 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.432428 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56439998 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 273409 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1745865 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.067447 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.251059 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1532777 75.10% 75.10% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 508179 24.90% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1628228 93.26% 93.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 117521 6.73% 99.99% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 116 0.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2040956 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1745865 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1202,109 +1218,114 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 106825 # number of replacements -system.l2c.tags.tagsinuse 62089.721630 # Cycle average of tags in use -system.l2c.tags.total_refs 288805 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167355 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.725703 # Average number of references to valid blocks. +system.l2c.tags.replacements 106968 # number of replacements +system.l2c.tags.tagsinuse 62096.352232 # Cycle average of tags in use +system.l2c.tags.total_refs 248810 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167499 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.485442 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 47734.864298 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 47767.595021 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.041981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7941.182718 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4069.651943 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1613.022165 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 726.922600 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.728376 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7914.071704 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4068.609194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1612.456889 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 728.691105 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.728876 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.121173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.062098 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.024613 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011092 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.947414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.120759 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.062082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.024604 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.947515 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60523 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60524 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1889 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45532 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1892 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13030 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45506 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.923508 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5581048 # Number of tag accesses -system.l2c.tags.data_accesses 5581048 # Number of data accesses -system.l2c.Writeback_hits::writebacks 225916 # number of Writeback hits -system.l2c.Writeback_hits::total 225916 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 72 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 362 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 60 # number of SCUpgradeReq hits +system.l2c.tags.occ_task_id_percent::1024 0.923523 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5237373 # Number of tag accesses +system.l2c.tags.data_accesses 5237373 # Number of data accesses +system.l2c.Writeback_hits::writebacks 225907 # number of Writeback hits +system.l2c.Writeback_hits::total 225907 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 289 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 360 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 59 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 14091 # number of ReadExReq hits +system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 14099 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17178 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17186 # number of ReadExReq hits system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28425 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76409 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 28346 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76399 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11464 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11380 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 127912 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11438 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11382 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 127799 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28425 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 90500 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28346 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 90498 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11464 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14467 # number of demand (read+write) hits -system.l2c.demand_hits::total 145090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11438 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14469 # number of demand (read+write) hits +system.l2c.demand_hits::total 144985 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28425 # number of overall hits -system.l2c.overall_hits::cpu0.data 90500 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28346 # number of overall hits +system.l2c.overall_hits::cpu0.data 90498 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11464 # number of overall hits -system.l2c.overall_hits::cpu1.data 14467 # number of overall hits -system.l2c.overall_hits::total 145090 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9984 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3297 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13281 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses +system.l2c.overall_hits::cpu1.inst 11438 # number of overall hits +system.l2c.overall_hits::cpu1.data 14469 # number of overall hits +system.l2c.overall_hits::total 144985 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9985 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3298 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13283 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1936 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136573 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::total 1937 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136565 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152409 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152401 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 16484 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 11221 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2277 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1138 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 31129 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 16563 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 11232 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2303 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1139 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 31247 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16484 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 147794 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2277 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16974 # number of demand (read+write) misses -system.l2c.demand_misses::total 183538 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 147797 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2303 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16975 # number of demand (read+write) misses +system.l2c.demand_misses::total 183648 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16484 # number of overall misses -system.l2c.overall_misses::cpu0.data 147794 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2277 # number of overall misses -system.l2c.overall_misses::cpu1.data 16974 # number of overall misses -system.l2c.overall_misses::total 183538 # number of overall misses -system.l2c.Writeback_accesses::writebacks 225916 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225916 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 16563 # number of overall misses +system.l2c.overall_misses::cpu0.data 147797 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2303 # number of overall misses +system.l2c.overall_misses::cpu1.data 16975 # number of overall misses +system.l2c.overall_misses::total 183648 # number of overall misses +system.l2c.Writeback_accesses::writebacks 225907 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225907 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 10274 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 3369 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13643 # number of UpgradeReq accesses(hits+misses) @@ -1317,60 +1338,63 @@ system.l2c.ReadExReq_accesses::total 169587 # nu system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.inst 44909 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 87630 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 42 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 87631 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 43 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.inst 13741 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12518 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 159041 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12521 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 159046 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 44909 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238294 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238295 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 13741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31441 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328628 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31444 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328633 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 44909 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238294 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238295 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 13741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31441 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328628 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971773 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978629 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.973466 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.926650 # miss rate for SCUpgradeReq accesses +system.l2c.overall_accesses::cpu1.data 31444 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328633 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971871 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978925 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.973613 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.927873 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.993255 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966068 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.906474 # miss rate for ReadExReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.966567 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.906421 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.836865 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.898707 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.898660 # miss rate for ReadExReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.367053 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128050 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.165708 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090909 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.195729 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.368812 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128174 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.167601 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090967 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.196465 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.367053 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.620217 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.165708 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.539868 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.558498 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.368812 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.620227 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.167601 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.539849 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.558824 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.367053 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.620217 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.165708 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.539868 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.558498 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.368812 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.620227 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.167601 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.539849 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.558824 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1379,51 +1403,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96236 # number of writebacks -system.l2c.writebacks::total 96236 # number of writebacks +system.l2c.writebacks::writebacks 96112 # number of writebacks +system.l2c.writebacks::total 96112 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 43997 # Transaction distribution -system.membus.trans_dist::ReadResp 75378 # Transaction distribution +system.membus.trans_dist::ReadResp 75496 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::Writeback 132426 # Transaction distribution -system.membus.trans_dist::CleanEvict 15452 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40917 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15653 # Transaction distribution -system.membus.trans_dist::ReadExReq 196055 # Transaction distribution -system.membus.trans_dist::ReadExResp 151973 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31381 # Transaction distribution +system.membus.trans_dist::Writeback 132302 # Transaction distribution +system.membus.trans_dist::CleanEvict 8413 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60363 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40918 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15656 # Transaction distribution +system.membus.trans_dist::ReadExReq 196047 # Transaction distribution +system.membus.trans_dist::ReadExResp 151965 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31499 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 666955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 788339 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 897733 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660257 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 781641 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 890796 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17934348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18124130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17933452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18123234 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20456418 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20455522 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 587659 # Request fanout histogram +system.membus.snoop_fanout::samples 580848 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 587659 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 580848 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 587659 # Request fanout histogram +system.membus.snoop_fanout::total 580848 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1455,45 +1479,51 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks +system.toL2Bus.snoop_filter.tot_requests 874927 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 450220 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 131568 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9077 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 8809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225916 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 84734 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225907 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 41761 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1184948 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 427892 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1612840 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417842 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45103662 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 998221 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.036541 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.187632 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1153838 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 416020 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1569858 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685372 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417714 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45103086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180140 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1129657 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.285654 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.452250 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 961745 96.35% 96.35% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36476 3.65% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 807234 71.46% 71.46% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 322155 28.52% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 268 0.02% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 998221 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1129657 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 33ede6cdf..8e10ef807 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1188421 # Simulator instruction rate (inst/s) -host_op_rate 1446712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23172506899 # Simulator tick rate (ticks/s) -host_mem_usage 571472 # Number of bytes of host memory used -host_seconds 120.14 # Real time elapsed on the host +host_inst_rate 1171566 # Simulator instruction rate (inst/s) +host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22843865684 # Simulator tick rate (ticks/s) +host_mem_usage 624228 # Number of bytes of host memory used +host_seconds 121.87 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,9 +403,9 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor @@ -428,8 +428,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits @@ -535,12 +535,18 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks system.cpu.l2cache.writebacks::total 101949 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -548,28 +554,28 @@ system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Tr system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram +system.cpu.toL2Bus.snoops 182974 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -678,7 +684,7 @@ system.membus.trans_dist::ReadResp 74202 # Tr system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::Writeback 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -692,9 +698,9 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -746,13 +752,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 2deca7899..719058a40 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868749 # Number of seconds simulated -sim_ticks 2868748596000 # Number of ticks simulated -final_tick 2868748596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871120 # Number of seconds simulated +sim_ticks 2871119862000 # Number of ticks simulated +final_tick 2871119862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 740337 # Simulator instruction rate (inst/s) -host_op_rate 895502 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16150564794 # Simulator tick rate (ticks/s) -host_mem_usage 599396 # Number of bytes of host memory used -host_seconds 177.63 # Real time elapsed on the host -sim_insts 131502488 # Number of instructions simulated -sim_ops 159063828 # Number of ops (including micro ops) simulated +host_inst_rate 654504 # Simulator instruction rate (inst/s) +host_op_rate 791691 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14285860596 # Simulator tick rate (ticks/s) +host_mem_usage 653456 # Number of bytes of host memory used +host_seconds 200.98 # Real time elapsed on the host +sim_insts 131539806 # Number of instructions simulated +sim_ops 159111212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1184036 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1278116 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8584576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 111060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 568976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 412800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1136484 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1250788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8185344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 157844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 581136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 673536 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12141100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1184036 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 111060 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1295096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8715904 # Number of bytes written to this memory +system.physmem.bytes_read::total 11986604 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1136484 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 157844 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1294328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8637696 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8733468 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8655260 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20490 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134134 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1890 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 127896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 10524 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198852 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 136186 # Number of write requests responded to by this memory +system.physmem.num_reads::total 196438 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 134964 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140577 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139355 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 412736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 445531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2992446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 38714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 198336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 143895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4232194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 412736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 38714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 451450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3038225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395833 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 435645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2850924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 202407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 234590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4174888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395833 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3008476 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3044348 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3038225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3014594 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3008476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 412736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 451639 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2992446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 38714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 198350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 143895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7276541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198852 # Number of read requests accepted -system.physmem.writeReqs 140577 # Number of write requests accepted -system.physmem.readBursts 198852 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140577 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12717568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue -system.physmem.bytesWritten 8745536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12141100 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8733468 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 395833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 441748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2850924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 202421 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 234590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7189482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 196438 # Number of read requests accepted +system.physmem.writeReqs 139355 # Number of write requests accepted +system.physmem.readBursts 196438 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 139355 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12561984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue +system.physmem.bytesWritten 8668288 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11986604 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8655260 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48892 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12039 # Per bank write bursts -system.physmem.perBankRdBursts::1 11932 # Per bank write bursts -system.physmem.perBankRdBursts::2 12219 # Per bank write bursts -system.physmem.perBankRdBursts::3 12193 # Per bank write bursts -system.physmem.perBankRdBursts::4 20606 # Per bank write bursts -system.physmem.perBankRdBursts::5 12429 # Per bank write bursts -system.physmem.perBankRdBursts::6 12151 # Per bank write bursts -system.physmem.perBankRdBursts::7 12313 # Per bank write bursts -system.physmem.perBankRdBursts::8 12521 # Per bank write bursts -system.physmem.perBankRdBursts::9 12643 # Per bank write bursts -system.physmem.perBankRdBursts::10 11981 # Per bank write bursts -system.physmem.perBankRdBursts::11 11107 # Per bank write bursts -system.physmem.perBankRdBursts::12 11212 # Per bank write bursts -system.physmem.perBankRdBursts::13 11639 # Per bank write bursts -system.physmem.perBankRdBursts::14 10708 # Per bank write bursts -system.physmem.perBankRdBursts::15 11019 # Per bank write bursts -system.physmem.perBankWrBursts::0 8788 # Per bank write bursts -system.physmem.perBankWrBursts::1 8813 # Per bank write bursts -system.physmem.perBankWrBursts::2 9145 # Per bank write bursts -system.physmem.perBankWrBursts::3 8891 # Per bank write bursts -system.physmem.perBankWrBursts::4 8356 # Per bank write bursts -system.physmem.perBankWrBursts::5 8969 # Per bank write bursts -system.physmem.perBankWrBursts::6 8864 # Per bank write bursts -system.physmem.perBankWrBursts::7 8722 # Per bank write bursts -system.physmem.perBankWrBursts::8 9036 # Per bank write bursts -system.physmem.perBankWrBursts::9 9148 # Per bank write bursts -system.physmem.perBankWrBursts::10 8611 # Per bank write bursts -system.physmem.perBankWrBursts::11 8177 # Per bank write bursts -system.physmem.perBankWrBursts::12 8063 # Per bank write bursts -system.physmem.perBankWrBursts::13 7981 # Per bank write bursts -system.physmem.perBankWrBursts::14 7509 # Per bank write bursts -system.physmem.perBankWrBursts::15 7576 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 49183 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11406 # Per bank write bursts +system.physmem.perBankRdBursts::1 11655 # Per bank write bursts +system.physmem.perBankRdBursts::2 11752 # Per bank write bursts +system.physmem.perBankRdBursts::3 11575 # Per bank write bursts +system.physmem.perBankRdBursts::4 20585 # Per bank write bursts +system.physmem.perBankRdBursts::5 12467 # Per bank write bursts +system.physmem.perBankRdBursts::6 12095 # Per bank write bursts +system.physmem.perBankRdBursts::7 12222 # Per bank write bursts +system.physmem.perBankRdBursts::8 12044 # Per bank write bursts +system.physmem.perBankRdBursts::9 12120 # Per bank write bursts +system.physmem.perBankRdBursts::10 11627 # Per bank write bursts +system.physmem.perBankRdBursts::11 11103 # Per bank write bursts +system.physmem.perBankRdBursts::12 11588 # Per bank write bursts +system.physmem.perBankRdBursts::13 11719 # Per bank write bursts +system.physmem.perBankRdBursts::14 10853 # Per bank write bursts +system.physmem.perBankRdBursts::15 11470 # Per bank write bursts +system.physmem.perBankWrBursts::0 8250 # Per bank write bursts +system.physmem.perBankWrBursts::1 8603 # Per bank write bursts +system.physmem.perBankWrBursts::2 8782 # Per bank write bursts +system.physmem.perBankWrBursts::3 8359 # Per bank write bursts +system.physmem.perBankWrBursts::4 8401 # Per bank write bursts +system.physmem.perBankWrBursts::5 9093 # Per bank write bursts +system.physmem.perBankWrBursts::6 8866 # Per bank write bursts +system.physmem.perBankWrBursts::7 8828 # Per bank write bursts +system.physmem.perBankWrBursts::8 8708 # Per bank write bursts +system.physmem.perBankWrBursts::9 8716 # Per bank write bursts +system.physmem.perBankWrBursts::10 8411 # Per bank write bursts +system.physmem.perBankWrBursts::11 8212 # Per bank write bursts +system.physmem.perBankWrBursts::12 8400 # Per bank write bursts +system.physmem.perBankWrBursts::13 8108 # Per bank write bursts +system.physmem.perBankWrBursts::14 7766 # Per bank write bursts +system.physmem.perBankWrBursts::15 7939 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 39 # Number of times write queue was full causing retry -system.physmem.totGap 2868748135500 # Total gap between requests +system.physmem.numWrRetry 25 # Number of times write queue was full causing retry +system.physmem.totGap 2871119474000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9731 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 189093 # Read request sizes (log2) +system.physmem.readPktSize::6 186679 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136186 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 134964 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 137894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -180,158 +180,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 133 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88033 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.806754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 138.095781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.392225 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45989 52.24% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18103 20.56% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5912 6.72% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3673 4.17% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2470 2.81% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 1.78% 88.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 995 1.13% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 958 1.09% 90.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8368 9.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88033 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.243709 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 545.811163 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.110228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.616765 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.492638 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5748 84.59% 84.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 291 4.28% 88.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 178 2.62% 91.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 60 0.88% 92.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 79 1.16% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 156 2.30% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 28 0.41% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.18% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.10% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.13% 96.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 96.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 161 2.37% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.16% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.07% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads -system.physmem.totQLat 4722732900 # Total ticks spent queuing -system.physmem.totMemAccLat 8448582900 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 993560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23766.72 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.210195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.335340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.154059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46068 52.56% 52.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17715 20.21% 72.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6262 7.14% 79.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3427 3.91% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2480 2.83% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1647 1.88% 88.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 825 0.94% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 930 1.06% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8298 9.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87652 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6626 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.622698 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 552.814463 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6624 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6626 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.440990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.878741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.359150 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5426 81.89% 81.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 462 6.97% 88.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 72 1.09% 89.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 157 2.37% 92.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.48% 92.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 137 2.07% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.62% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.26% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 26 0.39% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 21 0.32% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 152 2.29% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.38% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.06% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6626 # Writes before turning the bus around for reads +system.physmem.totQLat 4505900396 # Total ticks spent queuing +system.physmem.totMemAccLat 8186169146 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 981405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22956.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42516.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41706.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.76 # Average write queue length when enqueuing -system.physmem.readRowHits 166188 # Number of row buffer hits during reads -system.physmem.writeRowHits 81139 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes -system.physmem.avgGap 8451688.38 # Average gap between requests -system.physmem.pageHitRate 73.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 346580640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 189106500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 825871800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 457151040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84248156880 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647343810500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920782998080 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.555658 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740372132788 # Time in different power states -system.physmem_0.memoryStateTime::REF 95793620000 # Time in different power states +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing +system.physmem.readRowHits 163849 # Number of row buffer hits during reads +system.physmem.writeRowHits 80221 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.22 # Row buffer hit rate for writes +system.physmem.avgGap 8550266.01 # Average gap between requests +system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 338884560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 184907250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 809296800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 448299360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85706052435 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647489846750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1922504718675 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.601510 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740606830696 # Time in different power states +system.physmem_0.memoryStateTime::REF 95872920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32582747712 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34639965804 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 318948840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 174029625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 724074000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 428334480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83576818575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1647932703750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920527229990 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.466501 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2741353761866 # Time in different power states -system.physmem_1.memoryStateTime::REF 95793620000 # Time in different power states +system.physmem_1.actEnergy 323764560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 176657250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 721687200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 429364800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84711391605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648362356250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922252653185 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.513716 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742063716846 # Time in different power states +system.physmem_1.memoryStateTime::REF 95872920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31595469384 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33181034404 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -387,57 +390,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7824 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7824 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1442 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6382 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7824 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7824 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7824 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10325.194401 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9252.413387 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6597.669693 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 6417 99.80% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 7 0.11% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 5019 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5019 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1041 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 3978 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 5019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5019 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 4056 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10869.452663 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9826.177645 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7625.006320 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 4042 99.65% 99.65% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10 0.25% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.07% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1109412500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1109412500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1109412500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5027 78.18% 78.18% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1403 21.82% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6430 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7824 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 4056 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3032 74.75% 74.75% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1024 25.25% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4056 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5019 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7824 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6430 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5019 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4056 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6430 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14254 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4056 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9075 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25236580 # DTB read hits -system.cpu0.dtb.read_misses 6707 # DTB read misses -system.cpu0.dtb.write_hits 18793560 # DTB write hits -system.cpu0.dtb.write_misses 1117 # DTB write misses +system.cpu0.dtb.read_hits 23515104 # DTB read hits +system.cpu0.dtb.read_misses 4346 # DTB read misses +system.cpu0.dtb.write_hits 17278792 # DTB write hits +system.cpu0.dtb.write_misses 673 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3444 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2434 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1747 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1554 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25243287 # DTB read accesses -system.cpu0.dtb.write_accesses 18794677 # DTB write accesses +system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23519450 # DTB read accesses +system.cpu0.dtb.write_accesses 17279465 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 44030140 # DTB hits -system.cpu0.dtb.misses 7824 # DTB misses -system.cpu0.dtb.accesses 44037964 # DTB accesses +system.cpu0.dtb.hits 40793896 # DTB hits +system.cpu0.dtb.misses 5019 # DTB misses +system.cpu0.dtb.accesses 40798915 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -467,40 +469,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3348 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10655.874786 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9465.333686 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5846.917058 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 920 39.45% 39.45% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1284 55.06% 94.51% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 84 3.60% 98.11% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 8 0.34% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1109040500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1109040500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1109040500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2305 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 237 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2068 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 1509 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10774.022531 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9696.406116 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7256.111559 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 1436 95.16% 95.16% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 61 4.04% 99.20% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 10 0.66% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 1509 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1272 84.29% 84.29% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 237 15.71% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1509 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 119342617 # ITB inst hits -system.cpu0.itb.inst_misses 3348 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 3814 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 111711640 # ITB inst hits +system.cpu0.itb.inst_misses 2305 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -509,179 +509,178 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1402 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 119345965 # ITB inst accesses -system.cpu0.itb.hits 119342617 # DTB hits -system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 119345965 # DTB accesses -system.cpu0.numCycles 5737497192 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 111713945 # ITB inst accesses +system.cpu0.itb.hits 111711640 # DTB hits +system.cpu0.itb.misses 2305 # DTB misses +system.cpu0.itb.accesses 111713945 # DTB accesses +system.cpu0.numCycles 5741309822 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 115654281 # Number of instructions committed -system.cpu0.committedOps 139770289 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123734710 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 12768418 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15718242 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123734710 # number of integer instructions -system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 227859200 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85998639 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 506429091 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52352971 # number of times the CC registers were written -system.cpu0.num_mem_refs 45168124 # number of memory refs -system.cpu0.num_load_insts 25488908 # Number of load instructions -system.cpu0.num_store_insts 19679216 # Number of store instructions -system.cpu0.num_idle_cycles 5463941135.084096 # Number of idle cycles -system.cpu0.num_busy_cycles 273556056.915905 # Number of busy cycles -system.cpu0.not_idle_fraction 0.047679 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.952321 # Percentage of idle cycles -system.cpu0.Branches 29223626 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 98271812 68.45% 68.45% # Class of executed instruction -system.cpu0.op_class::IntMult 109732 0.08% 68.53% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8207 0.01% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::MemRead 25488908 17.75% 86.29% # Class of executed instruction -system.cpu0.op_class::MemWrite 19679216 13.71% 100.00% # Class of executed instruction +system.cpu0.committedInsts 108455216 # Number of instructions committed +system.cpu0.committedOps 130919966 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 115934267 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4495 # Number of float alu accesses +system.cpu0.num_func_calls 12371356 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14793634 # number of instructions that are conditional controls +system.cpu0.num_int_insts 115934267 # number of integer instructions +system.cpu0.num_fp_insts 4495 # number of float instructions +system.cpu0.num_int_register_reads 213655151 # number of times the integer registers were read +system.cpu0.num_int_register_writes 80737315 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3581 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 474775860 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 48809609 # number of times the CC registers were written +system.cpu0.num_mem_refs 41877995 # number of memory refs +system.cpu0.num_load_insts 23749275 # Number of load instructions +system.cpu0.num_store_insts 18128720 # Number of store instructions +system.cpu0.num_idle_cycles 5480212444.901863 # Number of idle cycles +system.cpu0.num_busy_cycles 261097377.098137 # Number of busy cycles +system.cpu0.not_idle_fraction 0.045477 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.954523 # Percentage of idle cycles +system.cpu0.Branches 27818534 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2172 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 92606456 68.80% 68.80% # Class of executed instruction +system.cpu0.op_class::IntMult 105045 0.08% 68.88% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 7793 0.01% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu0.op_class::MemRead 23749275 17.64% 86.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 18128720 13.47% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143560148 # Class of executed instruction +system.cpu0.op_class::total 134599461 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 696532 # number of replacements -system.cpu0.dcache.tags.tagsinuse 491.305468 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43154174 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 697044 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 61.910258 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1135377000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.305468 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959581 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.959581 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88699037 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88699037 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23972048 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23972048 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18061887 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18061887 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318120 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318120 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365603 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365603 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362648 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362648 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 42033935 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 42033935 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42352055 # number of overall hits -system.cpu0.dcache.overall_hits::total 42352055 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 398676 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 398676 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324664 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324664 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 128643 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 128643 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21706 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21706 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19707 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19707 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 723340 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 723340 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 851983 # number of overall misses -system.cpu0.dcache.overall_misses::total 851983 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5067389500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5067389500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5162627000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5162627000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330228000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330228000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435506500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 435506500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1585500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1585500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10230016500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10230016500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10230016500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10230016500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24370724 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24370724 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18386551 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18386551 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446763 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446763 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387309 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387309 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382355 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42757275 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42757275 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43204038 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43204038 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017658 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017658 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.287945 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.287945 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056043 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056043 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051541 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016917 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016917 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019720 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019720 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.545656 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.545656 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15901.445802 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15901.445802 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.673639 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.673639 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22099.076470 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22099.076470 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 1796 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 588364 # number of replacements +system.cpu0.dcache.tags.tagsinuse 493.639030 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 40011095 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 588715 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 67.963437 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1836356000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.639030 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964139 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.964139 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.685547 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 82121594 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 82121594 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 22367728 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22367728 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16608644 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16608644 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300494 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 300494 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 340955 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 340955 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 337105 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 337105 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 38976372 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 38976372 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 39276866 # number of overall hits +system.cpu0.dcache.overall_hits::total 39276866 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 340778 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 340778 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 289444 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 289444 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 113643 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6274722500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5086196500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086196500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11360919000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11360919000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013895 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013895 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017129 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.209667 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.209667 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017156 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017156 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015275 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015275 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017286 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.017286 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13147.901719 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.901719 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18722.378845 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18722.378845 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17896.649814 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17896.649814 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16374.314295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16374.314295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.857674 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.857674 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13091.866210 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13091.866210 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13450.264224 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13450.264224 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196761.976187 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196761.976187 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171898.725582 # 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average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179135.579192 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179135.579192 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188936.139429 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 188936.139429 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1105972 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.454897 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 118236124 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1106484 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 106.857509 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13516114000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.454897 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998935 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998935 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 987035 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.323984 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 110724084 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 987547 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 112.120318 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14346160000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.323984 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998680 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998680 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 239791727 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 239791727 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 118236124 # 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number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10938029500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10938029500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10938029500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10938029500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 119342617 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 119342617 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 119342617 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 119342617 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 119342617 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 119342617 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009272 # 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average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10916.277659 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10916.277659 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,448 +840,451 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1106493 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1106493 # 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average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10286657500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10286657500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10286657500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10286657500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10286657500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10286657500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841098 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1841106 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1606259 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1606313 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 46 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 237750 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 269395 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16110.328705 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3241181 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 285612 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.348196 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 209215 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 245604 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16082.851224 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2813687 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 260278 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.810314 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7729.941983 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.543117 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.104661 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4692.501202 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1977.796502 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1707.441239 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.471798 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000155 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.286408 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.120715 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983296 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1097 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15114 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 275 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 382 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 431 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3320 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7689 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3966 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.066956 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922485 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 60150726 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 60150726 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7925 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3539 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 11464 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 508356 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 508356 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28387 # 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number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365472000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365472000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1464493 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1464493 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2004346000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2004346000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2385304000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2385304000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2775342500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2775342500 # 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miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.475877 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.911860 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.911860 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 7782.048512 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.435939 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.142248 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4563.552019 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1967.112212 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1769.560295 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.474979 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1270 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 259 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1410 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 11666 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.813904 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 52809362 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 52809362 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 5209 # 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mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103665 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228935 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17971.556886 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56080.431658 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20097.617754 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.617754 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14895.796214 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14895.796214 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 107499.363636 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 107499.363636 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40970.516581 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40970.516581 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43657.624649 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23317.538103 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23317.538103 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32523.378397 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46005.871762 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188761.945261 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165310.539933 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164398.725582 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164398.725582 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 177301.806597 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 164936.854273 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.244353 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 16343.396226 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83027.252039 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31352.992194 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31352.992194 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16210.561722 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16210.561722 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 583500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 583500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58928.736033 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58928.736033 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69856.539725 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28234.315480 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28234.315480 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44993.304398 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66891.537242 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189703.746298 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176816.216879 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171635.579192 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171635.579192 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181172.215662 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 174689.138577 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 64646 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1697156 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28719 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 871288 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1384656 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 292494 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87584 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111017 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 299003 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 286103 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1106493 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 579158 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3315880 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2563217 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10051 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22351 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5911499 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70851640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84881644 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14612 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 32580 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 155780476 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1106596 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4822448 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.211081 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.408076 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3288140 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1656034 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 25235 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 165607 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165490 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 117 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 54153 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1498300 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 629767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1193646 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 275537 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87023 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42073 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 110674 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 255600 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 251928 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 987556 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 494836 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3354 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2960662 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2239612 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6956 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14519 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5221749 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 63239672 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 73903156 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10332 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22088 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 137175248 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 821565 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4077224 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.054943 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.227994 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3804521 78.89% 78.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1017927 21.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3853328 94.51% 94.51% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 223779 5.49% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 117 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4822448 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2435282990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4077224 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2138731998 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113496000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115020156 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1668761500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1490356000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1211060981 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1049276975 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 4373000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14212986 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 8998497 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1311,60 +1315,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3357 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3357 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 663 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3357 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2587 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9934.866641 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9080.760096 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4767.740714 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 19 0.73% 0.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 1032 39.89% 40.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1082 41.82% 82.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 330 12.76% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 64 2.47% 97.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 39 1.51% 99.19% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 16 0.62% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 5 0.19% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2587 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1655632468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1655632468 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1655632468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1932 74.68% 74.68% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 655 25.32% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2587 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3357 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 6206 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6206 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1170 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5036 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6206 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6206 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6206 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10147.252747 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9159.943965 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4842.286315 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 42 0.84% 0.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 2213 44.22% 45.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1504 30.05% 75.10% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 1077 21.52% 96.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 52 1.04% 97.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 27 0.54% 98.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 32 0.64% 98.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 42 0.84% 99.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.10% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 7 0.14% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1704519828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1704519828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1704519828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3865 77.22% 77.22% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1140 22.78% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5005 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6206 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3357 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2587 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6206 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5005 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2587 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5944 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5005 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11211 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3844486 # DTB read hits -system.cpu1.dtb.read_misses 2847 # DTB read misses -system.cpu1.dtb.write_hits 3369243 # DTB write hits -system.cpu1.dtb.write_misses 510 # DTB write misses +system.cpu1.dtb.read_hits 5575996 # DTB read hits +system.cpu1.dtb.read_misses 5233 # DTB read misses +system.cpu1.dtb.write_hits 4889133 # DTB write hits +system.cpu1.dtb.write_misses 973 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3067 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3847333 # DTB read accesses -system.cpu1.dtb.write_accesses 3369753 # DTB write accesses +system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5581229 # DTB read accesses +system.cpu1.dtb.write_accesses 4890106 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7213729 # DTB hits -system.cpu1.dtb.misses 3357 # DTB misses -system.cpu1.dtb.accesses 7217086 # DTB accesses +system.cpu1.dtb.hits 10465129 # DTB hits +system.cpu1.dtb.misses 6206 # DTB misses +system.cpu1.dtb.accesses 10471335 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1394,43 +1402,46 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1746 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10678.410117 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9623.001262 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5682.967955 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 356 32.16% 32.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 499 45.08% 77.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 93.59% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 17 1.54% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.71% 97.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 12 1.08% 99.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.45% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 5 0.45% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1655094468 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1655094468 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1655094468 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2787 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2787 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 249 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2538 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2787 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1928 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11234.439834 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9816.231267 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6428.442620 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 752 39.00% 39.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 479 24.84% 63.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 554 28.73% 92.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 71 3.68% 96.27% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.10% 96.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.78% 97.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 0.88% 98.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.26% 98.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 26 1.35% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.16% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.10% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1928 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1705600828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1705600828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1705600828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1679 87.09% 87.09% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 249 12.91% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1928 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2787 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2787 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16180944 # ITB inst hits -system.cpu1.itb.inst_misses 1746 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1928 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1928 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 4715 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 23850368 # ITB inst hits +system.cpu1.itb.inst_misses 2787 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1439,178 +1450,179 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1894 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16182690 # ITB inst accesses -system.cpu1.itb.hits 16180944 # DTB hits -system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 16182690 # DTB accesses -system.cpu1.numCycles 5736568944 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 23853155 # ITB inst accesses +system.cpu1.itb.hits 23850368 # DTB hits +system.cpu1.itb.misses 2787 # DTB misses +system.cpu1.itb.accesses 23853155 # DTB accesses +system.cpu1.numCycles 5742239724 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15848207 # Number of instructions committed -system.cpu1.committedOps 19293539 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17383760 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 938177 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1786282 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17383760 # number of integer instructions -system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 31469136 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12170371 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 70461385 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6330901 # number of times the CC registers were written -system.cpu1.num_mem_refs 7446495 # number of memory refs -system.cpu1.num_load_insts 3955836 # Number of load instructions -system.cpu1.num_store_insts 3490659 # Number of store instructions -system.cpu1.num_idle_cycles 5686521745.715384 # Number of idle cycles -system.cpu1.num_busy_cycles 50047198.284615 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008724 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991276 # Percentage of idle cycles -system.cpu1.Branches 2803460 # Number of branches fetched -system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12144730 61.90% 61.90% # Class of executed instruction -system.cpu1.op_class::IntMult 26187 0.13% 62.03% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3277 0.02% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction -system.cpu1.op_class::MemRead 3955836 20.16% 82.21% # Class of executed instruction -system.cpu1.op_class::MemWrite 3490659 17.79% 100.00% # Class of executed instruction +system.cpu1.committedInsts 23084590 # Number of instructions committed +system.cpu1.committedOps 28191246 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 25227117 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses +system.cpu1.num_func_calls 1341368 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2715447 # number of instructions that are conditional controls +system.cpu1.num_int_insts 25227117 # number of integer instructions +system.cpu1.num_fp_insts 6988 # number of float instructions +system.cpu1.num_int_register_reads 45751310 # number of times the integer registers were read +system.cpu1.num_int_register_writes 17465196 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102291851 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9890204 # number of times the CC registers were written +system.cpu1.num_mem_refs 10752307 # number of memory refs +system.cpu1.num_load_insts 5706058 # Number of load instructions +system.cpu1.num_store_insts 5046249 # Number of store instructions +system.cpu1.num_idle_cycles 5671495056.418025 # Number of idle cycles +system.cpu1.num_busy_cycles 70744667.581975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012320 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987680 # Percentage of idle cycles +system.cpu1.Branches 4219564 # Number of branches fetched +system.cpu1.op_class::No_OpClass 167 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 17843088 62.32% 62.32% # Class of executed instruction +system.cpu1.op_class::IntMult 31349 0.11% 62.43% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3702 0.01% 62.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.44% # Class of executed instruction +system.cpu1.op_class::MemRead 5706058 19.93% 82.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 5046249 17.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 19620755 # Class of executed instruction +system.cpu1.op_class::total 28630613 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 186869 # number of replacements -system.cpu1.dcache.tags.tagsinuse 468.718276 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6945303 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187221 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.096816 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104852682500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.718276 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915465 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.915465 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14648138 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14648138 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3533706 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3533706 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3181686 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3181686 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48716 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48716 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78610 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78610 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70554 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70554 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6715392 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6715392 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6764108 # number of overall hits -system.cpu1.dcache.overall_hits::total 6764108 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133537 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133537 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 91347 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 91347 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30388 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30388 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17048 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17048 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23285 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23285 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 224884 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 224884 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255272 # number of overall misses -system.cpu1.dcache.overall_misses::total 255272 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1938354000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1938354000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2351393500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2351393500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 319800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544967000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 544967000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2548000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2548000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4289747500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4289747500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4289747500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4289747500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3667243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3667243 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3273033 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3273033 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79104 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79104 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95658 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95658 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93839 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93839 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6940276 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6940276 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7019380 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7019380 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036413 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036413 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027909 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027909 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.384153 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.384153 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178218 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178218 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248138 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248138 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032403 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.032403 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036367 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.036367 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14515.482600 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14515.482600 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25741.332501 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25741.332501 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18758.798686 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18758.798686 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23404.208718 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23404.208718 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2852 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 292035 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.567308 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 10109505 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 292547 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 34.556858 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105794397000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.567308 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917124 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.917124 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 21253597 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 21253597 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 5149175 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5149175 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4639914 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4639914 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 67630 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 67630 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103001 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 103001 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95778 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 95778 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9789089 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9789089 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9856719 # number of overall hits +system.cpu1.dcache.overall_hits::total 9856719 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 190277 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 190277 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 126690 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 126690 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 44121 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 44121 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18673 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18673 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23929 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23929 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 316967 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 316967 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 361088 # number of overall misses +system.cpu1.dcache.overall_misses::total 361088 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2557291000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2557291000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3433917500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3433917500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339355000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 339355000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 630190000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 630190000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5470500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5470500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5991208500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5991208500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5991208500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5991208500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 5339452 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 5339452 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4766604 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4766604 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 111751 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 111751 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 121674 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 121674 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 119707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 119707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 10106056 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 10106056 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 10217807 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 10217807 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035636 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035636 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.026579 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.026579 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.394815 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.394815 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153467 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.153467 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.199896 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.199896 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031364 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031364 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035339 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035339 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13439.832455 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13439.832455 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27104.881995 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27104.881995 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18173.566111 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18173.566111 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26335.826821 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26335.826821 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19075.378862 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19075.378862 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16804.614294 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16804.614294 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18901.679039 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18901.679039 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16592.100818 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16592.100818 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1619,147 +1631,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 116740 # number of writebacks -system.cpu1.dcache.writebacks::total 116740 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 267 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11810 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11810 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 267 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 267 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 267 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133270 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133270 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91347 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91347 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29613 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29613 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5238 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5238 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23285 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23285 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 224617 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 224617 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254230 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254230 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2508 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2508 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2155 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2155 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 4663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 4663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1799290500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1799290500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2260046500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2260046500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487726000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487726000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90112000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90112000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521727000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521727000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4059337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4059337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4547063000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4547063000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 302228000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 302228000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224553500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224553500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 526781500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 526781500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036341 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036341 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027909 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027909 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374355 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374355 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054758 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054758 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248138 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248138 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032364 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032364 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036218 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036218 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13501.091769 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13501.091769 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24741.332501 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24741.332501 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16469.996285 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16469.996285 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17203.512791 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17203.512791 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22406.141293 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22406.141293 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 180790 # number of writebacks +system.cpu1.dcache.writebacks::total 180790 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 404 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13063 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13063 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 404 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 404 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 404 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189873 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 189873 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 126690 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 126690 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 43074 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 43074 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5610 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5610 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23929 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23929 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 316563 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 316563 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 359637 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 359637 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3143 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3143 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2520 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5663 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5663 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2352437000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2352437000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3307227500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3307227500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 648806500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 648806500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97651500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97651500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606310000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606310000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5421500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5421500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5659664500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5659664500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6308471000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6308471000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 420340500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 420340500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 296300500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 296300500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 716641000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 716641000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035560 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035560 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026579 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026579 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.385446 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.385446 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046107 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046107 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.199896 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.199896 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031324 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031324 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035197 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035197 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12389.528790 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12389.528790 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26104.881995 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26104.881995 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15062.601569 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15062.601569 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17406.684492 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17406.684492 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25337.874546 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25337.874546 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18072.260782 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18072.260782 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17885.627188 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17885.627188 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120505.582137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120505.582137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104201.160093 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 104201.160093 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 112970.512546 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 112970.512546 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17878.477586 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17878.477586 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17541.217950 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17541.217950 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 133738.625517 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 133738.625517 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117579.563492 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 117579.563492 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 126547.942787 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 126547.942787 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 501529 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.573325 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15678898 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 502041 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.230314 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 84707327000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.573325 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973776 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973776 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 622414 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.397194 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 23227437 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 622926 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 37.287634 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 105696892000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.397194 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973432 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973432 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 32863919 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 32863919 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 15678898 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15678898 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15678898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15678898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15678898 # number of overall hits -system.cpu1.icache.overall_hits::total 15678898 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 502041 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 502041 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 502041 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 502041 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 502041 # number of overall misses -system.cpu1.icache.overall_misses::total 502041 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4374235500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4374235500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4374235500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4374235500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4374235500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4374235500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16180939 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16180939 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16180939 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16180939 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16180939 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16180939 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031027 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.031027 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031027 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.031027 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031027 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.031027 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8712.904922 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8712.904922 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8712.904922 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8712.904922 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 48323652 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 48323652 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 23227437 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 23227437 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 23227437 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 23227437 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 23227437 # number of overall hits +system.cpu1.icache.overall_hits::total 23227437 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 622926 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 622926 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 622926 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 622926 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 622926 # number of overall misses +system.cpu1.icache.overall_misses::total 622926 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5716886500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5716886500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5716886500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5716886500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5716886500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5716886500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23850363 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23850363 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23850363 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23850363 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23850363 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23850363 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026118 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.026118 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026118 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.026118 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026118 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.026118 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9177.472926 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9177.472926 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9177.472926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9177.472926 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1768,237 +1780,240 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 502041 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 502041 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 502041 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 502041 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 502041 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 502041 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622926 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 622926 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 622926 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 622926 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 622926 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 622926 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4123215000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4123215000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4123215000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4123215000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4123215000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4123215000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15225000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15225000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15225000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15225000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.031027 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.031027 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.031027 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8212.904922 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86016.949153 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86016.949153 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5405423500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5405423500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5405423500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5405423500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5405423500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5405423500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23975000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 23975000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026118 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.026118 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.026118 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8677.472926 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135451.977401 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135451.977401 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199800 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199800 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 437692 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 437708 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 61752 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 45885 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14962.501141 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1260771 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 60629 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.794851 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 85932 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 65711 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15078.335139 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1680940 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 81927 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.517534 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.992983 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.872865 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.082863 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2870.067957 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2148.313714 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 992.170760 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.546020 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000236 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 8770.071442 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.089565 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.088469 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3192.092107 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2103.725355 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1007.268201 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.535283 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000189 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.175175 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.131123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060557 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.913239 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1179 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13548 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 28 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1149 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.194830 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128401 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.061479 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.920309 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1082 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15126 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 297 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 350 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 424 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1569 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11689 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.071960 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2876390500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2001835233 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 5611466233 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22647500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 395196500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 417844000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 277400500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 277400500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22647500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 672597000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 695244500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041953 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950225 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950225 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962591 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962591 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.942414 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.942414 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954027 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.954027 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.550373 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.550373 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402728 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402728 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442608 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157133 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442608 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.386863 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.386863 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.030944 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.296596 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.296596 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132116 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189766 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14076.539101 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35399.651782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16132.527727 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16132.527727 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15482.397823 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15482.397823 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1082750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1082750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32240.143683 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32240.143683 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26963.756732 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15739.450869 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15739.450869 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21899.528115 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24221.103470 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112505.582137 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110264.990689 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 96701.160093 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 96701.160093 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 105201.586961 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 104225.723140 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168343 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15545.454545 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57126.740283 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22278.461810 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22278.461810 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18691.023788 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18691.023788 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2527000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2527000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44219.940604 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44219.940604 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37728.548454 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17293.844958 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17293.844958 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28246.142169 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34461.268734 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125738.625517 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125856.626506 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 110079.563492 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 110079.563492 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118770.439696 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 119048.715753 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 53417 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 719726 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2155 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 479672 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 677908 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 29213 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72925 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85236 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 84437 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66918 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 502041 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 506824 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1497175 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 834504 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5289 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9415 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2346383 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32131332 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24936310 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7860 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13456 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 57088958 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 1117653 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2525896 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.414848 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.492696 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1936586 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 978536 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 13921 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 103851 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 103732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 19887 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 919525 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 223940 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 770866 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 41722 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 69543 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86819 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 103431 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 101180 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 622926 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 309787 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 46 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1858177 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1153867 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8365 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17379 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3037788 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39867972 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35780458 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12160 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 75685138 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 354401 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2220337 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.063895 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.244785 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1478032 58.52% 58.52% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1047864 41.48% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 2078588 93.62% 93.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 141630 6.38% 99.99% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 119 0.01% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2525896 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 861521000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2220337 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1156529000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79810000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80617594 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 753238500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 934566000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 375346000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 534214495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 5325000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6051499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 11246990 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59423 # Transaction distribution -system.iobus.trans_dist::WriteResp 59423 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31011 # Transaction distribution +system.iobus.trans_dist::ReadResp 31011 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56596 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2232,11 +2253,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71540 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2257,11 +2278,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162790 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484054 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40088000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2301,52 +2322,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187554192 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186504974 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36780000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.390549 # Cycle average of tags in use +system.iocache.tags.replacements 36460 # number of replacements +system.iocache.tags.tagsinuse 14.383048 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36476 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 288373025000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.390549 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899409 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899409 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290140338000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.383048 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898940 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898940 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.tags.tag_accesses 328302 # Number of tag accesses +system.iocache.tags.data_accesses 328302 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 254 # number of ReadReq misses +system.iocache.ReadReq_misses::total 254 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses -system.iocache.demand_misses::total 255 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 255 # number of overall misses -system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32657877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32657877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4277536315 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4277536315 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32657877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32657877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32657877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32657877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 254 # number of demand (read+write) misses +system.iocache.demand_misses::total 254 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 254 # number of overall misses +system.iocache.overall_misses::total 254 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 33010877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33010877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4717790097 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4717790097 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 33010877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 33010877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 33010877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 33010877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 254 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 254 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 254 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 254 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 254 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 254 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2355,40 +2376,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128070.105882 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128070.105882 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.697742 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118085.697742 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128070.105882 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128070.105882 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129964.082677 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129964.082677 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130239.346759 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130239.346759 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129964.082677 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129964.082677 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.571429 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 254 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 254 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19907877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19907877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466336315 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2466336315 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19907877 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37500.688357 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 950.717991 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 465.629828 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2237.479906 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000046 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12055.995118 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.047185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7486.510812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2815.662270 # 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Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007105 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.975969 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32308 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.114235 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042964 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.570736 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.007474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033258 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.974142 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1819 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29951 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.492981 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2359 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30054 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.487183 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.489075 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5325589 # 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number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 33 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 23888 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 44855 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 41598 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 52 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 64 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 16804 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13921 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 9486 # number of demand (read+write) hits +system.l2c.demand_hits::total 150756 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 55 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 33 # number of overall hits +system.l2c.overall_hits::cpu0.inst 23888 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82110.544049 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170761.620535 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94661.741214 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143967.834597 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147398.638532 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 79700.928074 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142673.349744 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 159771.980542 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87741.682765 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 143434.329613 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.821593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.788756 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808854 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758929 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.877509 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.844389 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.754840 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.803361 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.774644 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.173299 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078610 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.536275 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.553759 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.553759 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 76013.832853 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73964.006630 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75238.376780 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77363.529412 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76840.694006 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76971.943296 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135438.267702 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121123.554024 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129379.232212 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126557.694531 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128658.644401 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133834.881063 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171703.525742 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107879.738770 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154992.229331 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154635.508752 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 93079.365079 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149617.507198 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163644.251717 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101289.008659 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 152776.587233 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44038 # Transaction distribution -system.membus.trans_dist::ReadResp 214387 # Transaction distribution -system.membus.trans_dist::WriteReq 30874 # Transaction distribution -system.membus.trans_dist::WriteResp 30874 # Transaction distribution -system.membus.trans_dist::Writeback 136186 # Transaction distribution -system.membus.trans_dist::CleanEvict 15507 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74602 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39992 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12685 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 39841 # Transaction distribution -system.membus.trans_dist::ReadExResp 19332 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170349 # Transaction distribution +system.membus.trans_dist::ReadReq 44076 # Transaction distribution +system.membus.trans_dist::ReadResp 212234 # Transaction distribution +system.membus.trans_dist::WriteReq 30913 # Transaction distribution +system.membus.trans_dist::WriteResp 30913 # Transaction distribution +system.membus.trans_dist::Writeback 134964 # Transaction distribution +system.membus.trans_dist::CleanEvict 15319 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74839 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40260 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12961 # Transaction distribution +system.membus.trans_dist::ReadExReq 39815 # Transaction distribution +system.membus.trans_dist::ReadExResp 19093 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 168158 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 670072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 791596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 900517 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664805 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 786483 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 895419 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162790 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18557448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18747458 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21064578 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123030 # Total snoops (count) -system.membus.snoop_fanout::samples 587901 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27468 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18323720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18514046 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20832190 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123434 # Total snoops (count) +system.membus.snoop_fanout::samples 584834 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 587901 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 584834 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 587901 # Request fanout histogram -system.membus.reqLayer0.occupancy 88280499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 584834 # Request fanout histogram +system.membus.reqLayer0.occupancy 88258000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11327500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11355499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 983138119 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 974246641 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1138149025 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1126274005 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64374606 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64655929 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2973,56 +2993,62 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 44042 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 480570 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30874 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 362932 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 82945 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 77217 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 117510 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 92 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50721 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50721 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 436543 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 910965 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 460102 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 151032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21991 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 21404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 587 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44080 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 476819 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 359850 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 80476 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 77372 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40572 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 117944 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51046 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51046 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 432754 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1115711 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 276298 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1392009 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31905816 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4776938 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36682754 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 449881 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1195846 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.169748 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.375411 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1048506 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 332828 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1381334 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 29760096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6517470 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36277566 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 449108 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1186895 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.300945 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.459746 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 992854 83.03% 83.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 202992 16.97% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 830292 69.95% 69.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 356016 30.00% 99.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 587 0.05% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1195846 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 812251839 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1186895 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 806375018 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 359119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 627943021 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 593704114 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 221271516 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 252660411 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 2f0ebe667..79e3a7b0a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903468 # Number of seconds simulated -sim_ticks 2903467553500 # Number of ticks simulated -final_tick 2903467553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909343 # Number of seconds simulated +sim_ticks 2909343316500 # Number of ticks simulated +final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 455888 # Simulator instruction rate (inst/s) -host_op_rate 549660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11767164312 # Simulator tick rate (ticks/s) -host_mem_usage 571472 # Number of bytes of host memory used -host_seconds 246.74 # Real time elapsed on the host -sim_insts 112487279 # Number of instructions simulated -sim_ops 135624752 # Number of ops (including micro ops) simulated +host_inst_rate 666869 # Simulator instruction rate (inst/s) +host_op_rate 804035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17251437084 # Simulator tick rate (ticks/s) +host_mem_usage 624248 # Number of bytes of host memory used +host_seconds 168.64 # Real time elapsed on the host +sim_insts 112463069 # Number of instructions simulated +sim_ops 135595282 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1189412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9042916 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10233864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1189412 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189412 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7647616 # Number of bytes written to this memory +system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7665140 # Number of bytes written to this memory +system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119494 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123875 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 409652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3114523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3524704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 409652 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409652 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2633960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6036 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2639995 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2633960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 409652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3120558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6164699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168877 # Number of read requests accepted -system.physmem.writeReqs 123875 # Number of write requests accepted -system.physmem.readBursts 168877 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123875 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10799552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7677760 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10233864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7665140 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166592 # Number of read requests accepted +system.physmem.writeReqs 121840 # Number of write requests accepted +system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10018 # Per bank write bursts -system.physmem.perBankRdBursts::1 9658 # Per bank write bursts -system.physmem.perBankRdBursts::2 10300 # Per bank write bursts -system.physmem.perBankRdBursts::3 9945 # Per bank write bursts -system.physmem.perBankRdBursts::4 18863 # Per bank write bursts -system.physmem.perBankRdBursts::5 10091 # Per bank write bursts -system.physmem.perBankRdBursts::6 10302 # Per bank write bursts -system.physmem.perBankRdBursts::7 10601 # Per bank write bursts -system.physmem.perBankRdBursts::8 9921 # Per bank write bursts -system.physmem.perBankRdBursts::9 10207 # Per bank write bursts -system.physmem.perBankRdBursts::10 9962 # Per bank write bursts -system.physmem.perBankRdBursts::11 9026 # Per bank write bursts -system.physmem.perBankRdBursts::12 9868 # Per bank write bursts -system.physmem.perBankRdBursts::13 10473 # Per bank write bursts -system.physmem.perBankRdBursts::14 9981 # Per bank write bursts -system.physmem.perBankRdBursts::15 9527 # Per bank write bursts -system.physmem.perBankWrBursts::0 7412 # Per bank write bursts -system.physmem.perBankWrBursts::1 7255 # Per bank write bursts -system.physmem.perBankWrBursts::2 8123 # Per bank write bursts -system.physmem.perBankWrBursts::3 7537 # Per bank write bursts -system.physmem.perBankWrBursts::4 7355 # Per bank write bursts -system.physmem.perBankWrBursts::5 7348 # Per bank write bursts -system.physmem.perBankWrBursts::6 7577 # Per bank write bursts -system.physmem.perBankWrBursts::7 7905 # Per bank write bursts -system.physmem.perBankWrBursts::8 7603 # Per bank write bursts -system.physmem.perBankWrBursts::9 7853 # Per bank write bursts -system.physmem.perBankWrBursts::10 7551 # Per bank write bursts -system.physmem.perBankWrBursts::11 6940 # Per bank write bursts -system.physmem.perBankWrBursts::12 7397 # Per bank write bursts -system.physmem.perBankWrBursts::13 7831 # Per bank write bursts -system.physmem.perBankWrBursts::14 7359 # Per bank write bursts -system.physmem.perBankWrBursts::15 6919 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10226 # Per bank write bursts +system.physmem.perBankRdBursts::1 9700 # Per bank write bursts +system.physmem.perBankRdBursts::2 10356 # Per bank write bursts +system.physmem.perBankRdBursts::3 10496 # Per bank write bursts +system.physmem.perBankRdBursts::4 18505 # Per bank write bursts +system.physmem.perBankRdBursts::5 10022 # Per bank write bursts +system.physmem.perBankRdBursts::6 10179 # Per bank write bursts +system.physmem.perBankRdBursts::7 10614 # Per bank write bursts +system.physmem.perBankRdBursts::8 9478 # Per bank write bursts +system.physmem.perBankRdBursts::9 10041 # Per bank write bursts +system.physmem.perBankRdBursts::10 9320 # Per bank write bursts +system.physmem.perBankRdBursts::11 9342 # Per bank write bursts +system.physmem.perBankRdBursts::12 9424 # Per bank write bursts +system.physmem.perBankRdBursts::13 10229 # Per bank write bursts +system.physmem.perBankRdBursts::14 9340 # Per bank write bursts +system.physmem.perBankRdBursts::15 9201 # Per bank write bursts +system.physmem.perBankWrBursts::0 7577 # Per bank write bursts +system.physmem.perBankWrBursts::1 7036 # Per bank write bursts +system.physmem.perBankWrBursts::2 7887 # Per bank write bursts +system.physmem.perBankWrBursts::3 8049 # Per bank write bursts +system.physmem.perBankWrBursts::4 7151 # Per bank write bursts +system.physmem.perBankWrBursts::5 7579 # Per bank write bursts +system.physmem.perBankWrBursts::6 7566 # Per bank write bursts +system.physmem.perBankWrBursts::7 7770 # Per bank write bursts +system.physmem.perBankWrBursts::8 7275 # Per bank write bursts +system.physmem.perBankWrBursts::9 7619 # Per bank write bursts +system.physmem.perBankWrBursts::10 6810 # Per bank write bursts +system.physmem.perBankWrBursts::11 7097 # Per bank write bursts +system.physmem.perBankWrBursts::12 7200 # Per bank write bursts +system.physmem.perBankWrBursts::13 7753 # Per bank write bursts +system.physmem.perBankWrBursts::14 6925 # Per bank write bursts +system.physmem.perBankWrBursts::15 6640 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 2903467231500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2909342872000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159305 # Read request sizes (log2) +system.physmem.readPktSize::6 157020 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119494 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117459 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,159 +159,152 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 170 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # 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What write queue length does an incoming req see system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.689209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.095727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.740944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21592 36.42% 36.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15113 25.49% 61.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5696 9.61% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3272 5.52% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2400 4.05% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1627 2.74% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1059 1.79% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 986 1.66% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7536 12.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59281 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5916 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.520960 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 582.774923 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5915 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5916 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5916 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.278059 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.578317 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.228760 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5122 86.58% 86.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 0.59% 87.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 194 3.28% 90.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 61 1.03% 91.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 61 1.03% 92.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 181 3.06% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.24% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.08% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.12% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.12% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.76% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.03% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.12% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.10% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.29% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5916 # Writes before turning the bus around for reads -system.physmem.totQLat 1515248250 # Total ticks spent queuing -system.physmem.totMemAccLat 4679179500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8979.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads +system.physmem.totQLat 1636363750 # Total ticks spent queuing +system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27729.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.93 # Average write queue length when enqueuing -system.physmem.readRowHits 138696 # Number of row buffer hits during reads -system.physmem.writeRowHits 90730 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.62 # Row buffer hit rate for writes -system.physmem.avgGap 9917839.10 # Average gap between requests -system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229068000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 124987500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 700268400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392117760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87025634640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665738759750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943850825810 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.494214 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770947478500 # Time in different power states -system.physmem_0.memoryStateTime::REF 96952960000 # Time in different power states +system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing +system.physmem.readRowHits 136200 # Number of row buffer hits during reads +system.physmem.writeRowHits 89619 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes +system.physmem.avgGap 10086754.84 # Average gap between requests +system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.621597 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35561301500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219096360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119546625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 615919200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385255440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85786607970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666825625250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943592040605 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.405084 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772773591250 # Time in different power states -system.physmem_1.memoryStateTime::REF 96952960000 # Time in different power states +system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.478544 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33740904250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -361,56 +354,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9548 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9548 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1269 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8279 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9548 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9548 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9548 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7384 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11763.949079 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9756.046308 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7392.958780 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 5809 78.67% 78.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1570 21.26% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7384 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 925393500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 925393500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 925393500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6162 83.45% 83.45% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1222 16.55% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7384 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9548 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 9555 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9548 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7384 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7384 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16932 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24527083 # DTB read hits -system.cpu.dtb.read_misses 8134 # DTB read misses -system.cpu.dtb.write_hits 19611642 # DTB write hits -system.cpu.dtb.write_misses 1414 # DTB write misses +system.cpu.dtb.read_hits 24521784 # DTB read hits +system.cpu.dtb.read_misses 8135 # DTB read misses +system.cpu.dtb.write_hits 19607400 # DTB write hits +system.cpu.dtb.write_misses 1420 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1680 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24535217 # DTB read accesses -system.cpu.dtb.write_accesses 19613056 # DTB write accesses +system.cpu.dtb.read_accesses 24529919 # DTB read accesses +system.cpu.dtb.write_accesses 19608820 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44138725 # DTB hits -system.cpu.dtb.misses 9548 # DTB misses -system.cpu.dtb.accesses 44148273 # DTB accesses +system.cpu.dtb.hits 44129184 # DTB hits +system.cpu.dtb.misses 9555 # DTB misses +system.cpu.dtb.accesses 44138739 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -440,38 +432,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 4762 # Table walker walks requested -system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walks 4763 # Table walker walks requested +system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11752.816221 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9620.437143 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7446.323545 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1417 45.61% 45.61% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1012 32.57% 78.18% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 676 21.76% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115585268 # ITB inst hits -system.cpu.itb.inst_misses 4762 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115560644 # ITB inst hits +system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -487,38 +477,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115590030 # ITB inst accesses -system.cpu.itb.hits 115585268 # DTB hits -system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115590030 # DTB accesses -system.cpu.numCycles 5806935107 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 115565407 # ITB inst accesses +system.cpu.itb.hits 115560644 # DTB hits +system.cpu.itb.misses 4763 # DTB misses +system.cpu.itb.accesses 115565407 # DTB accesses +system.cpu.numCycles 5818686633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112487279 # Number of instructions committed -system.cpu.committedOps 135624752 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119926396 # Number of integer alu accesses +system.cpu.committedInsts 112463069 # Number of instructions committed +system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9895067 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15234125 # number of instructions that are conditional controls -system.cpu.num_int_insts 119926396 # number of integer instructions +system.cpu.num_func_calls 9893453 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls +system.cpu.num_int_insts 119900050 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218121828 # number of times the integer registers were read -system.cpu.num_int_register_writes 82669566 # number of times the integer registers were written +system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read +system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489877250 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51907763 # number of times the CC registers were written -system.cpu.num_mem_refs 45420046 # number of memory refs -system.cpu.num_load_insts 24850080 # Number of load instructions -system.cpu.num_store_insts 20569966 # Number of store instructions -system.cpu.num_idle_cycles 5385437399.888144 # Number of idle cycles -system.cpu.num_busy_cycles 421497707.111855 # Number of busy cycles -system.cpu.not_idle_fraction 0.072585 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927415 # Percentage of idle cycles -system.cpu.Branches 25923230 # Number of branches fetched +system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written +system.cpu.num_mem_refs 45409486 # number of memory refs +system.cpu.num_load_insts 24844046 # Number of load instructions +system.cpu.num_store_insts 20565440 # Number of store instructions +system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles +system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924573 # Percentage of idle cycles +system.cpu.Branches 25918657 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93200379 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114573 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -546,110 +536,110 @@ system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24850080 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20569966 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138745790 # Class of executed instruction +system.cpu.op_class::total 138715716 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3030 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 820821 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.829842 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43246183 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821333 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.653653 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.829842 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999668 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 821347 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177159261 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177159261 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23117842 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23117842 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18828857 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18828857 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392869 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392869 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443457 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443457 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460420 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460420 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41946699 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41946699 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42339568 # number of overall hits -system.cpu.dcache.overall_hits::total 42339568 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401262 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401262 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298702 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298702 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118314 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118314 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22748 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22748 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177121649 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177121649 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112263 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112263 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18824569 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18824569 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392807 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392807 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443229 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460200 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460200 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41936832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41936832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329639 # number of overall hits +system.cpu.dcache.overall_hits::total 42329639 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 401818 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 401818 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298972 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298972 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118323 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22757 # 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average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13154.531148 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12894.927961 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12894.927961 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016414 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016414 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018914 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018914 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15169.085934 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15169.085934 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62897.783070 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62897.783070 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13910.384417 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13910.384417 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13553.716097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13553.716097 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25499.003266 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25499.003266 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23738.923670 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21652540000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21652540000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 676974000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 676974000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 676974000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # 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average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75035.912215 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22566023500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22566023500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22566023500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22566023500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010606 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063749 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063749 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74277.777778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20795.429414 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20795.429414 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.434832 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.434832 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010581 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023362 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023362 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062853 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062853 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66422.426361 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66422.426361 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70080.452755 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70080.452755 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72705.316558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72705.316558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177208.865840 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 151449.992531 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154209.665145 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154209.665145 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166403.909017 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 152573.851058 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 67206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2292179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1805693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2736 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2738 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699351 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2579570 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12812 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7701560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108793272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96436737 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14388 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205272145 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 179423 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5300588 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.035792 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.185771 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175948 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5110870 96.42% 96.42% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 189718 3.58% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5300588 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3265127000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2558048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1278361999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17827000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::ReadReq 30177 # Transaction distribution +system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1211,9 +1207,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1236,9 +1232,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1279,52 +1275,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187438974 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134160 # Cycle average of tags in use +system.iocache.tags.replacements 36418 # number of replacements +system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 299040065000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134160 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070885 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070885 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.tags.tag_accesses 328068 # Number of tag accesses +system.iocache.tags.data_accesses 328068 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses +system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses -system.iocache.demand_misses::total 234 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 234 # number of overall misses -system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4271537097 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4271537097 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses +system.iocache.demand_misses::total 228 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 228 # number of overall misses +system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1333,14 +1329,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117920.083287 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117920.083287 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1351,22 +1347,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460337097 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2460337097 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1375,68 +1371,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67920.083287 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67920.083287 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 40164 # Transaction distribution -system.membus.trans_dist::ReadResp 70750 # Transaction distribution -system.membus.trans_dist::WriteReq 27594 # Transaction distribution -system.membus.trans_dist::WriteResp 27594 # Transaction distribution -system.membus.trans_dist::Writeback 119494 # Transaction distribution -system.membus.trans_dist::CleanEvict 6493 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::ReadReq 40160 # Transaction distribution +system.membus.trans_dist::ReadResp 70632 # Transaction distribution +system.membus.trans_dist::WriteReq 27589 # Transaction distribution +system.membus.trans_dist::WriteResp 27589 # Transaction distribution +system.membus.trans_dist::Writeback 117459 # Transaction distribution +system.membus.trans_dist::CleanEvict 6342 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 129215 # Transaction distribution -system.membus.trans_dist::ReadExResp 129215 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30586 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution +system.membus.trans_dist::ReadExReq 127038 # Transaction distribution +system.membus.trans_dist::ReadExResp 127038 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445567 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15581884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15745273 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18062393 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 394512 # Request fanout histogram +system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 492 # Total snoops (count) +system.membus.snoop_fanout::samples 390004 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394512 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394512 # Request fanout histogram -system.membus.reqLayer0.occupancy 90495000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390004 # Request fanout histogram +system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 834776313 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 964479239 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64484992 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1469,13 +1465,13 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 86f263873..83f940052 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1097147 # Simulator instruction rate (inst/s) -host_op_rate 1335600 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21392785088 # Simulator tick rate (ticks/s) -host_mem_usage 571732 # Number of bytes of host memory used -host_seconds 130.13 # Real time elapsed on the host +host_inst_rate 1174884 # Simulator instruction rate (inst/s) +host_op_rate 1430233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22908545755 # Simulator tick rate (ticks/s) +host_mem_usage 623708 # Number of bytes of host memory used +host_seconds 121.52 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -763,9 +763,9 @@ system.iocache.writebacks::total 36190 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 109907 # number of replacements system.l2c.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.l2c.tags.total_refs 4567770 # Total number of references to valid blocks. +system.l2c.tags.total_refs 4528496 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 175188 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 26.073532 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 25.849350 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 48764.072075 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor @@ -794,8 +794,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 10699 # system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40922425 # Number of tag accesses -system.l2c.tags.data_accesses 40922425 # Number of data accesses +system.l2c.tags.tag_accesses 40608233 # Number of tag accesses +system.l2c.tags.data_accesses 40608233 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits @@ -956,7 +956,7 @@ system.membus.trans_dist::ReadResp 74196 # Tr system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::Writeback 138133 # Transaction distribution -system.membus.trans_dist::CleanEvict 8204 # Transaction distribution +system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -970,9 +970,9 @@ system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506563 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 613923 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723054 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) @@ -1024,22 +1024,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks +system.toL2Bus.snoop_filter.tot_requests 5060706 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2541063 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 71244 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1836352 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1797078 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -1047,27 +1053,27 @@ system.toL2Bus.trans_dist::ReadExReq 298922 # Tr system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116722 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2582000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5084714 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574734 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7761036 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 36631 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5176290 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.013064 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.113547 # Request fanout histogram +system.toL2Bus.snoops 182968 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.134877 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5108669 98.69% 98.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 67621 1.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5223970 98.15% 98.15% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 98657 1.85% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5176290 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5322627 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index cda6fdde5..a4264e923 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903518 # Number of seconds simulated -sim_ticks 2903517798500 # Number of ticks simulated -final_tick 2903517798500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909388 # Number of seconds simulated +sim_ticks 2909387991500 # Number of ticks simulated +final_tick 2909387991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 703123 # Simulator instruction rate (inst/s) -host_op_rate 847748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18151522616 # Simulator tick rate (ticks/s) -host_mem_usage 572756 # Number of bytes of host memory used -host_seconds 159.96 # Real time elapsed on the host -sim_insts 112471533 # Number of instructions simulated -sim_ops 135605825 # Number of ops (including micro ops) simulated +host_inst_rate 670421 # Simulator instruction rate (inst/s) +host_op_rate 808321 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17345176485 # Simulator tick rate (ticks/s) +host_mem_usage 625252 # Number of bytes of host memory used +host_seconds 167.73 # Real time elapsed on the host +sim_insts 112452815 # Number of instructions simulated +sim_ops 135583410 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 588836 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3938784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 600704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5102020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 538144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4761988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 646852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4138720 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10231944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 588836 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 600704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1189540 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7646016 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7663540 # Number of bytes written to this memory +system.physmem.bytes_read::total 10087176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 538144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 646852 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 8860 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8664 # Number of bytes written to this memory +system.physmem.bytes_written::total 7534772 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17654 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 62062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 79720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 64683 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168847 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119469 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123850 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166585 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2215 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2166 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121838 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 202801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1356556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 206888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1757186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3523982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 202801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 206888 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409689 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2633363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6033 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2639398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2633363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 184968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1636766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 222333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1422540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 184968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 222333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2583790 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 3045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2978 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2589813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2583790 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 202801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1362589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 206888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1757188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6163380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168847 # Number of read requests accepted -system.physmem.writeReqs 123850 # Number of write requests accepted -system.physmem.readBursts 168847 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123850 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10798016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 7677504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10231944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7663540 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 184968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1639812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 222333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1425518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6056926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166585 # Number of read requests accepted +system.physmem.writeReqs 121838 # Number of write requests accepted +system.physmem.readBursts 166585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121838 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue +system.physmem.bytesWritten 7548800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10087176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7534772 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10014 # Per bank write bursts -system.physmem.perBankRdBursts::1 9659 # Per bank write bursts -system.physmem.perBankRdBursts::2 10299 # Per bank write bursts -system.physmem.perBankRdBursts::3 9948 # Per bank write bursts -system.physmem.perBankRdBursts::4 18863 # Per bank write bursts -system.physmem.perBankRdBursts::5 10091 # Per bank write bursts -system.physmem.perBankRdBursts::6 10301 # Per bank write bursts -system.physmem.perBankRdBursts::7 10599 # Per bank write bursts -system.physmem.perBankRdBursts::8 9915 # Per bank write bursts -system.physmem.perBankRdBursts::9 10209 # Per bank write bursts -system.physmem.perBankRdBursts::10 9947 # Per bank write bursts -system.physmem.perBankRdBursts::11 9027 # Per bank write bursts -system.physmem.perBankRdBursts::12 9869 # Per bank write bursts -system.physmem.perBankRdBursts::13 10471 # Per bank write bursts -system.physmem.perBankRdBursts::14 9980 # Per bank write bursts -system.physmem.perBankRdBursts::15 9527 # Per bank write bursts -system.physmem.perBankWrBursts::0 7419 # Per bank write bursts -system.physmem.perBankWrBursts::1 7262 # Per bank write bursts -system.physmem.perBankWrBursts::2 8122 # Per bank write bursts -system.physmem.perBankWrBursts::3 7539 # Per bank write bursts -system.physmem.perBankWrBursts::4 7355 # Per bank write bursts -system.physmem.perBankWrBursts::5 7348 # Per bank write bursts -system.physmem.perBankWrBursts::6 7576 # Per bank write bursts -system.physmem.perBankWrBursts::7 7905 # Per bank write bursts -system.physmem.perBankWrBursts::8 7603 # Per bank write bursts -system.physmem.perBankWrBursts::9 7846 # Per bank write bursts -system.physmem.perBankWrBursts::10 7540 # Per bank write bursts -system.physmem.perBankWrBursts::11 6940 # Per bank write bursts -system.physmem.perBankWrBursts::12 7394 # Per bank write bursts -system.physmem.perBankWrBursts::13 7835 # Per bank write bursts -system.physmem.perBankWrBursts::14 7358 # Per bank write bursts -system.physmem.perBankWrBursts::15 6919 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40727 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10228 # Per bank write bursts +system.physmem.perBankRdBursts::1 9700 # Per bank write bursts +system.physmem.perBankRdBursts::2 10356 # Per bank write bursts +system.physmem.perBankRdBursts::3 10495 # Per bank write bursts +system.physmem.perBankRdBursts::4 18506 # Per bank write bursts +system.physmem.perBankRdBursts::5 10022 # Per bank write bursts +system.physmem.perBankRdBursts::6 10178 # Per bank write bursts +system.physmem.perBankRdBursts::7 10614 # Per bank write bursts +system.physmem.perBankRdBursts::8 9477 # Per bank write bursts +system.physmem.perBankRdBursts::9 10047 # Per bank write bursts +system.physmem.perBankRdBursts::10 9317 # Per bank write bursts +system.physmem.perBankRdBursts::11 9342 # Per bank write bursts +system.physmem.perBankRdBursts::12 9423 # Per bank write bursts +system.physmem.perBankRdBursts::13 10228 # Per bank write bursts +system.physmem.perBankRdBursts::14 9339 # Per bank write bursts +system.physmem.perBankRdBursts::15 9201 # Per bank write bursts +system.physmem.perBankWrBursts::0 7595 # Per bank write bursts +system.physmem.perBankWrBursts::1 7036 # Per bank write bursts +system.physmem.perBankWrBursts::2 7887 # Per bank write bursts +system.physmem.perBankWrBursts::3 8047 # Per bank write bursts +system.physmem.perBankWrBursts::4 7152 # Per bank write bursts +system.physmem.perBankWrBursts::5 7580 # Per bank write bursts +system.physmem.perBankWrBursts::6 7566 # Per bank write bursts +system.physmem.perBankWrBursts::7 7770 # Per bank write bursts +system.physmem.perBankWrBursts::8 7275 # Per bank write bursts +system.physmem.perBankWrBursts::9 7619 # Per bank write bursts +system.physmem.perBankWrBursts::10 6806 # Per bank write bursts +system.physmem.perBankWrBursts::11 7096 # Per bank write bursts +system.physmem.perBankWrBursts::12 7204 # Per bank write bursts +system.physmem.perBankWrBursts::13 7753 # Per bank write bursts +system.physmem.perBankWrBursts::14 6924 # Per bank write bursts +system.physmem.perBankWrBursts::15 6640 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2903517476500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2909387547000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159275 # Read request sizes (log2) +system.physmem.readPktSize::6 157013 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119469 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117457 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -161,178 +161,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8053 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59278 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.674753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.487125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.482596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21806 36.79% 36.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14989 25.29% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5586 9.42% 71.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3267 5.51% 77.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2330 3.93% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1628 2.75% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1108 1.87% 85.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1064 1.79% 87.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7500 12.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59278 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5882 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.683781 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 547.352228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5880 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.902116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.522866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.172226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21290 36.36% 36.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14652 25.03% 61.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6083 10.39% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3178 5.43% 77.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2491 4.25% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1565 2.67% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1038 1.77% 85.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1041 1.78% 87.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7211 12.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58549 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5743 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.986941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 548.492879 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5740 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5882 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.394594 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.624984 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.894436 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 8 0.14% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 7 0.12% 0.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 10 0.17% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4921 83.66% 84.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 66 1.12% 85.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 241 4.10% 89.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 88 1.50% 91.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 77 1.31% 92.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 178 3.03% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.24% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 13 0.22% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.09% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 174 2.96% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.24% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads -system.physmem.totQLat 1493162250 # Total ticks spent queuing -system.physmem.totMemAccLat 4656643500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8849.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5743 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5743 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.538046 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.602147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.025411 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 27 0.47% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 14 0.24% 0.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 12 0.21% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 14 0.24% 1.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4750 82.71% 83.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 125 2.18% 86.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 82 1.43% 87.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 205 3.57% 91.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.56% 91.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 152 2.65% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.19% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.31% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.16% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 172 2.99% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.10% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.37% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.05% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.24% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5743 # Writes before turning the bus around for reads +system.physmem.totQLat 1603192250 # Total ticks spent queuing +system.physmem.totMemAccLat 4724561000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9630.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27599.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28380.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.20 # Average write queue length when enqueuing -system.physmem.readRowHits 138806 # Number of row buffer hits during reads -system.physmem.writeRowHits 90595 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes -system.physmem.avgGap 9919874.40 # Average gap between requests -system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229302360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125115375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 700237200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392208480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87298782345 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665531858750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943921054190 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.505834 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770598960250 # Time in different power states -system.physmem_0.memoryStateTime::REF 96954780000 # Time in different power states +system.physmem.avgWrQLen 7.27 # Average write queue length when enqueuing +system.physmem.readRowHits 136293 # Number of row buffer hits during reads +system.physmem.writeRowHits 89580 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes +system.physmem.avgGap 10087224.48 # Average gap between requests +system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229158720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125037000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702772200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90369730305 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666360544250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948207148235 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.628037 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2771956641500 # Time in different power states +system.physmem_0.memoryStateTime::REF 97150820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35962503500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40279614750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 218839320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119406375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 615763200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385138800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 86123693430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666562638500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943669029305 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.419034 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772326743250 # Time in different power states -system.physmem_1.memoryStateTime::REF 96954780000 # Time in different power states +system.physmem_1.actEnergy 213471720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116477625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595709400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371414160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88357601520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668125569500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947807247845 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.490585 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774916457500 # Time in different power states +system.physmem_1.memoryStateTime::REF 97150820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34236177250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37320566000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -382,60 +379,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6827 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6827 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2216 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4610 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walks 6929 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6929 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2193 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4735 # Level at which table walker walks with short descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6826 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6826 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6826 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5786 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12342.983063 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10713.852920 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6703.217150 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4631 80.04% 80.04% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1152 19.91% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5786 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -1209080312 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.765375 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 925400000 -76.54% -76.54% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -2134480312 176.54% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -1209080312 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3595 62.14% 62.14% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2190 37.86% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5785 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6827 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::samples 6928 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6928 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6928 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5821 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12939.357499 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11196.384549 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7211.949482 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4588 78.82% 78.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1229 21.11% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5821 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1237488496 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean -0.616549 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2000461000 161.65% 161.65% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -762972504 -61.65% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1237488496 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3649 62.70% 62.70% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2171 37.30% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5820 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6929 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6827 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5785 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6929 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5820 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5785 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12612 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5820 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12749 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12507441 # DTB read hits -system.cpu0.dtb.read_misses 5917 # DTB read misses -system.cpu0.dtb.write_hits 9856816 # DTB write hits -system.cpu0.dtb.write_misses 910 # DTB write misses -system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12044488 # DTB read hits +system.cpu0.dtb.read_misses 5975 # DTB read misses +system.cpu0.dtb.write_hits 9654865 # DTB write hits +system.cpu0.dtb.write_misses 954 # DTB write misses +system.cpu0.dtb.flush_tlb 2940 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4603 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4388 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 884 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12513358 # DTB read accesses -system.cpu0.dtb.write_accesses 9857726 # DTB write accesses +system.cpu0.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12050463 # DTB read accesses +system.cpu0.dtb.write_accesses 9655819 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22364257 # DTB hits -system.cpu0.dtb.misses 6827 # DTB misses -system.cpu0.dtb.accesses 22371084 # DTB accesses +system.cpu0.dtb.hits 21699353 # DTB hits +system.cpu0.dtb.misses 6929 # DTB misses +system.cpu0.dtb.accesses 21706282 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,254 +460,256 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3521 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3521 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 830 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2691 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3521 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3521 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3521 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2670 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12834.082397 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11032.722243 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6917.920498 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 769 28.80% 28.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1283 48.05% 76.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 616 23.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2670 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1840 68.91% 68.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 830 31.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2670 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3426 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3426 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 828 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2598 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3426 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3426 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3426 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12817.630962 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11147.269267 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6399.295854 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::4096-6143 694 27.13% 27.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::10240-12287 823 32.17% 59.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::12288-14335 178 6.96% 66.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::14336-16383 343 13.41% 79.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-18431 1 0.04% 79.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::22528-24575 515 20.13% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-26623 4 0.16% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1730 67.63% 67.63% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 828 32.37% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2558 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3521 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3521 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3426 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3426 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2670 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2670 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6191 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 58595537 # ITB inst hits -system.cpu0.itb.inst_misses 3521 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2558 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2558 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5984 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56823446 # ITB inst hits +system.cpu0.itb.inst_misses 3426 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2940 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2691 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2582 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58599058 # ITB inst accesses -system.cpu0.itb.hits 58595537 # DTB hits -system.cpu0.itb.misses 3521 # DTB misses -system.cpu0.itb.accesses 58599058 # DTB accesses -system.cpu0.numCycles 2904052506 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56826872 # ITB inst accesses +system.cpu0.itb.hits 56823446 # DTB hits +system.cpu0.itb.misses 3426 # DTB misses +system.cpu0.itb.accesses 56826872 # DTB accesses +system.cpu0.numCycles 2910048510 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57017963 # Number of instructions committed -system.cpu0.committedOps 68702056 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60736686 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5415 # Number of float alu accesses -system.cpu0.num_func_calls 5101109 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7710665 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60736686 # number of integer instructions -system.cpu0.num_fp_insts 5415 # number of float instructions -system.cpu0.num_int_register_reads 110496547 # number of times the integer registers were read -system.cpu0.num_int_register_writes 42022968 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4193 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 248490103 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26091255 # number of times the CC registers were written -system.cpu0.num_mem_refs 23020484 # number of memory refs -system.cpu0.num_load_insts 12672781 # Number of load instructions -system.cpu0.num_store_insts 10347703 # Number of store instructions -system.cpu0.num_idle_cycles 2689228469.175671 # Number of idle cycles -system.cpu0.num_busy_cycles 214824036.824329 # Number of busy cycles -system.cpu0.not_idle_fraction 0.073974 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.926026 # Percentage of idle cycles -system.cpu0.Branches 13203328 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2205 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 47217639 67.16% 67.16% # Class of executed instruction -system.cpu0.op_class::IntMult 59885 0.09% 67.25% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4420 0.01% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::MemRead 12672781 18.03% 85.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 10347703 14.72% 100.00% # Class of executed instruction +system.cpu0.committedInsts 55288600 # Number of instructions committed +system.cpu0.committedOps 66713599 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58931600 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5354 # Number of float alu accesses +system.cpu0.num_func_calls 4809440 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7565706 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58931600 # number of integer instructions +system.cpu0.num_fp_insts 5354 # number of float instructions +system.cpu0.num_int_register_reads 107138015 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40582750 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4124 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1232 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 240777875 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25734446 # number of times the CC registers were written +system.cpu0.num_mem_refs 22316238 # number of memory refs +system.cpu0.num_load_insts 12197914 # Number of load instructions +system.cpu0.num_store_insts 10118324 # Number of store instructions +system.cpu0.num_idle_cycles 2666885275.671365 # Number of idle cycles +system.cpu0.num_busy_cycles 243163234.328635 # Number of busy cycles +system.cpu0.not_idle_fraction 0.083560 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.916440 # Percentage of idle cycles +system.cpu0.Branches 12750711 # Number of branches fetched +system.cpu0.op_class::No_OpClass 119 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 45844704 67.20% 67.20% # Class of executed instruction +system.cpu0.op_class::IntMult 57827 0.08% 67.28% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3997 0.01% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::MemRead 12197914 17.88% 85.17% # Class of executed instruction +system.cpu0.op_class::MemWrite 10118324 14.83% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 70304633 # Class of executed instruction +system.cpu0.op_class::total 68222885 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3029 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 820099 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.829843 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43241744 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 820611 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.694570 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 401.515698 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 110.314145 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.784210 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.215457 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 821400 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.702036 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43232181 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 821912 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.599525 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 174.965504 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 336.736532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.341730 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.657689 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177137427 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177137427 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11786116 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11329399 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23115515 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9461522 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9365348 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18826870 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201006 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191753 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392759 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 231308 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 212173 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443481 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 239891 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 220488 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460379 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 21247638 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20694747 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41942385 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 21448644 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 20886500 # number of overall hits -system.cpu0.dcache.overall_hits::total 42335144 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 202704 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 197921 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 400625 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 143580 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 155041 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298621 # 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number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9551716 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18823167 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190318 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202376 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392694 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 212739 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 230449 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443188 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 220738 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 239445 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460183 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20631199 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21302146 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10278276500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 19329792000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2904028500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3003756000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5907784500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2320925500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2251479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4572405000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5224954000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5255235500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10480189500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016883 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017138 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017008 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014948 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015614 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224761 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.230313 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227484 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018543 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.018121 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018341 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12964903000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 11904577000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24869480000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13768904000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12715148000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26484052000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2876770000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3059986500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5936756500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2305348000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2486099500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4791447500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5182118000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5546086000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10728204000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017073 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017035 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017054 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016065 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015217 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015635 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230689 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.224470 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227498 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017147 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019334 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018285 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016023 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016752 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016383 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018510 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019265 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018883 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13848.742423 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13901.949866 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13875.022814 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38166.370664 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43706.658239 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41042.831884 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13128.246088 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13091.368228 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13109.936430 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12710.590586 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12988.507168 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12842.105263 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016621 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016221 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019130 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018712 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15162.609022 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15163.629489 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15163.127298 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 65879.506811 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59734.344194 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62845.823620 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14006.742043 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13774.679242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13889.269308 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13606.183146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13461.169191 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13526.408451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23940.059481 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27007.575306 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25488.307810 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22375.664050 # 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average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11090149500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11460445000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22550594500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11090149500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11460445000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22550594500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11090149500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11460445000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22550594500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13291.239330 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1002,60 +1005,54 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6604 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6604 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1835 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4768 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6603 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6603 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6603 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5481 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12293.559569 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10651.112974 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6472.015315 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1651 30.12% 30.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2769 50.52% 80.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1058 19.30% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5481 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1004634564 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.995586 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000200000 -99.56% -99.56% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -2004834564 199.56% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1004634564 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3666 66.90% 66.90% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1814 33.10% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5480 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6604 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 6703 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6703 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2138 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4565 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6703 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6703 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6703 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5647 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13331.414911 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11611.737502 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7443.565061 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5646 99.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5647 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3534 62.58% 62.58% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 2113 37.42% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5647 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6703 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6604 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5480 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6703 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5647 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5480 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12084 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12350 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12016469 # DTB read hits -system.cpu1.dtb.read_misses 5667 # DTB read misses -system.cpu1.dtb.write_hits 9752712 # DTB write hits -system.cpu1.dtb.write_misses 937 # DTB write misses -system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12475099 # DTB read hits +system.cpu1.dtb.read_misses 5811 # DTB read misses +system.cpu1.dtb.write_hits 9951122 # DTB write hits +system.cpu1.dtb.write_misses 892 # DTB write misses +system.cpu1.dtb.flush_tlb 2942 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4084 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4467 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12022136 # DTB read accesses -system.cpu1.dtb.write_accesses 9753649 # DTB write accesses +system.cpu1.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12480910 # DTB read accesses +system.cpu1.dtb.write_accesses 9952014 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 21769181 # DTB hits -system.cpu1.dtb.misses 6604 # DTB misses -system.cpu1.dtb.accesses 21775785 # DTB accesses +system.cpu1.dtb.hits 22426221 # DTB hits +system.cpu1.dtb.misses 6703 # DTB misses +system.cpu1.dtb.accesses 22432924 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1085,122 +1082,119 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3234 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3234 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 677 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3234 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3234 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3234 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2430 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12793.004115 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11015.336185 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6613.791032 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 712 29.30% 29.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.04% 29.34% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.70% 57.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 477 19.63% 76.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 16 0.66% 77.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 551 22.67% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2430 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1753 72.14% 72.14% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 677 27.86% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2430 # Table walker page sizes translated +system.cpu1.itb.walker.walks 3400 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3400 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 811 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2589 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3400 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3400 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3400 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13798.698814 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12017.058980 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7032.742162 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1945 74.44% 74.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 667 25.53% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1802 68.96% 68.96% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 811 31.04% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2613 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3234 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3234 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3400 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2430 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2430 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5664 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 56973488 # ITB inst hits -system.cpu1.itb.inst_misses 3234 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2613 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2613 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6013 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58726785 # ITB inst hits +system.cpu1.itb.inst_misses 3400 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2933 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2942 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2428 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2616 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 56976722 # ITB inst accesses -system.cpu1.itb.hits 56973488 # DTB hits -system.cpu1.itb.misses 3234 # DTB misses -system.cpu1.itb.accesses 56976722 # DTB accesses -system.cpu1.numCycles 2902983091 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58730185 # ITB inst accesses +system.cpu1.itb.hits 58726785 # DTB hits +system.cpu1.itb.misses 3400 # DTB misses +system.cpu1.itb.accesses 58730185 # DTB accesses +system.cpu1.numCycles 2908727473 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55453570 # Number of instructions committed -system.cpu1.committedOps 66903769 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59172733 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5746 # Number of float alu accesses -system.cpu1.num_func_calls 4791563 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7521701 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59172733 # number of integer instructions -system.cpu1.num_fp_insts 5746 # number of float instructions -system.cpu1.num_int_register_reads 107592864 # number of times the integer registers were read -system.cpu1.num_int_register_writes 40634379 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4256 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 241317525 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25809860 # number of times the CC registers were written -system.cpu1.num_mem_refs 22393766 # number of memory refs -system.cpu1.num_load_insts 12173697 # Number of load instructions -system.cpu1.num_store_insts 10220069 # Number of store instructions -system.cpu1.num_idle_cycles 2697480671.520393 # Number of idle cycles -system.cpu1.num_busy_cycles 205502419.479607 # Number of busy cycles -system.cpu1.not_idle_fraction 0.070790 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.929210 # Percentage of idle cycles -system.cpu1.Branches 12715726 # Number of branches fetched -system.cpu1.op_class::No_OpClass 132 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45969122 67.18% 67.19% # Class of executed instruction -system.cpu1.op_class::IntMult 54656 0.08% 67.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4033 0.01% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu1.op_class::MemRead 12173697 17.79% 85.06% # Class of executed instruction -system.cpu1.op_class::MemWrite 10220069 14.94% 100.00% # Class of executed instruction +system.cpu1.committedInsts 57164215 # Number of instructions committed +system.cpu1.committedOps 68869811 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 60957593 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5807 # Number of float alu accesses +system.cpu1.num_func_calls 5082908 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7664467 # number of instructions that are conditional controls +system.cpu1.num_int_insts 60957593 # number of integer instructions +system.cpu1.num_fp_insts 5807 # number of float instructions +system.cpu1.num_int_register_reads 110918664 # number of times the integer registers were read +system.cpu1.num_int_register_writes 42060766 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4325 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1484 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 248948036 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26157973 # number of times the CC registers were written +system.cpu1.num_mem_refs 23089661 # number of memory refs +system.cpu1.num_load_insts 12644031 # Number of load instructions +system.cpu1.num_store_insts 10445630 # Number of store instructions +system.cpu1.num_idle_cycles 2688977301.144567 # Number of idle cycles +system.cpu1.num_busy_cycles 219750171.855433 # Number of busy cycles +system.cpu1.not_idle_fraction 0.075549 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.924451 # Percentage of idle cycles +system.cpu1.Branches 13165858 # Number of branches fetched +system.cpu1.op_class::No_OpClass 2218 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 47327866 67.15% 67.15% # Class of executed instruction +system.cpu1.op_class::IntMult 56561 0.08% 67.23% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4450 0.01% 67.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.24% # Class of executed instruction +system.cpu1.op_class::MemRead 12644031 17.94% 85.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 10445630 14.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68421709 # Class of executed instruction +system.cpu1.op_class::total 70480756 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::ReadReq 30177 # Transaction distribution +system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1225,9 +1219,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1250,9 +1244,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) @@ -1293,52 +1287,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187451467 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186329023 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.079135 # Cycle average of tags in use +system.iocache.tags.replacements 36418 # number of replacements +system.iocache.tags.tagsinuse 1.084103 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309074032000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.079135 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067446 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067446 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313630728000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084103 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067756 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067756 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.tags.tag_accesses 328068 # Number of tag accesses +system.iocache.tags.data_accesses 328068 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses +system.iocache.ReadReq_misses::total 228 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses -system.iocache.demand_misses::total 234 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 234 # number of overall misses -system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4271859590 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4271859590 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses +system.iocache.demand_misses::total 228 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 228 # number of overall misses +system.iocache.overall_misses::total 228 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28361877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28361877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4696967146 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4696967146 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28361877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28361877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28361877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28361877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1347,14 +1341,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117928.986031 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117928.986031 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124394.197368 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124394.197368 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129664.508227 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129664.508227 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124394.197368 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124394.197368 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1365,22 +1359,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460659590 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2460659590 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16961877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16961877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2885767146 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2885767146 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16961877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16961877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16961877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16961877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1389,262 +1383,262 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67928.986031 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67928.986031 # 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average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74394.197368 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74394.197368 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 89754 # number of replacements -system.l2c.tags.tagsinuse 64926.218037 # Cycle average of tags in use -system.l2c.tags.total_refs 4554949 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 154987 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.389233 # Average number of references to valid blocks. +system.l2c.tags.replacements 87592 # number of replacements +system.l2c.tags.tagsinuse 64865.832577 # Cycle average of tags in use +system.l2c.tags.total_refs 4555575 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 152761 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.821584 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063147 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.034183 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.084248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.042210 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989774 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6804 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40610992 # Number of tag accesses +system.l2c.tags.data_accesses 40610992 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6164 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3132 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6231 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3376 # number of ReadReq hits +system.l2c.ReadReq_hits::total 18903 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 685305 # number of Writeback hits +system.l2c.Writeback_hits::total 685305 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 80673 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 86743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167416 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 834184 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 844481 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1678665 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 252476 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 260979 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 513455 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6164 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3132 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4840380500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5181324000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11051822500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.992938 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989653 # 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mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023424 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.153298 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.195653 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063607 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.153298 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.195653 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063607 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 80150 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20784.773060 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.326909 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20788.029466 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 69500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.462058 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.406861 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.434806 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010582 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.023519 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.023191 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023352 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062674 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062674 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 124500 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70817.211949 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70784.540702 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70801.275046 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66669.360705 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65989.175430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 66281.796739 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70006.241331 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 72779.308658 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72360.123397 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 72569.272698 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67268.994431 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66474.778476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 67177.826952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67268.994431 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66474.778476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 67177.826952 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170523.098254 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184196.745465 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151463.085159 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133848.540832 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182242.319938 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154232.900794 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152127.642532 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 183352.167931 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 152591.019794 # average overall mshr uncacheable latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116781.514727 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117326.893666 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117033.472056 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120607.886822 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122228.169709 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121606.601033 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 121914.474220 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177699.603306 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178593.892462 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163786.068227 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162147.785478 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162195.207154 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162172.387546 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 170429.932045 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 170854.184528 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 163128.939173 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70721 # Transaction distribution +system.membus.trans_dist::ReadResp 70627 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 119469 # Transaction distribution -system.membus.trans_dist::CleanEvict 6488 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::Writeback 117457 # Transaction distribution +system.membus.trans_dist::CleanEvict 6338 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 129210 # Transaction distribution -system.membus.trans_dist::ReadExResp 129210 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30561 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution +system.membus.trans_dist::ReadExReq 127036 # Transaction distribution +system.membus.trans_dist::ReadExResp 127036 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30467 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 445477 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 553069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 661969 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 546371 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655265 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15578364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15741717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15304828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15468181 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18058837 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 394437 # Request fanout histogram +system.membus.pkt_size::total 17785301 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 492 # Total snoops (count) +system.membus.snoop_fanout::samples 389991 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394437 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 389991 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394437 # Request fanout histogram -system.membus.reqLayer0.occupancy 90486000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 389991 # Request fanout histogram +system.membus.reqLayer0.occupancy 90490000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1696500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 834684564 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 821977659 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 964305240 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952225245 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64480996 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64492032 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1910,63 +1910,69 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 74970 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2298377 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 5059453 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540884 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 582 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 582 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 75104 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2297700 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 803098 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1802826 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 802762 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1800707 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2769 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295883 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295883 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1698424 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 524998 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2771 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296210 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296210 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1696651 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 525960 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5081680 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2577380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18024 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34106 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7711190 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108733880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96470557 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24084 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 45196 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205273717 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180370 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5305015 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.037219 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.189299 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5076713 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581153 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18522 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35333 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7711721 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108619704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96660573 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205355921 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176740 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5302052 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018353 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.134225 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5107565 96.28% 96.28% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 197450 3.72% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5204742 98.16% 98.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 97310 1.84% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5305015 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3268607000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5302052 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3269894500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2556658000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2553998500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1277273499 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1279231000 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12003000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12013000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22807000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22931000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index fee5e3090..838105743 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1340669 # Simulator instruction rate (inst/s) -host_op_rate 2744641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34257071569 # Simulator tick rate (ticks/s) -host_mem_usage 654012 # Number of bytes of host memory used -host_seconds 149.23 # Real time elapsed on the host +host_inst_rate 1349307 # Simulator instruction rate (inst/s) +host_op_rate 2762327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34477807791 # Simulator tick rate (ticks/s) +host_mem_usage 659588 # Number of bytes of host memory used +host_seconds 148.27 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -337,9 +337,9 @@ system.cpu.itb_walker_cache.writebacks::total 545 system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 106193 # number of replacements system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4345511 # Total number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4340112 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.539145 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.507414 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor @@ -359,8 +359,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39306136 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39306136 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 39255968 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39255968 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits @@ -456,42 +456,48 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks system.cpu.l2cache.writebacks::total 98168 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 886676 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880405 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 792735 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321418 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377686 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 35029733 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377675 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613331 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 49698 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18776912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002627 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051183 # Request fanout histogram +system.cpu.toL2Bus.snoops 203459 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18930673 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 18727593 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 49319 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18911114 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18776912 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18930673 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -600,7 +606,7 @@ system.membus.trans_dist::ReadResp 13903747 # Tr system.membus.trans_dist::WriteReq 13943 # Transaction distribution system.membus.trans_dist::WriteResp 13943 # Transaction distribution system.membus.trans_dist::Writeback 144835 # Transaction distribution -system.membus.trans_dist::CleanEvict 9844 # Transaction distribution +system.membus.trans_dist::CleanEvict 8392 # Transaction distribution system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution system.membus.trans_dist::ReadExReq 134360 # Transaction distribution @@ -614,11 +620,11 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 471480 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28214040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28360246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28213119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28358794 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) @@ -629,17 +635,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 14257691 # Request fanout histogram +system.membus.snoop_fanout::samples 14256770 # Request fanout histogram system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 14255995 99.99% 99.99% # Request fanout histogram +system.membus.snoop_fanout::1 14255074 99.99% 99.99% # Request fanout histogram system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 14257691 # Request fanout histogram +system.membus.snoop_fanout::total 14256770 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 2f3799b17..aa1e69b35 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.184733 # Number of seconds simulated -sim_ticks 5184732721500 # Number of ticks simulated -final_tick 5184732721500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.194921 # Number of seconds simulated +sim_ticks 5194921252500 # Number of ticks simulated +final_tick 5194921252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 808289 # Simulator instruction rate (inst/s) -host_op_rate 1558079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32570584041 # Simulator tick rate (ticks/s) -host_mem_usage 654268 # Number of bytes of host memory used -host_seconds 159.18 # Real time elapsed on the host -sim_insts 128667033 # Number of instructions simulated -sim_ops 248022101 # Number of ops (including micro ops) simulated +host_inst_rate 862150 # Simulator instruction rate (inst/s) +host_op_rate 1661827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34815163679 # Simulator tick rate (ticks/s) +host_mem_usage 660376 # Number of bytes of host memory used +host_seconds 149.21 # Real time elapsed on the host +sim_insts 128645146 # Number of instructions simulated +sim_ops 247968367 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9044928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 824576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8975232 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9898944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8133056 # Number of bytes written to this memory -system.physmem.bytes_written::total 8133056 # Number of bytes written to this memory +system.physmem.bytes_read::total 9828480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8074432 # Number of bytes written to this memory +system.physmem.bytes_written::total 8074432 # Number of bytes written to this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141327 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140238 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154671 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 127079 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127079 # Number of write requests responded to by this memory +system.physmem.num_reads::total 153570 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126163 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1744531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1909249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159187 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159187 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1568655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1568655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1568655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1727694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1891940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1554293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1554293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1554293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1744531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3477903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154671 # Number of read requests accepted -system.physmem.writeReqs 127079 # Number of write requests accepted -system.physmem.readBursts 154671 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 127079 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9888768 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu.inst 158727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1727694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3446234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 153570 # Number of read requests accepted +system.physmem.writeReqs 126163 # Number of write requests accepted +system.physmem.readBursts 153570 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 126163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9818304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 8131392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9898944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8133056 # Total written bytes from the system interface side +system.physmem.bytesWritten 8073216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9828480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8074432 # Total written bytes from the system interface side system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48348 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9772 # Per bank write bursts -system.physmem.perBankRdBursts::1 9412 # Per bank write bursts -system.physmem.perBankRdBursts::2 9829 # Per bank write bursts -system.physmem.perBankRdBursts::3 9622 # Per bank write bursts -system.physmem.perBankRdBursts::4 9563 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 9720 # Per bank write bursts -system.physmem.perBankRdBursts::7 9664 # Per bank write bursts -system.physmem.perBankRdBursts::8 9219 # Per bank write bursts -system.physmem.perBankRdBursts::9 9313 # Per bank write bursts -system.physmem.perBankRdBursts::10 9431 # Per bank write bursts -system.physmem.perBankRdBursts::11 9415 # Per bank write bursts -system.physmem.perBankRdBursts::12 9985 # Per bank write bursts -system.physmem.perBankRdBursts::13 10194 # Per bank write bursts -system.physmem.perBankRdBursts::14 10163 # Per bank write bursts -system.physmem.perBankRdBursts::15 9855 # Per bank write bursts -system.physmem.perBankWrBursts::0 8316 # Per bank write bursts -system.physmem.perBankWrBursts::1 7960 # Per bank write bursts -system.physmem.perBankWrBursts::2 8144 # Per bank write bursts -system.physmem.perBankWrBursts::3 8236 # Per bank write bursts -system.physmem.perBankWrBursts::4 8504 # Per bank write bursts -system.physmem.perBankWrBursts::5 7731 # Per bank write bursts -system.physmem.perBankWrBursts::6 7974 # Per bank write bursts -system.physmem.perBankWrBursts::7 7835 # Per bank write bursts -system.physmem.perBankWrBursts::8 7118 # Per bank write bursts -system.physmem.perBankWrBursts::9 7555 # Per bank write bursts -system.physmem.perBankWrBursts::10 7609 # Per bank write bursts -system.physmem.perBankWrBursts::11 7637 # Per bank write bursts -system.physmem.perBankWrBursts::12 8092 # Per bank write bursts -system.physmem.perBankWrBursts::13 8095 # Per bank write bursts -system.physmem.perBankWrBursts::14 8240 # Per bank write bursts -system.physmem.perBankWrBursts::15 8007 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48373 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9606 # Per bank write bursts +system.physmem.perBankRdBursts::1 9083 # Per bank write bursts +system.physmem.perBankRdBursts::2 10021 # Per bank write bursts +system.physmem.perBankRdBursts::3 9578 # Per bank write bursts +system.physmem.perBankRdBursts::4 9425 # Per bank write bursts +system.physmem.perBankRdBursts::5 9133 # Per bank write bursts +system.physmem.perBankRdBursts::6 9428 # Per bank write bursts +system.physmem.perBankRdBursts::7 9379 # Per bank write bursts +system.physmem.perBankRdBursts::8 9296 # Per bank write bursts +system.physmem.perBankRdBursts::9 9532 # Per bank write bursts +system.physmem.perBankRdBursts::10 9485 # Per bank write bursts +system.physmem.perBankRdBursts::11 9788 # Per bank write bursts +system.physmem.perBankRdBursts::12 9982 # Per bank write bursts +system.physmem.perBankRdBursts::13 10070 # Per bank write bursts +system.physmem.perBankRdBursts::14 9926 # Per bank write bursts +system.physmem.perBankRdBursts::15 9679 # Per bank write bursts +system.physmem.perBankWrBursts::0 8208 # Per bank write bursts +system.physmem.perBankWrBursts::1 7344 # Per bank write bursts +system.physmem.perBankWrBursts::2 8031 # Per bank write bursts +system.physmem.perBankWrBursts::3 7623 # Per bank write bursts +system.physmem.perBankWrBursts::4 7645 # Per bank write bursts +system.physmem.perBankWrBursts::5 7565 # Per bank write bursts +system.physmem.perBankWrBursts::6 7708 # Per bank write bursts +system.physmem.perBankWrBursts::7 7791 # Per bank write bursts +system.physmem.perBankWrBursts::8 7759 # Per bank write bursts +system.physmem.perBankWrBursts::9 7930 # Per bank write bursts +system.physmem.perBankWrBursts::10 7732 # Per bank write bursts +system.physmem.perBankWrBursts::11 7853 # Per bank write bursts +system.physmem.perBankWrBursts::12 8038 # Per bank write bursts +system.physmem.perBankWrBursts::13 8512 # Per bank write bursts +system.physmem.perBankWrBursts::14 8378 # Per bank write bursts +system.physmem.perBankWrBursts::15 8027 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 5184732588500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5194921069000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154671 # Read request sizes (log2) +system.physmem.readPktSize::6 153570 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 127079 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126163 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -152,189 +152,188 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6964 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 55882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.466912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.971568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.231986 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19566 35.01% 35.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13855 24.79% 59.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5752 10.29% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3280 5.87% 75.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2436 4.36% 80.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1597 2.86% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1106 1.98% 85.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 958 1.71% 86.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7332 13.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 55882 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5902 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.177906 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 623.301246 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5901 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::51 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 55967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.678668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.248377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.031309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19371 34.61% 34.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13720 24.51% 59.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6335 11.32% 70.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3428 6.13% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2404 4.30% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1641 2.93% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1130 2.02% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 964 1.72% 87.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6974 12.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 55967 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5838 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.276465 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 626.709863 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5837 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5902 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5902 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.527109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.363013 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.814592 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4841 82.02% 82.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 49 0.83% 82.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 261 4.42% 87.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 70 1.19% 88.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 69 1.17% 89.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 251 4.25% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.37% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 13 0.22% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.25% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 235 3.98% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.14% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.46% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5902 # Writes before turning the bus around for reads -system.physmem.totQLat 1454171981 # Total ticks spent queuing -system.physmem.totMemAccLat 4351271981 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9411.39 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5838 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5838 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.607400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.425561 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.518520 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4794 82.12% 82.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.88% 84.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 38 0.65% 84.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 229 3.92% 88.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 28 0.48% 89.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 201 3.44% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 72 1.23% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 93.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.21% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 30 0.51% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.10% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 233 3.99% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 31 0.53% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.27% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5838 # Writes before turning the bus around for reads +system.physmem.totQLat 1519267484 # Total ticks spent queuing +system.physmem.totMemAccLat 4395723734 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 767055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9903.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28161.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28653.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 126926 # Number of row buffer hits during reads -system.physmem.writeRowHits 98756 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.71 # Row buffer hit rate for writes -system.physmem.avgGap 18401890.29 # Average gap between requests -system.physmem.pageHitRate 80.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 207522000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 113231250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 600100800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 419256000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 134001495225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2993293881750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3467276945505 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.747605 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4979520185732 # Time in different power states -system.physmem_0.memoryStateTime::REF 173129580000 # Time in different power states +system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing +system.physmem.readRowHits 125316 # Number of row buffer hits during reads +system.physmem.writeRowHits 98271 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.89 # Row buffer hit rate for writes +system.physmem.avgGap 18570998.31 # Average gap between requests +system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 205775640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 112278375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 590093400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 401209200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 136710410535 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2997028289250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3474354711360 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.798995 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4985717898976 # Time in different power states +system.physmem_0.memoryStateTime::REF 173469660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32082834268 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35728624774 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214945920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117282000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 605085000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 404047440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134530881300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2992829508000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3467343208140 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.760386 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4978746411720 # Time in different power states -system.physmem_1.memoryStateTime::REF 173129580000 # Time in different power states +system.physmem_1.actEnergy 217334880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118585500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 606504600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 416203920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 137303657415 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2996507897250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3474476838525 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.822504 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4984854152228 # Time in different power states +system.physmem_1.memoryStateTime::REF 173469660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32855777030 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36597268272 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10369465443 # number of cpu cycles simulated +system.cpu.numCycles 10389842505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128667033 # Number of instructions committed -system.cpu.committedOps 248022101 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232599125 # Number of integer alu accesses +system.cpu.committedInsts 128645146 # Number of instructions committed +system.cpu.committedOps 247968367 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232546073 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2317363 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23194478 # number of instructions that are conditional controls -system.cpu.num_int_insts 232599125 # number of integer instructions +system.cpu.num_func_calls 2315361 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23194066 # number of instructions that are conditional controls +system.cpu.num_int_insts 232546073 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 435753384 # number of times the integer registers were read -system.cpu.num_int_register_writes 198362025 # number of times the integer registers were written +system.cpu.num_int_register_reads 435625867 # number of times the integer registers were read +system.cpu.num_int_register_writes 198317571 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133133176 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95670461 # number of times the CC registers were written -system.cpu.num_mem_refs 22356642 # number of memory refs -system.cpu.num_load_insts 13946240 # Number of load instructions -system.cpu.num_store_insts 8410402 # Number of store instructions -system.cpu.num_idle_cycles 9769457503.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600007939.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057863 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942137 # Percentage of idle cycles -system.cpu.Branches 26370667 # Number of branches fetched -system.cpu.op_class::No_OpClass 172538 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225235379 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140393 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123647 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 133116487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95666128 # number of times the CC registers were written +system.cpu.num_mem_refs 22339099 # number of memory refs +system.cpu.num_load_insts 13935933 # Number of load instructions +system.cpu.num_store_insts 8403166 # Number of store instructions +system.cpu.num_idle_cycles 9774871363.998119 # Number of idle cycles +system.cpu.num_busy_cycles 614971141.001882 # Number of busy cycles +system.cpu.not_idle_fraction 0.059190 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940810 # Percentage of idle cycles +system.cpu.Branches 26367781 # Number of branches fetched +system.cpu.op_class::No_OpClass 172241 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225200251 90.82% 90.89% # Class of executed instruction +system.cpu.op_class::IntMult 140056 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123237 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -361,215 +360,215 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13941273 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8410402 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13930961 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8403166 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248023648 # Class of executed instruction +system.cpu.op_class::total 247969928 # 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number of replacements +system.cpu.dcache.tags.tagsinuse 511.995361 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20131143 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623840 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.397245 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995361 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88751069 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88751069 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12012436 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12012436 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8077606 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8077606 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59170 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59170 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8402408 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8402408 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461708 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461708 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21320665 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21320665 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21782373 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21782373 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070119 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070119 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038656 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038656 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871845 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871845 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057720 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057720 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074976 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074976 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14144.598105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14144.598105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37337.758016 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37337.758016 # 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number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20070308 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20070308 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20128970 # number of overall hits +system.cpu.dcache.overall_hits::total 20128970 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906883 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906883 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325772 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403210 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403210 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232655 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1232655 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1635865 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8395187 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8395187 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21302963 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21302963 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21764835 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21764835 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070259 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070259 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038805 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038805 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872991 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872991 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075161 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075161 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.902098 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.902098 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56160.007542 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56160.007542 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25835.221515 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25835.221515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19467.324612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19467.324612 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15094 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 441 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.527778 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.226757 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11904745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11904745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11312729479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11312729479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5814985000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5814985000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23217474979 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23217474979 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29032459979 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29032459979 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684333500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684333500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622247500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622247500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97306581000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 97306581000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070097 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070097 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037574 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037574 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871772 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871772 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057280 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057280 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074544 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074544 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.672181 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.672181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35832.774736 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35832.774736 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14447.024129 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14447.024129 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19011.363005 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19011.363005 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17879.927020 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17879.927020 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.431581 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.431581 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188433.996838 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188433.996838 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165806.023480 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165806.023480 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586874 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 586874 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12641489000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12641489000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17000944477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17000944477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6508610000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6508610000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29642433477 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29642433477 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36151043477 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36151043477 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684331000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684331000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622740500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622740500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97307071500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 97307071500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070236 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872913 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872913 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074711 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074711 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.982457 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.982457 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53749.089405 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53749.089405 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16143.426907 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16143.426907 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24239.596986 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24239.596986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22232.197983 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22232.197983 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.427218 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.427218 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188415.265805 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188415.265805 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165805.729168 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165805.729168 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7782 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.044171 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13071 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7797 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.676414 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5158049844500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.044171 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315261 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315261 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 7724 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13169 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7738 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.701861 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5166372049500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53116 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53116 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13073 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13073 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13073 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13073 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13073 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13073 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8990 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8990 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8990 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8990 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8990 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8990 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97324000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97324000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97324000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 97324000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97324000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 97324000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22063 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22063 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22063 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22063 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22063 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22063 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407470 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407470 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407470 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407470 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407470 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407470 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10825.806452 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10825.806452 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10825.806452 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13186 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13186 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13186 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13186 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13186 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13186 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8927 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8927 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8927 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8927 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8927 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8927 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97243000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97243000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97243000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 97243000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97243000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 97243000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22113 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22113 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22113 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22113 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22113 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22113 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403699 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403699 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403699 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403699 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403699 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403699 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10893.133191 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10893.133191 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10893.133191 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,86 +577,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8990 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8990 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8990 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8990 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8990 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8990 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88334000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88334000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88334000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88334000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88334000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88334000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407470 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407470 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407470 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9825.806452 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2877 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2877 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8927 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8927 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8927 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8927 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8927 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8927 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88316000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88316000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88316000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88316000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88316000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88316000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.403699 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.403699 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.403699 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9893.133191 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 792637 # number of replacements -system.cpu.icache.tags.tagsinuse 510.330403 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144952019 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 793149 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.755093 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161555480500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.330403 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996739 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996739 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 789867 # number of replacements +system.cpu.icache.tags.tagsinuse 510.214824 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144930127 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 790379 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 183.367887 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 164495636500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.214824 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996513 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996513 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146538331 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146538331 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144952019 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144952019 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144952019 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144952019 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144952019 # number of overall hits -system.cpu.icache.overall_hits::total 144952019 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 793156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 793156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 793156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 793156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 793156 # number of overall misses -system.cpu.icache.overall_misses::total 793156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11221653000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11221653000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11221653000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11221653000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11221653000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11221653000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145745175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145745175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145745175 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145745175 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145745175 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145745175 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005442 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005442 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005442 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005442 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005442 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005442 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14148.103274 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14148.103274 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14148.103274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14148.103274 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146510899 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146510899 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144930127 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144930127 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144930127 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144930127 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144930127 # number of overall hits +system.cpu.icache.overall_hits::total 144930127 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 790386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 790386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 790386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 790386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 790386 # number of overall misses +system.cpu.icache.overall_misses::total 790386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11833714500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11833714500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11833714500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11833714500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11833714500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11833714500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145720513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145720513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145720513 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145720513 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145720513 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145720513 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005424 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005424 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005424 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005424 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005424 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005424 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14972.069976 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14972.069976 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14972.069976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14972.069976 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -666,88 +665,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793156 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 793156 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 793156 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 793156 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 793156 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 793156 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10428497000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10428497000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10428497000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10428497000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10428497000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10428497000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005442 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005442 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005442 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13148.103274 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13148.103274 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790386 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 790386 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 790386 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 790386 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 790386 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 790386 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11043328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11043328500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11043328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11043328500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11043328500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11043328500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005424 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005424 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005424 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13972.069976 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13972.069976 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3538 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.060279 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7930 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3549 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.234432 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161245744500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.060279 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191267 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191267 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3784 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.071212 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7587 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3797 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.998156 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5168596607500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071212 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191951 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191951 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29062 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29062 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7929 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7929 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29077 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29077 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7587 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7587 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7931 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7931 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7931 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7931 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4400 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4400 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4400 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4400 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4400 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4400 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45407000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45407000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45407000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 45407000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45407000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 45407000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12329 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12329 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7589 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7589 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7589 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7589 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4633 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4633 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4633 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4633 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4633 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4633 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48911500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48911500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48911500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 48911500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48911500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 48911500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12331 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12331 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12331 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12331 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356882 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356882 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356824 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.356824 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356824 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.356824 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10319.772727 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10319.772727 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10319.772727 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.379133 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.379133 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.379071 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.379071 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.379071 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.379071 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10557.198360 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10557.198360 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10557.198360 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,169 +755,169 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 796 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 796 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4400 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4400 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4400 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4400 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 41007000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 41007000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 41007000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 41007000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 41007000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 41007000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356882 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356882 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356824 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356824 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9319.772727 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 721 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 721 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4633 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4633 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4633 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4633 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4633 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4633 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 44278500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 44278500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 44278500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 44278500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 44278500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 44278500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.379133 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.379133 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.379071 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.379071 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9557.198360 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87263 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64757.225173 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4369524 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151965 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 28.753489 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 86240 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64592.333945 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4367637 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 150989 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 28.926856 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50419.617435 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.145028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3328.329800 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11009.132909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.769342 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50133.527739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3457.643805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11001.015544 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.764977 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050786 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.167986 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.988117 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64702 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5302 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56392 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987274 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39224493 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39224493 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1541775 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1541775 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 307 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 307 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199754 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199754 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 780246 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 780246 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6724 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3018 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1278797 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1288539 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6724 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3018 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 780246 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1478551 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2268539 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6724 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3018 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 780246 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1478551 # number of overall hits -system.cpu.l2cache.overall_hits::total 2268539 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1367 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1367 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113781 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113781 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12897 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 12897 # number of ReadCleanReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.167862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.985601 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64749 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56598 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987991 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 39213781 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39213781 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1544059 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1544059 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 298 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 298 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 201469 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 201469 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 777488 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 777488 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6514 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3101 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280565 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1290180 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6514 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3101 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 777488 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1482034 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2269137 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6514 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3101 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777488 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1482034 # number of overall hits +system.cpu.l2cache.overall_hits::total 2269137 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1394 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1394 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 112654 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 112654 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12885 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 12885 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28476 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 28481 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28510 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 28515 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12897 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142257 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3452410000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 587500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1562149500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16617922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18180659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1562149500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16617922500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18180659500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 87522404000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 87522404000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2462660500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2462660500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89985064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89985064500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816607 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816607 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362897 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362897 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016261 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021783 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021625 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.064017 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.064017 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21240.673007 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21240.673007 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66412.599643 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66412.599643 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70879.002869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70879.002869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 70300 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71770.350471 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71770.092342 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.424600 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.424600 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176933.996838 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176933.996838 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.728901 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.728901 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823877 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823877 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358630 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358630 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016302 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021624 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063575 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063575 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71385.581062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71385.581062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 116872.015197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 116872.015197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121074.096808 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121073.470103 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.423727 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.423727 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176915.265805 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176915.265805 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.444651 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.444651 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 4854729 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2424193 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1088 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1088 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 572954 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2687857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1668857 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 884964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 793156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322272 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2686987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1670227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2186 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 790386 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378925 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6040657 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20226 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8448782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50761152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203819691 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 629120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255454379 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 189246 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5626152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.032703 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.177859 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2370613 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6047740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8447236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50583872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204138427 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 601024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255568251 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 188441 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5624579 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.080591 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5442159 96.73% 96.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 183993 3.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5604820 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14130 0.25% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5629 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5626152 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4269812500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5624579 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4271820500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 588787 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1189734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1185579000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3013374987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3016848998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6600000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6949500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13485000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13390500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 226549 # Transaction distribution -system.iobus.trans_dist::ReadResp 226549 # Transaction distribution +system.iobus.trans_dist::ReadReq 226550 # Transaction distribution +system.iobus.trans_dist::ReadResp 226550 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 57726 # Transaction distribution -system.iobus.trans_dist::MessageReq 1652 # Transaction distribution -system.iobus.trans_dist::MessageResp 1652 # Transaction distribution +system.iobus.trans_dist::MessageReq 1654 # Transaction distribution +system.iobus.trans_dist::MessageResp 1654 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1095,11 +1100,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 473420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 571854 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 571860 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1119,12 +1124,12 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 242990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276902 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3939784 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276918 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1160,54 +1165,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 242362178 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 240989862 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 462414000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50042000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50044000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47510 # number of replacements -system.iocache.tags.tagsinuse 0.095938 # Cycle average of tags in use +system.iocache.tags.replacements 47511 # number of replacements +system.iocache.tags.tagsinuse 0.108299 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5046145075000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095938 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005996 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005996 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5048321264000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108299 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006769 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428085 # Number of tag accesses -system.iocache.tags.data_accesses 428085 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 845 # number of ReadReq misses -system.iocache.ReadReq_misses::total 845 # number of ReadReq misses +system.iocache.tags.tag_accesses 428094 # Number of tag accesses +system.iocache.tags.data_accesses 428094 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses +system.iocache.ReadReq_misses::total 846 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 845 # number of demand (read+write) misses -system.iocache.demand_misses::total 845 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 845 # number of overall misses -system.iocache.overall_misses::total 845 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 134017694 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 134017694 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5509470484 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5509470484 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 134017694 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 134017694 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 134017694 # number of overall miss cycles -system.iocache.overall_miss_latency::total 134017694 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 845 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 845 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses +system.iocache.demand_misses::total 846 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses +system.iocache.overall_misses::total 846 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144199688 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144199688 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6059543174 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6059543174 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144199688 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144199688 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144199688 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144199688 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 845 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 845 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 845 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 845 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1216,40 +1221,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158600.821302 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 117925.310017 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 117925.310017 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 158600.821302 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 158600.821302 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 170448.803783 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129699.126156 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129699.126156 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 170448.803783 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 170448.803783 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 693 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 36 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.178571 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 19.250000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 845 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 845 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 845 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 845 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 845 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 91767694 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3173470484 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3173470484 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 91767694 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 91767694 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 101899688 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3723543174 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3723543174 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 101899688 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 101899688 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1258,73 +1263,73 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108600.821302 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67925.310017 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67925.310017 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 120448.803783 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79699.126156 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79699.126156 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 572954 # Transaction distribution -system.membus.trans_dist::ReadResp 615177 # Transaction distribution -system.membus.trans_dist::WriteReq 13916 # Transaction distribution -system.membus.trans_dist::WriteResp 13916 # Transaction distribution -system.membus.trans_dist::Writeback 127079 # Transaction distribution -system.membus.trans_dist::CleanEvict 7222 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2154 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1646 # Transaction distribution -system.membus.trans_dist::ReadExReq 113502 # Transaction distribution -system.membus.trans_dist::ReadExResp 113502 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42223 # Transaction distribution -system.membus.trans_dist::MessageReq 1652 # Transaction distribution -system.membus.trans_dist::MessageResp 1652 # Transaction distribution +system.membus.trans_dist::ReadResp 615200 # Transaction distribution +system.membus.trans_dist::WriteReq 13920 # Transaction distribution +system.membus.trans_dist::WriteResp 13920 # Transaction distribution +system.membus.trans_dist::Writeback 126163 # Transaction distribution +system.membus.trans_dist::CleanEvict 7113 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2165 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1671 # Transaction distribution +system.membus.trans_dist::ReadExReq 112377 # Transaction distribution +system.membus.trans_dist::ReadExResp 112377 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42246 # Transaction distribution +system.membus.trans_dist::MessageReq 1654 # Transaction distribution +system.membus.trans_dist::MessageResp 1654 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 473420 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 400152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1573892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1718963 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 396961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1570709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1715783 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242990 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15016960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16660587 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400653 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14887872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16531515 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19682235 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1580 # Total snoops (count) -system.membus.snoop_fanout::samples 927896 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001780 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.042157 # Request fanout histogram +system.membus.pkt_size::total 19553171 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1565 # Total snoops (count) +system.membus.snoop_fanout::samples 925791 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001787 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.042230 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 926244 99.82% 99.82% # Request fanout histogram -system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 924137 99.82% 99.82% # Request fanout histogram +system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 927896 # Request fanout histogram -system.membus.reqLayer0.occupancy 359896000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 925791 # Request fanout histogram +system.membus.reqLayer0.occupancy 359890000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 527973000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 527983500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 848970266 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 843164843 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2157850870 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2152042345 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85904679 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85908558 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 1a6e00d22..e3deed2b6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37552000 # Number of ticks simulated -final_tick 37552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37553000 # Number of ticks simulated +final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72134 # Simulator instruction rate (inst/s) -host_op_rate 72118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 423067865 # Simulator tick rate (ticks/s) -host_mem_usage 288748 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 161315 # Simulator instruction rate (inst/s) +host_op_rate 161262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 945919395 # Simulator tick rate (ticks/s) +host_mem_usage 296228 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 620366425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 288027269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 908393694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 620366425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 620366425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 620366425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 288027269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 908393694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 620349905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 288019599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 908369504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 620349905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 620349905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 620349905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 288019599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 908369504 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37447500 # Total gap between requests +system.physmem.totGap 37448500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2665000 # To system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 908.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 908.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 908.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 908.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.10 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70257.97 # Average gap between requests +system.physmem.avgGap 70259.85 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ) @@ -293,24 +293,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75104 # number of cpu cycles simulated +system.cpu.numCycles 75106 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.735000 # CPI: cycles per instruction -system.cpu.ipc 0.085215 # IPC: instructions per cycle +system.cpu.cpi 11.735312 # CPI: cycles per instruction +system.cpu.ipc 0.085213 # IPC: instructions per cycle system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62587 # Total number of cycles that the object has spent stopped +system.cpu.idleCycles 62589 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.919220 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.920661 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.919220 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 103.920661 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id @@ -417,14 +417,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.811080 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 175.815240 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.811080 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085845 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.815240 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085847 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085847 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id @@ -443,12 +443,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27931500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27931500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27931500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27931500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27931500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27931500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27932500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27932500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27932500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27932500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27932500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27932500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses @@ -461,12 +461,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.137684 system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76524.657534 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76524.657534 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76524.657534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76524.657534 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76527.397260 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76527.397260 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76527.397260 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76527.397260 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,33 +481,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27566500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27566500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27566500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27566500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27566500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27566500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27567500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27567500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75524.657534 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75524.657534 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75527.397260 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75527.397260 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.447652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.452540 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.824515 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.828674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623866 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy @@ -640,6 +640,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -653,14 +659,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001873 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043274 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 533 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 85a8b430a..58b2620bf 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21900500 # Number of ticks simulated final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43231 # Simulator instruction rate (inst/s) -host_op_rate 43225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 148545474 # Simulator tick rate (ticks/s) -host_mem_usage 289772 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 94413 # Simulator instruction rate (inst/s) +host_op_rate 94393 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 324370159 # Simulator tick rate (ticks/s) +host_mem_usage 297000 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -698,12 +698,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id @@ -724,12 +724,12 @@ system.cpu.icache.demand_misses::cpu.inst 459 # n system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses system.cpu.icache.overall_misses::total 459 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32352500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32352500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32352500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32352500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32352500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32352500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses @@ -742,12 +742,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.220038 system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70484.749455 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70484.749455 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70484.749455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70484.749455 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,24 +768,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 311 system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23859500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23859500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23859500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23859500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23859500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23859500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76718.649518 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76718.649518 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use @@ -927,6 +927,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution @@ -940,14 +946,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 2c1174c59..e7401ee31 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32544500 # Number of ticks simulated -final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32545500 # Number of ticks simulated +final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 619666 # Simulator instruction rate (inst/s) -host_op_rate 618826 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3148046044 # Simulator tick rate (ticks/s) -host_mem_usage 291528 # Number of bytes of host memory used +host_inst_rate 507828 # Simulator instruction rate (inst/s) +host_op_rate 507304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581337246 # Simulator tick rate (ticks/s) +host_mem_usage 294696 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65089 # number of cpu cycles simulated +system.cpu.numCycles 65091 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65089 # Number of busy cycles +system.cpu.num_busy_cycles 65091 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.755352 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.755352 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id @@ -226,14 +226,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.988451 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.988451 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062494 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062494 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,36 +290,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15024500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15024500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53851.254480 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53851.254480 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.465722 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.994443 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.471279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -462,14 +468,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 2f7c0906a..a420f2b35 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20075000 # Number of ticks simulated final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42420 # Simulator instruction rate (inst/s) -host_op_rate 42407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329231154 # Simulator tick rate (ticks/s) -host_mem_usage 287436 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 131673 # Simulator instruction rate (inst/s) +host_op_rate 131586 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1021264689 # Simulator tick rate (ticks/s) +host_mem_usage 295944 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -634,6 +634,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 308 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -647,15 +653,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 6ee889334..c4983f8bd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 12363500 # Number of ticks simulated final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20992 # Simulator instruction rate (inst/s) -host_op_rate 20989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108692792 # Simulator tick rate (ticks/s) -host_mem_usage 288464 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 79745 # Simulator instruction rate (inst/s) +host_op_rate 79707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 412680664 # Simulator tick rate (ticks/s) +host_mem_usage 295680 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -919,6 +919,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution @@ -932,15 +938,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 7411927e4..6bacfac4e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000017 # Nu sim_ticks 16524500 # Number of ticks simulated final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 374183 # Simulator instruction rate (inst/s) -host_op_rate 373424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2390351512 # Simulator tick rate (ticks/s) -host_mem_usage 291260 # Number of bytes of host memory used +host_inst_rate 315037 # Simulator instruction rate (inst/s) +host_op_rate 314537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2013954906 # Simulator tick rate (ticks/s) +host_mem_usage 293376 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -443,6 +443,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -456,15 +462,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 3e86bd3ac..ffa31a0bc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29941500 # Number of ticks simulated -final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29949500 # Number of ticks simulated +final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58660 # Simulator instruction rate (inst/s) -host_op_rate 68656 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 381226078 # Simulator tick rate (ticks/s) -host_mem_usage 304332 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 110305 # Simulator instruction rate (inst/s) +host_op_rate 129095 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 716958322 # Simulator tick rate (ticks/s) +host_mem_usage 313816 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29851000 # Total gap between requests +system.physmem.totGap 29858000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # By system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2218000 # Total ticks spent queuing -system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2201000 # Total ticks spent queuing +system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.03 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70904.99 # Average gap between requests +system.physmem.avgGap 70921.62 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) @@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 59883 # number of cpu cycles simulated +system.cpu.numCycles 59899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.003909 # CPI: cycles per instruction -system.cpu.ipc 0.076900 # IPC: instructions per cycle +system.cpu.cpi 13.007383 # CPI: cycles per instruction +system.cpu.ipc 0.076879 # IPC: instructions per cycle system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped +system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.506122 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id @@ -423,14 +423,14 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6956500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11976000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11976000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11976000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11976000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -451,14 +451,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65802.197802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65802.197802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,14 +483,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9551500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9551500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -499,24 +499,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.800750 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.800750 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079004 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079004 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id @@ -535,12 +535,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23597500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23597500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23597500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23597500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23597500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23597500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses @@ -553,12 +553,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73284.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73284.161491 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,34 +573,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id @@ -633,16 +633,16 @@ system.cpu.l2cache.overall_misses::cpu.data 124 # system.cpu.l2cache.overall_misses::total 429 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) @@ -669,16 +669,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -707,16 +707,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 116 system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26968500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19564000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses @@ -731,17 +731,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -756,14 +762,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 471 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) @@ -791,7 +797,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 491000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index be50d79db..0d7cf1bb4 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17163000 # Number of ticks simulated -final_tick 17163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17170000 # Number of ticks simulated +final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25428 # Simulator instruction rate (inst/s) -host_op_rate 29777 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95019968 # Simulator tick rate (ticks/s) -host_mem_usage 305352 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 50361 # Simulator instruction rate (inst/s) +host_op_rate 58973 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188251031 # Simulator tick rate (ticks/s) +host_mem_usage 313812 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025461749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 451203170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1476664919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025461749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025461749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025461749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 451203170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1476664919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1025043681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451019220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1476062900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1025043681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1025043681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1025043681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451019220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1476062900 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17090000 # Total gap between requests +system.physmem.totGap 17097000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # By system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3055250 # Total ticks spent queuing -system.physmem.totMemAccLat 10480250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3045250 # Total ticks spent queuing +system.physmem.totMemAccLat 10470250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7715.28 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7690.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26465.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1476.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26440.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1476.06 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1476.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1476.06 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.54 # Data bus utilization in percentage -system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.53 # Data bus utilization in percentage +system.physmem.busUtilRead 11.53 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,21 +220,21 @@ system.physmem.readRowHits 330 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43156.57 # Average gap between requests +system.physmem.avgGap 43174.24 # Average gap between requests system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10798650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14428830 # Total energy per rank (pJ) -system.physmem_0.averagePower 911.198611 # Core power per rank (mW) +system.physmem_0.totalEnergy 14433105 # Total energy per rank (pJ) +system.physmem_0.averagePower 911.108972 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16176750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16183750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) @@ -245,18 +245,18 @@ system.physmem_1.actBackEnergy 10407915 # En system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ) system.physmem_1.averagePower 807.028896 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 665250 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 672250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2533 # Number of BP lookups -system.cpu.branchPred.condPredicted 1576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 452 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2102 # Number of BTB lookups -system.cpu.branchPred.BTBHits 812 # Number of BTB hits +system.cpu.branchPred.lookups 2537 # Number of BP lookups +system.cpu.branchPred.condPredicted 1577 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 453 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2106 # Number of BTB lookups +system.cpu.branchPred.BTBHits 814 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.629876 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.651472 # BTB Hit Percentage system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -496,95 +496,95 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34327 # number of cpu cycles simulated +system.cpu.numCycles 34341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7647 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11725 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2533 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1133 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4667 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 953 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11733 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2537 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1135 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4671 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 955 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.059729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.422792 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13078 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.059336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.422082 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10498 80.39% 80.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 262 2.01% 82.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.65% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 219 1.68% 85.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 263 2.01% 87.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 312 2.39% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 142 1.09% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.21% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 990 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10515 80.40% 80.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 260 1.99% 82.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 215 1.64% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 219 1.67% 85.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 267 2.04% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 312 2.39% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 1.09% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 157 1.20% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 991 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.073790 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.341568 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4216 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 13078 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073877 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.341662 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6351 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4223 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2063 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 321 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 380 # Number of times decode resolved a branch +system.cpu.decode.UnblockCycles 119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 322 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11316 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11299 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 321 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6551 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 647 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2328 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1964 # Number of cycles rename is running +system.cpu.rename.SquashCycles 322 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6564 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 644 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2338 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1962 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 10673 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 10655 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10857 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 48954 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 11788 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 10847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 48852 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 11762 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5363 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5353 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 42 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2126 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1537 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2118 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1531 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9711 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9695 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7972 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7975 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4379 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10941 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4363 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10837 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13059 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.610460 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.342240 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.609803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.341106 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9876 75.63% 75.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1174 8.99% 84.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 5.84% 90.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 454 3.48% 93.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 326 2.50% 96.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.13% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 116 0.89% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9890 75.62% 75.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1180 9.02% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 5.83% 90.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 451 3.45% 93.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 329 2.52% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.13% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 115 0.88% 99.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13078 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available @@ -620,69 +620,69 @@ system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4885 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1831 22.97% 84.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1246 15.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4886 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1833 22.98% 84.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1246 15.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7972 # Type of FU issued -system.cpu.iq.rate 0.232237 # Inst issue rate +system.cpu.iq.FU_type_0::total 7975 # Type of FU issued +system.cpu.iq.rate 0.232230 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019067 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29107 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14039 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7309 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019060 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14007 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7313 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8081 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8084 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1099 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1091 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 599 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 593 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 321 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 613 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 322 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 611 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 9766 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 9750 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2126 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1537 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2118 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1531 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall @@ -690,43 +690,43 @@ system.cpu.iew.memOrderViolationEvents 19 # Nu system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7697 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 275 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 274 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2930 # number of memory reference insts executed -system.cpu.iew.exec_branches 1433 # Number of branches executed -system.cpu.iew.exec_stores 1194 # Number of stores executed -system.cpu.iew.exec_rate 0.224226 # Inst execution rate -system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7341 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3456 # num instructions producing a value -system.cpu.iew.wb_consumers 6757 # num instructions consuming a value +system.cpu.iew.exec_refs 2933 # number of memory reference insts executed +system.cpu.iew.exec_branches 1435 # Number of branches executed +system.cpu.iew.exec_stores 1197 # Number of stores executed +system.cpu.iew.exec_rate 0.224251 # Inst execution rate +system.cpu.iew.wb_sent 7436 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7345 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3459 # num instructions producing a value +system.cpu.iew.wb_consumers 6763 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.213855 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511470 # average fanout of values written-back +system.cpu.iew.wb_rate 0.213884 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511459 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4387 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4371 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 297 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12286 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.437734 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.284067 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 298 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.437023 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.282384 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10235 83.31% 83.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 882 7.18% 90.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.42% 93.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 222 1.81% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.90% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 213 1.73% 98.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 51 0.42% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.33% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10254 83.33% 83.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 882 7.17% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.41% 93.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 223 1.81% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 112 0.91% 96.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 213 1.73% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 51 0.41% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.33% 99.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12306 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -773,32 +773,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21783 # The number of ROB reads -system.cpu.rob.rob_writes 20313 # The number of ROB writes -system.cpu.timesIdled 192 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21268 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21787 # The number of ROB reads +system.cpu.rob.rob_writes 20281 # The number of ROB writes +system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21263 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.475392 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.475392 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7631 # number of integer regfile reads +system.cpu.cpi 7.478441 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.478441 # CPI: Total CPI of All Threads +system.cpu.ipc 0.133718 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.133718 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7636 # number of integer regfile reads system.cpu.int_regfile_writes 4176 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27375 # number of cc regfile reads -system.cpu.cc_regfile_writes 3204 # number of cc regfile writes -system.cpu.misc_regfile_reads 3054 # number of misc regfile reads +system.cpu.cc_regfile_reads 27387 # number of cc regfile reads +system.cpu.cc_regfile_writes 3201 # number of cc regfile writes +system.cpu.misc_regfile_reads 3057 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.851603 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 87.846363 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.851603 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021448 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021448 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.846363 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021447 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021447 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id @@ -827,16 +827,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10572000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10572000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22577500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22577500 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10593000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10593000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22578500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22578500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33149500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33149500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33149500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33149500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33171500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33171500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33171500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33171500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -859,16 +859,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.196838 system.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58408.839779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58408.839779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71222.397476 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71222.397476 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58524.861878 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58524.861878 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71225.552050 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71225.552050 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66565.261044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66565.261044 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66609.437751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66609.437751 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -895,14 +895,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6969000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6969000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3397000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3397000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10366000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10366000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10366000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10366000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6985000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6985000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10383000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10383000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses @@ -911,66 +911,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103 system.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66371.428571 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66371.428571 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80880.952381 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80880.952381 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66523.809524 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66523.809524 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.741808 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1582 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.742670 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1585 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.399317 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.409556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.741808 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073116 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.742670 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073117 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073117 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4229 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4229 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1582 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1582 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1582 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1582 # number of overall hits -system.cpu.icache.overall_hits::total 1582 # number of overall hits +system.cpu.icache.tags.tag_accesses 4235 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4235 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1585 # number of overall hits +system.cpu.icache.overall_hits::total 1585 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses system.cpu.icache.overall_misses::total 386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26869500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26869500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26869500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26869500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26869500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26869500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196138 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196138 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196138 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196138 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196138 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196138 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69610.103627 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69610.103627 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69610.103627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69610.103627 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26879500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26879500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26879500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26879500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26879500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26879500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195840 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195840 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195840 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195840 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195840 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195840 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69636.010363 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69636.010363 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69636.010363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69636.010363 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -991,33 +991,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 293 system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21385500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21385500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21385500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21385500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21385500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21385500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148882 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148882 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148882 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72988.054608 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72988.054608 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21398500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21398500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21398500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21398500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21398500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21398500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148656 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148656 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148656 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73032.423208 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73032.423208 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 187.228350 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 187.228140 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.551776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.676574 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.553706 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.674434 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy @@ -1051,16 +1051,16 @@ system.cpu.l2cache.overall_misses::cpu.data 126 # system.cpu.l2cache.overall_misses::total 401 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20756000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 20756000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6584500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6584500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20756000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9917500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30673500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20756000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9917500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30673500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20751000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 20751000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6579500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6579500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20751000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9912500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30663500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20751000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9912500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30663500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) @@ -1087,16 +1087,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75476.363636 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75476.363636 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78386.904762 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78386.904762 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76492.518703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76492.518703 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75458.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75458.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78327.380952 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78327.380952 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76467.581047 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76467.581047 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1125,16 +1125,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 121 system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18006000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18006000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5464000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5464000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18006000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8377000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26383000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18006000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8377000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26383000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18001000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18001000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18001000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8372000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26373000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18001000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8372000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26373000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses @@ -1149,17 +1149,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65476.363636 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65476.363636 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69164.556962 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65458.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65458.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69101.265823 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69101.265823 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 441 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 44 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution @@ -1173,14 +1179,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.102041 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.303046 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 396 89.80% 89.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 45 10.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index c7177147a..8015f8322 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17777000 # Number of ticks simulated -final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17778000 # Number of ticks simulated +final_tick 17778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63242 # Simulator instruction rate (inst/s) -host_op_rate 74054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244740900 # Simulator tick rate (ticks/s) -host_mem_usage 307828 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 58925 # Simulator instruction rate (inst/s) +host_op_rate 69000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 228057572 # Simulator tick rate (ticks/s) +host_mem_usage 310616 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst 271 # Nu system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975642684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 388817011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 97204253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1461663948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975642684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975642684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975642684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 388817011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 97204253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1461663948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 975587805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 388795140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 97198785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1461581730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975587805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975587805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975587805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 388795140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 97198785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1461581730 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue @@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17763500 # Total gap between requests +system.physmem.totGap 17764500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -204,15 +204,15 @@ system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # By system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3130500 # Total ticks spent queuing -system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3121500 # Total ticks spent queuing +system.physmem.totMemAccLat 10752750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7669.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26419.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1465.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1465.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 11.45 # Data bus utilization in percentage @@ -224,35 +224,35 @@ system.physmem.readRowHits 340 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43644.96 # Average gap between requests +system.physmem.avgGap 43647.42 # Average gap between requests system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10769580 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.346375 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states +system.physmem_0.totalEnergy 14349765 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.276555 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 315250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15294250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.767883 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states +system.physmem_1.actBackEnergy 10147140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 598500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12757005 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.747987 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 956000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14370250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2336 # Number of BP lookups system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35555 # number of cpu cycles simulated +system.cpu.numCycles 35557 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6181 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11260 # Number of instructions fetch has processed system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 7643 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3826 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 175 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.207772 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8934 59.04% 59.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2459 16.25% 75.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.44% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3219 21.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5038 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065697 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.316675 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5932 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3662 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5040 # Number of cycles decode is running system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode +system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9865 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1623 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4094 # Number of cycles rename is running +system.cpu.rename.IdleCycles 7001 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 962 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1967 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4096 # Number of cycles rename is running system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename +system.cpu.rename.RenamedInsts 8887 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9238 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40311 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9765 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3744 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 1809 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8352 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3013 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7853 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.472345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.858310 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10931 72.23% 72.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1952 12.90% 85.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1600 10.57% 95.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 604 3.99% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 46 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,90 +466,90 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15133 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 412 28.91% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 465 32.63% 61.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 548 38.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4470 62.53% 62.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1081 15.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7146 # Type of FU issued -system.cpu.iq.rate 0.200984 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7148 # Type of FU issued +system.cpu.iq.rate 0.201029 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1425 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199356 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11395 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6553 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8545 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 782 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed @@ -561,9 +561,9 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 8405 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 1809 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall @@ -572,7 +572,7 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 6744 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed @@ -580,35 +580,35 @@ system.cpu.iew.exec_nop 14 # nu system.cpu.iew.exec_refs 2427 # number of memory reference insts executed system.cpu.iew.exec_branches 1272 # Number of branches executed system.cpu.iew.exec_stores 1023 # Number of stores executed -system.cpu.iew.exec_rate 0.189622 # Inst execution rate -system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6567 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2975 # num instructions producing a value -system.cpu.iew.wb_consumers 5372 # num instructions consuming a value +system.cpu.iew.exec_rate 0.189667 # Inst execution rate +system.cpu.iew.wb_sent 6611 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6569 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2977 # num instructions producing a value +system.cpu.iew.wb_consumers 5378 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back +system.cpu.iew.wb_rate 0.184746 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553552 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 14591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.368583 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.017117 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11942 81.84% 81.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1388 9.51% 91.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 601 4.12% 95.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 167 1.14% 98.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.53% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14591 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,32 +655,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22320 # The number of ROB reads -system.cpu.rob.rob_writes 16439 # The number of ROB writes -system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22343 # The number of ROB reads +system.cpu.rob.rob_writes 16451 # The number of ROB writes +system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20424 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6718 # number of integer regfile reads -system.cpu.int_regfile_writes 3745 # number of integer regfile writes +system.cpu.cpi 7.743249 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.743249 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6720 # number of integer regfile reads +system.cpu.int_regfile_writes 3747 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23959 # number of cc regfile reads +system.cpu.cc_regfile_reads 23965 # number of cc regfile reads system.cpu.cc_regfile_writes 2898 # number of cc regfile writes system.cpu.misc_regfile_reads 2607 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.271040 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.271040 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164592 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164592 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id @@ -709,16 +709,16 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9210000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9210000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 125500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16927500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16927500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16927500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16927500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -741,16 +741,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55149.700599 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55149.700599 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47283.519553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47283.519553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,14 +777,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5839000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5839000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8293500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8293500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8293500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8293500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -793,71 +793,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063471 system.cpu.dcache.demand_mshr_miss_rate::total 0.063471 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57245.098039 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57245.098039 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.212207 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3460 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.728814 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 136.212207 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.266039 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.266039 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7941 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits -system.cpu.icache.overall_hits::total 3459 # number of overall hits +system.cpu.icache.tags.tag_accesses 7943 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7943 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3460 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3460 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3460 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3460 # number of overall hits +system.cpu.icache.overall_hits::total 3460 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21574493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21574493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21574493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21574493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21574493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21574493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3824 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3824 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3824 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095188 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.095188 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.095188 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.095188 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.095188 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.095188 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59270.585165 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59270.585165 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59270.585165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59270.585165 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8439 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.820225 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -873,24 +873,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 296 system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18788993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18788993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18788993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18788993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18788993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18788993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077406 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.077406 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.077406 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63476.327703 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63476.327703 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -899,18 +899,18 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 192.769134 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.484820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.082970 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.201345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008452 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.002752 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011766 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -947,16 +947,16 @@ system.cpu.l2cache.overall_misses::cpu.data 113 # system.cpu.l2cache.overall_misses::total 386 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2320000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2320000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18323500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 18323500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18323500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7869000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 26192500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18323500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7869000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26192500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 296 # number of ReadCleanReq accesses(hits+misses) @@ -983,16 +983,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67119.047619 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67119.047619 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67856.217617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67856.217617 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1030,17 +1030,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16642000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16642000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16642000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16642000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25195926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1060,18 +1060,24 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61183.823529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61183.823529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62026.315789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58868.985981 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 21 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 21 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution @@ -1087,15 +1093,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 64 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 546 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.117216 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.321973 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.133700 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.340641 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 482 88.28% 88.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64 11.72% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 473 86.63% 86.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 73 13.37% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 546 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) @@ -1122,9 +1128,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 514944 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2135000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 85d747802..d4b2570c8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25816500 # Number of ticks simulated -final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25848500 # Number of ticks simulated +final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428411 # Simulator instruction rate (inst/s) -host_op_rate 499438 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2416370273 # Simulator tick rate (ticks/s) -host_mem_usage 308620 # Number of bytes of host memory used +host_inst_rate 341128 # Simulator instruction rate (inst/s) +host_op_rate 397821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1927554064 # Simulator tick rate (ticks/s) +host_mem_usage 312280 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51633 # number of cpu cycles simulated +system.cpu.numCycles 51697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4566 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1008 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id @@ -242,14 +242,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -270,14 +270,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,33 +384,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy @@ -547,6 +547,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution @@ -560,14 +566,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index d3878acf4..c52a652eb 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 22451000 # Number of ticks simulated final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41665 # Simulator instruction rate (inst/s) -host_op_rate 41658 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187549895 # Simulator tick rate (ticks/s) -host_mem_usage 287968 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 76638 # Simulator instruction rate (inst/s) +host_op_rate 76622 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 344943613 # Simulator tick rate (ticks/s) +host_mem_usage 294148 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -912,6 +912,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -926,15 +932,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 489 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 7140a68cc..d99d61508 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 30902500 # Number of ticks simulated final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339265 # Simulator instruction rate (inst/s) -host_op_rate 338999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1861147916 # Simulator tick rate (ticks/s) -host_mem_usage 289452 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 459853 # Simulator instruction rate (inst/s) +host_op_rate 459290 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2521006690 # Simulator tick rate (ticks/s) +host_mem_usage 291832 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -435,6 +435,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -449,15 +455,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 445 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 585054648..1b72b1558 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19922000 # Number of ticks simulated -final_tick 19922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19923000 # Number of ticks simulated +final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38523 # Simulator instruction rate (inst/s) -host_op_rate 38518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132470471 # Simulator tick rate (ticks/s) -host_mem_usage 286104 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 93968 # Simulator instruction rate (inst/s) +host_op_rate 93947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 323084408 # Simulator tick rate (ticks/s) +host_mem_usage 291680 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1101897400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 324465415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1426362815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1101897400 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1101897400 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1101897400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 324465415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1426362815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19782500 # Total gap between requests +system.physmem.totGap 19783500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # By system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 3750750 # Total ticks spent queuing -system.physmem.totMemAccLat 12075750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3746750 # Total ticks spent queuing +system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8447.64 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27197.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1426.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1426.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 11.14 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 359 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44555.18 # Average gap between requests +system.physmem.avgGap 44557.43 # Average gap between requests system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) @@ -245,7 +245,7 @@ system.physmem_1.actBackEnergy 7628310 # En system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ) system.physmem_1.averagePower 748.283278 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 6322250 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states @@ -279,7 +279,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 39845 # number of cpu cycles simulated +system.cpu.numCycles 39847 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss @@ -310,8 +310,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.059204 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.330983 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1924 # Number of cycles decode is running @@ -437,7 +437,7 @@ system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8840 # Type of FU issued -system.cpu.iq.rate 0.221860 # Inst issue rate +system.cpu.iq.rate 0.221849 # Inst issue rate system.cpu.iq.fu_busy_cnt 201 # FU busy when requested system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads @@ -481,13 +481,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3121 # number of memory reference insts executed system.cpu.iew.exec_branches 1355 # Number of branches executed system.cpu.iew.exec_stores 1414 # Number of stores executed -system.cpu.iew.exec_rate 0.212950 # Inst execution rate +system.cpu.iew.exec_rate 0.212939 # Inst execution rate system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8147 # cumulative count of insts written-back system.cpu.iew.wb_producers 4452 # num instructions producing a value system.cpu.iew.wb_consumers 7114 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.204467 # insts written-back per cycle +system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit @@ -559,24 +559,24 @@ system.cpu.commit.bw_lim_events 110 # nu system.cpu.rob.rob_reads 21420 # The number of ROB reads system.cpu.rob.rob_writes 21108 # The number of ROB writes system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27826 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.879316 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.879316 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145363 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145363 # IPC: Total IPC of All Threads +system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13451 # number of integer regfile reads system.cpu.int_regfile_writes 7138 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.587343 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.587343 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id @@ -601,14 +601,14 @@ system.cpu.dcache.demand_misses::cpu.data 433 # n system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses system.cpu.dcache.overall_misses::total 433 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7902500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7902500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31812496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31812496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31812496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31812496 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -625,14 +625,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.163643 system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73171.296296 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73171.296296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73469.967667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73469.967667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 103 system.cpu.dcache.demand_mshr_misses::total 103 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 103 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4528500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4530500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4530500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4006498 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4006498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8534998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8534998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8534998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8534998 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8536998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8536998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8536998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8536998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035000 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035000 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -673,22 +673,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038927 system.cpu.dcache.demand_mshr_miss_rate::total 0.038927 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038927 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80866.071429 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80866.071429 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80901.785714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80901.785714 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.966654 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.966455 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.966654 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 168.966455 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.082503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.082503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id @@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 433 # n system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses system.cpu.icache.overall_misses::total 433 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32237500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32237500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32237500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32237500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32237500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32237500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32239500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32239500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32239500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32239500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32239500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32239500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1822 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1822 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1822 # number of demand (read+write) accesses @@ -727,12 +727,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.237651 system.cpu.icache.demand_miss_rate::total 0.237651 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.237651 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.237651 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74451.501155 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74451.501155 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74451.501155 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74451.501155 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74456.120092 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74456.120092 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74456.120092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74456.120092 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -753,39 +753,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 350 system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26589500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26589500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26591500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26591500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26591500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26591500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26591500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26591500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192097 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.192097 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.192097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75970 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75970 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75975.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75975.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.677803 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.677769 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.020151 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770664 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.907139 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770776 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.906993 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005120 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000974 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006094 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4068 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4068 # Number of data accesses @@ -813,16 +813,16 @@ system.cpu.l2cache.overall_misses::cpu.data 101 # system.cpu.l2cache.overall_misses::total 445 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3932500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26002500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 26002500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25998500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25998500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 4422500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 26002500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25998500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 8355000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34357500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 26002500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 34353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25998500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 8355000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34357500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34353500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) @@ -849,16 +849,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583 system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75577.034884 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75577.034884 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77198.876404 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77198.876404 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -881,16 +881,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 101 system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22568500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22568500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22568500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29917500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29913500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22568500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29917500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29913500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses @@ -905,17 +905,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583 system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65606.104651 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65606.104651 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 453 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution @@ -929,14 +935,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.017660 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.131858 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 453 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 98.23% 98.23% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index fd8319ed7..a369fae45 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27800500 # Number of ticks simulated -final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27803500 # Number of ticks simulated +final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428112 # Simulator instruction rate (inst/s) -host_op_rate 427631 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2229390537 # Simulator tick rate (ticks/s) -host_mem_usage 290104 # Number of bytes of host memory used +host_inst_rate 506128 # Simulator instruction rate (inst/s) +host_op_rate 505504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2635153066 # Simulator tick rate (ticks/s) +host_mem_usage 292480 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 55601 # number of cpu cycles simulated +system.cpu.numCycles 55607 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles +system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id @@ -120,14 +120,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -144,14 +144,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -184,24 +184,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id @@ -220,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -238,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -258,33 +258,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy @@ -421,6 +421,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution @@ -434,14 +440,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index e476df038..b13c74560 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20817000 # Number of ticks simulated -final_tick 20817000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20818000 # Number of ticks simulated +final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31285 # Simulator instruction rate (inst/s) -host_op_rate 56673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 121026192 # Simulator tick rate (ticks/s) -host_mem_usage 306568 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 48919 # Simulator instruction rate (inst/s) +host_op_rate 88616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189245943 # Simulator tick rate (ticks/s) +host_mem_usage 313416 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17664 # Nu system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory system.physmem.num_reads::total 415 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 848537253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 427343037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1275880290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 848537253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 848537253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 848537253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 427343037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1275880290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 848496493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 427322509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1275819003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 848496493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 848496493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 848496493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 427322509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1275819003 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 415 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20721000 # Total gap between requests +system.physmem.totGap 20722000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2075000 # To system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1275.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 1275.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1275.88 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1275.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 9.97 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 309 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49930.12 # Average gap between requests +system.physmem.avgGap 49932.53 # Average gap between requests system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) @@ -262,7 +262,7 @@ system.cpu.branchPred.RASInCorrect 86 # Nu system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41635 # number of cpu cycles simulated +system.cpu.numCycles 41637 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss @@ -293,8 +293,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077675 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.351555 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.077671 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351538 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3206 # Number of cycles decode is running @@ -417,7 +417,7 @@ system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 17161 # Type of FU issued -system.cpu.iq.rate 0.412177 # Inst issue rate +system.cpu.iq.rate 0.412157 # Inst issue rate system.cpu.iq.fu_busy_cnt 212 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads @@ -461,13 +461,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3175 # number of memory reference insts executed system.cpu.iew.exec_branches 1626 # Number of branches executed system.cpu.iew.exec_stores 1262 # Number of stores executed -system.cpu.iew.exec_rate 0.390657 # Inst execution rate +system.cpu.iew.exec_rate 0.390638 # Inst execution rate system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit system.cpu.iew.wb_count 15771 # cumulative count of insts written-back system.cpu.iew.wb_producers 10637 # num instructions producing a value system.cpu.iew.wb_consumers 16589 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.378792 # insts written-back per cycle +system.cpu.iew.wb_rate 0.378774 # insts written-back per cycle system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit @@ -539,13 +539,13 @@ system.cpu.commit.bw_lim_events 255 # nu system.cpu.rob.rob_reads 41158 # The number of ROB reads system.cpu.rob.rob_writes 42744 # The number of ROB writes system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18910 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 18912 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.738848 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.738848 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129218 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129218 # IPC: Total IPC of All Threads +system.cpu.cpi 7.739219 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.739219 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129212 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129212 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 20871 # number of integer regfile reads system.cpu.int_regfile_writes 12651 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads @@ -554,12 +554,12 @@ system.cpu.cc_regfile_writes 4880 # nu system.cpu.misc_regfile_reads 7277 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.971685 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.973847 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.971685 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 81.973847 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id @@ -664,17 +664,17 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806 system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.298609 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 130.304167 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1706 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.158845 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.298609 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063622 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063622 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 130.304167 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063625 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063625 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 277 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses system.cpu.icache.tags.data_accesses 4427 # Number of data accesses @@ -690,12 +690,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28131500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28131500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28131500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28131500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28131500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28131500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28132500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28132500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28132500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28132500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28132500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28132500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2075 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2075 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2075 # number of demand (read+write) accesses @@ -708,12 +708,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.177831 system.cpu.icache.demand_miss_rate::total 0.177831 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.177831 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.177831 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76237.127371 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76237.127371 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76237.127371 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76237.127371 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76239.837398 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76239.837398 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76239.837398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76239.837398 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -734,33 +734,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 277 system.cpu.icache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 277 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22318000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22318000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22318000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22318000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22318000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22318000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22319000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22319000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22319000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22319000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22319000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22319000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133494 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.133494 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.133494 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80570.397112 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80570.397112 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80574.007220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80574.007220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 162.374270 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 162.380689 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.338432 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.035838 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.343988 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32.036700 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004955 # Average percentage of cache occupancy @@ -893,6 +893,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution @@ -906,14 +912,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002404 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.049029 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 416 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 415 99.76% 99.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index ef7ce3c79..a52dc699f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28358500 # Number of ticks simulated -final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 28359500 # Number of ticks simulated +final_tick 28359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304372 # Simulator instruction rate (inst/s) -host_op_rate 550952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1601632215 # Simulator tick rate (ticks/s) -host_mem_usage 308112 # Number of bytes of host memory used +host_inst_rate 279983 # Simulator instruction rate (inst/s) +host_op_rate 506758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1473373857 # Simulator tick rate (ticks/s) +host_mem_usage 311136 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 512279836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302403075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814682910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512279836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512279836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512279836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302403075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814682910 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56717 # number of cpu cycles simulated +system.cpu.numCycles 56719 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles +system.cpu.num_busy_cycles 56718.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -93,14 +93,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.791087 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.792611 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.791087 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019724 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019724 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.792611 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id @@ -197,14 +197,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.540319 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.543720 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.540319 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.543720 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id @@ -223,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12499500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12499500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12499500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12499500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12499500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12499500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -241,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54822.368421 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54822.368421 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54822.368421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54822.368421 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -261,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12270500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12270500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12270500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12270500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12270500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12270500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12271500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12271500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12271500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12271500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12271500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12271500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53817.982456 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53817.982456 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53822.368421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53822.368421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.006917 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 134.010901 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.536457 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.470460 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.539859 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.471042 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy @@ -420,6 +420,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution @@ -433,14 +439,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 3cf449dc8..9d107898a 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24832500 # Number of ticks simulated final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45282 # Simulator instruction rate (inst/s) -host_op_rate 45279 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88223588 # Simulator tick rate (ticks/s) -host_mem_usage 290360 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 79921 # Simulator instruction rate (inst/s) +host_op_rate 79915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155707227 # Simulator tick rate (ticks/s) +host_mem_usage 297588 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -298,59 +298,59 @@ system.cpu.numCycles 49666 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 1235 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 39559 # Number of instructions fetch has processed +system.cpu.fetch.Insts 39551 # Number of instructions fetch has processed system.cpu.fetch.Branches 6978 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2103 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10834 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 10833 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1446 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.CacheLines 5404 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 838 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 27534 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.436733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.801651 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.436442 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.801385 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20750 75.36% 75.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 584 2.12% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20751 75.37% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 584 2.12% 77.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 426 1.55% 79.03% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 584 2.12% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 571 2.07% 83.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 571 2.07% 83.23% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 441 1.60% 84.83% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 491 1.78% 86.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 560 2.03% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3127 11.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 560 2.03% 88.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3126 11.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 27534 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.140499 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.796501 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37298 # Number of cycles decode is idle +system.cpu.fetch.rate 0.796340 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37297 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 10659 # Number of cycles decode is blocked system.cpu.decode.RunCycles 5112 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 613 # Number of cycles decode is unblocking +system.cpu.decode.UnblockCycles 614 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1127 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 528 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 328 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 32201 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 32206 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 725 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1127 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37873 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 37872 # Number of cycles rename is idle system.cpu.rename.BlockCycles 4968 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1226 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5149 # Number of cycles rename is running +system.cpu.rename.RunCycles 5150 # Number of cycles rename is running system.cpu.rename.UnblockCycles 4466 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30276 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 30281 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 324 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 847 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 3132 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 22817 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37709 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37691 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 22821 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37713 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37695 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13677 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13681 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 60 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 2263 # count of insts added to the skid buffer @@ -847,12 +847,12 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.icache.tags.replacements::0 8 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 8 # number of replacements -system.cpu.icache.tags.tagsinuse 317.015033 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 317.014953 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4463 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 634 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 7.039432 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 317.015033 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 317.014953 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.154792 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.154792 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id @@ -873,12 +873,12 @@ system.cpu.icache.demand_misses::cpu.inst 935 # n system.cpu.icache.demand_misses::total 935 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 935 # number of overall misses system.cpu.icache.overall_misses::total 935 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 70145997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 70145997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 70145997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 70145997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 70145997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 70145997 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70147997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70147997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70147997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70147997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70147997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70147997 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5398 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5398 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5398 # number of demand (read+write) accesses @@ -891,12 +891,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.173212 system.cpu.icache.demand_miss_rate::total 0.173212 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.173212 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.173212 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75022.456684 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75022.456684 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75022.456684 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75022.456684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75022.456684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75022.456684 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75024.595722 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75024.595722 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75024.595722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75024.595722 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 3484 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 77 # number of cycles access was blocked @@ -917,24 +917,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 634 system.cpu.icache.demand_mshr_misses::total 634 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 634 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51559499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51559499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51559499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51559499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51559499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51559499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51561499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51561499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51561499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51561499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51561499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51561499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117451 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.117451 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.117451 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81324.130915 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81324.130915 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81324.130915 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 81324.130915 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81324.130915 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 81324.130915 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81327.285489 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81327.285489 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements @@ -1078,6 +1078,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 986 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution @@ -1092,14 +1098,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 62592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 986 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002028 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045015 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 986 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 984 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 986 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks) diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 82d581de7..dca96be88 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26943000 # Number of ticks simulated -final_tick 26943000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26944000 # Number of ticks simulated +final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30305 # Simulator instruction rate (inst/s) -host_op_rate 30304 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56555572 # Simulator tick rate (ticks/s) -host_mem_usage 288252 # Number of bytes of host memory used -host_seconds 0.48 # Real time elapsed on the host +host_inst_rate 95332 # Simulator instruction rate (inst/s) +host_op_rate 95323 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 177899852 # Simulator tick rate (ticks/s) +host_mem_usage 294468 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21888 # Nu system.physmem.num_reads::cpu.inst 342 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 489 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 812381695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 349181606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1161563300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812381695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812381695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812381695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 349181606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1161563300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 812351544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 349168646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1161520190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812351544 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812351544 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812351544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 349168646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1161520190 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 489 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 489 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26890000 # Total gap between requests +system.physmem.totGap 26891000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2445000 # To system.physmem.avgQLat 7529.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 26279.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1161.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 1161.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1161.56 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1161.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 9.07 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 409 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54989.78 # Average gap between requests +system.physmem.avgGap 54991.82 # Average gap between requests system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) @@ -245,7 +245,7 @@ system.physmem_1.actBackEnergy 15637950 # En system.physmem_1.preBackEnergy 453750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 19309500 # Total energy per rank (pJ) system.physmem_1.averagePower 817.549616 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2039000 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2040000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 22166500 # Time in different power states @@ -261,14 +261,14 @@ system.cpu.branchPred.usedRAS 554 # Nu system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 53887 # number of cpu cycles simulated +system.cpu.numCycles 53889 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13793 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 13792 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 37180 # Number of instructions fetch has processed system.cpu.fetch.Branches 8026 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 3719 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 15451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 15452 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps @@ -291,8 +291,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 31410 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.148941 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.689962 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.148936 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.689937 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 10981 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 12209 # Number of cycles decode is blocked system.cpu.decode.RunCycles 6549 # Number of cycles decode is running @@ -413,7 +413,7 @@ system.cpu.iq.FU_type_0::MemWrite 2088 10.02% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 20835 # Type of FU issued -system.cpu.iq.rate 0.386642 # Inst issue rate +system.cpu.iq.rate 0.386628 # Inst issue rate system.cpu.iq.fu_busy_cnt 177 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008495 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 73265 # Number of integer instruction queue reads @@ -457,13 +457,13 @@ system.cpu.iew.exec_nop 1117 # nu system.cpu.iew.exec_refs 5240 # number of memory reference insts executed system.cpu.iew.exec_branches 4296 # Number of branches executed system.cpu.iew.exec_stores 1999 # Number of stores executed -system.cpu.iew.exec_rate 0.371370 # Inst execution rate +system.cpu.iew.exec_rate 0.371356 # Inst execution rate system.cpu.iew.wb_sent 19648 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19408 # cumulative count of insts written-back system.cpu.iew.wb_producers 9326 # num instructions producing a value system.cpu.iew.wb_consumers 12017 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.360161 # insts written-back per cycle +system.cpu.iew.wb_rate 0.360148 # insts written-back per cycle system.cpu.iew.wb_fanout 0.776067 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 8625 # The number of squashed insts skipped by commit @@ -535,24 +535,24 @@ system.cpu.commit.bw_lim_events 290 # nu system.cpu.rob.rob_reads 52271 # The number of ROB reads system.cpu.rob.rob_writes 49405 # The number of ROB writes system.cpu.timesIdled 197 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 22477 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 22479 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.732821 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.732821 # CPI: Total CPI of All Threads -system.cpu.ipc 0.267894 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.267894 # IPC: Total IPC of All Threads +system.cpu.cpi 3.732959 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.732959 # CPI: Total CPI of All Threads +system.cpu.ipc 0.267884 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.267884 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 32029 # number of integer regfile reads system.cpu.int_regfile_writes 17799 # number of integer regfile writes system.cpu.misc_regfile_reads 6992 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.068517 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 98.069813 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4030 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.602740 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.068517 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 98.069813 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.023943 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.023943 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id @@ -663,14 +663,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78384.353741 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 190.286110 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 190.290590 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5576 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 344 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 16.209302 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 190.286110 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.092913 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.092913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 190.290590 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.092915 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.092915 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id @@ -689,12 +689,12 @@ system.cpu.icache.demand_misses::cpu.inst 519 # n system.cpu.icache.demand_misses::total 519 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 519 # number of overall misses system.cpu.icache.overall_misses::total 519 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 36198500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 36198500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 36198500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 36198500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 36198500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 36198500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 36200500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 36200500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 36200500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 36200500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 36200500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 36200500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6095 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6095 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6095 # number of demand (read+write) accesses @@ -707,12 +707,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.085152 system.cpu.icache.demand_miss_rate::total 0.085152 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.085152 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.085152 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69746.628131 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69746.628131 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69746.628131 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69746.628131 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69750.481696 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69750.481696 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69750.481696 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69750.481696 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -733,33 +733,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 344 system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26530000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26530000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26530000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26530000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26530000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26530000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26532000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26532000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26532000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26532000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26532000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26532000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.056440 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.056440 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.056440 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77122.093023 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77122.093023 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77127.906977 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77127.906977 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 223.995330 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 224.000415 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 405 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004938 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.659398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.335932 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.663901 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.336514 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005788 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001048 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006836 # Average percentage of cache occupancy @@ -892,6 +892,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66001.461988 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 491 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution @@ -905,14 +911,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 31360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004073 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.063757 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 491 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489 99.59% 99.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.41% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 625747903..b9f25890e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000041 # Number of seconds simulated -sim_ticks 41368500 # Number of ticks simulated -final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 41370500 # Number of ticks simulated +final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 372083 # Simulator instruction rate (inst/s) -host_op_rate 371955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1014555487 # Simulator tick rate (ticks/s) -host_mem_usage 290028 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 454115 # Simulator instruction rate (inst/s) +host_op_rate 453939 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1238118753 # Simulator tick rate (ticks/s) +host_mem_usage 292408 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 82737 # number of cpu cycles simulated +system.cpu.numCycles 82741 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles +system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.989824 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.989824 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id @@ -198,12 +198,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.774107 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.774107 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id @@ -224,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -242,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -262,33 +262,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15036500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15036500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15036500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15036500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15036500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15036500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.609803 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.092235 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517568 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy @@ -421,6 +421,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution @@ -434,14 +440,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 849193946..5eff3b495 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000062 # Number of seconds simulated -sim_ticks 61608000 # Number of ticks simulated -final_tick 61608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 61610000 # Number of ticks simulated +final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 214452 # Simulator instruction rate (inst/s) -host_op_rate 214360 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2049936831 # Simulator tick rate (ticks/s) -host_mem_usage 674692 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 402374 # Simulator instruction rate (inst/s) +host_op_rate 402048 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3843418590 # Simulator tick rate (ticks/s) +host_mem_usage 682268 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 6440 # Number of instructions simulated sim_ops 6440 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 288793663 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 174522789 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 463316452 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 288793663 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 288793663 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 288793663 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 174522789 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 463316452 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 446 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 61358000 # Total gap between requests +system.mem_ctrl.totGap 61360000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -205,9 +205,9 @@ system.mem_ctrl.totBusLat 2230000 # To system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 463.32 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 463.32 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage @@ -219,7 +219,7 @@ system.mem_ctrl.readRowHits 340 # Nu system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 137573.99 # Average gap between requests +system.mem_ctrl.avgGap 137578.48 # Average gap between requests system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) @@ -282,7 +282,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 61608 # number of cpu cycles simulated +system.cpu.numCycles 61610 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6440 # Number of instructions committed @@ -301,7 +301,7 @@ system.cpu.num_mem_refs 2063 # nu system.cpu.num_load_insts 1195 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61608 # Number of busy cycles +system.cpu.num_busy_cycles 61610 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1054 # Number of branches fetched @@ -341,14 +341,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6450 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.300595 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.300595 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.101856 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.101856 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id @@ -445,14 +445,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.923956 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.923956 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.445015 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.445015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id @@ -471,12 +471,12 @@ system.cpu.icache.demand_misses::cpu.inst 281 # n system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28179000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28179000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28179000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28179000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28179000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28179000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses @@ -489,12 +489,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043559 system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100281.138790 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100281.138790 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100281.138790 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100281.138790 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,25 +509,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281 system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27617000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27617000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27617000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27617000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27617000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27617000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98281.138790 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98281.138790 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 376 # Transaction distribution system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -541,14 +547,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 511 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.001957 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.044237 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 511 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 510 99.80% 99.80% # Request fanout histogram +system.l2bus.snoop_fanout::1 1 0.20% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 511 # Request fanout histogram system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) @@ -558,16 +564,16 @@ system.l2bus.respLayer0.utilization 1.4 # La system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 185.387550 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.677366 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 56.710184 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031415 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045261 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index dde0dd6ed..727647065 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79800 # Simulator instruction rate (inst/s) -host_op_rate 92294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 797317444 # Simulator tick rate (ticks/s) -host_mem_usage 690160 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 351391 # Simulator instruction rate (inst/s) +host_op_rate 406109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3506224066 # Simulator tick rate (ticks/s) +host_mem_usage 699088 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -199,12 +199,12 @@ system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # B system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2542000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 9123250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7242.17 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 25992.17 # Average memory access latency per DRAM burst +system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s @@ -226,28 +226,28 @@ system.mem_ctrl_0.preEnergy 189750 # En system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 31478535 # Energy for active background per rank (pJ) +system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ) system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37466355 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 797.538290 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 1053000 # Time in different power states +system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 44628000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 30270420 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1633500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 35988405 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 766.077484 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2556000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 42875250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -427,14 +427,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.307513 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.307513 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082332 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id @@ -461,14 +461,14 @@ system.cpu.dcache.demand_misses::cpu.data 142 # n system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8771000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8771000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4421000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4421000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13192000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13192000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -489,14 +489,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88595.959596 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 88595.959596 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102813.953488 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102813.953488 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92901.408451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92901.408451 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,14 +513,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4335000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4335000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12908000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12908000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses @@ -529,24 +529,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86595.959596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86595.959596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100813.953488 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100813.953488 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.491667 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.491667 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id @@ -565,12 +565,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23407000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23407000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23407000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23407000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23407000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23407000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses @@ -583,12 +583,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94004.016064 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 94004.016064 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 94004.016064 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 94004.016064 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,25 +603,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 249 system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22909000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22909000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22909000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22909000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22909000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22909000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92004.016064 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92004.016064 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -635,14 +641,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 461 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 461 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram +system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 461 # Request fanout histogram system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) @@ -652,16 +658,16 @@ system.l2bus.respLayer0.utilization 1.5 # La system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 156.235366 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.216430 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 49.018936 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026176 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.011968 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.038143 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id @@ -688,17 +694,17 @@ system.l2cache.demand_misses::total 351 # nu system.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.l2cache.overall_misses::cpu.data 126 # number of overall misses system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4206000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4206000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21658000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 7940000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 29598000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 21658000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 12146000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 33804000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 21658000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 12146000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 33804000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) @@ -721,17 +727,17 @@ system.l2cache.demand_miss_rate::total 0.897698 # mi system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97813.953488 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97813.953488 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96257.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95662.650602 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96097.402597 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96307.692308 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96307.692308 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,17 +757,17 @@ system.l2cache.demand_mshr_misses::total 351 # nu system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3346000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3346000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6280000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23438000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 9626000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 26784000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 9626000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 26784000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses @@ -773,17 +779,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.897698 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77813.953488 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77813.953488 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75662.650602 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76097.402597 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 00ce95d37..5eab4cd6f 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 807198 # Simulator instruction rate (inst/s) -host_op_rate 805914 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8425106508 # Simulator tick rate (ticks/s) -host_mem_usage 672980 # Number of bytes of host memory used +host_inst_rate 489554 # Simulator instruction rate (inst/s) +host_op_rate 489001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5114816745 # Simulator tick rate (ticks/s) +host_mem_usage 679136 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated @@ -514,6 +514,12 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 99919.191919 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 384 # Transaction distribution system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -527,15 +533,15 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 528 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 528 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 528 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram system.l2bus.snoop_fanout::total 528 # Request fanout histogram system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 279d13e98..82b97827e 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000053 # Number of seconds simulated -sim_ticks 53332000 # Number of ticks simulated -final_tick 53332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 53334000 # Number of ticks simulated +final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 257745 # Simulator instruction rate (inst/s) -host_op_rate 257613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2475242240 # Simulator tick rate (ticks/s) -host_mem_usage 673312 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 497623 # Simulator instruction rate (inst/s) +host_op_rate 497044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4772617450 # Simulator tick rate (ticks/s) +host_mem_usage 679800 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 16448 # Nu system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 308407710 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 164404110 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 472811820 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 308407710 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 308407710 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 308407710 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 164404110 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 472811820 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 394 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 53236000 # Total gap between requests +system.mem_ctrl.totGap 53238000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -204,15 +204,15 @@ system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # B system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3014250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10401750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7650.38 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26400.38 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 472.81 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 472.81 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage @@ -224,21 +224,21 @@ system.mem_ctrl.readRowHits 295 # Nu system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 135116.75 # Average gap between requests +system.mem_ctrl.avgGap 135121.83 # Average gap between requests system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ) system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 30542310 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1395000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37207005 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 792.017562 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 2172750 # Time in different power states +system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 43258500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ) @@ -255,7 +255,7 @@ system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 53332 # number of cpu cycles simulated +system.cpu.numCycles 53334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -274,7 +274,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 53331.999000 # Number of busy cycles +system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -314,12 +314,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.742557 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.742557 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id @@ -344,10 +344,10 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5532000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5532000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8433000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8433000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles @@ -368,10 +368,10 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98785.714286 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 98785.714286 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102841.463415 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102841.463415 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency @@ -392,10 +392,10 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles @@ -408,24 +408,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100841.463415 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100841.463415 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.062197 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.062197 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.383055 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.383055 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id @@ -444,12 +444,12 @@ system.cpu.icache.demand_misses::cpu.inst 259 # n system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26197000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26197000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26197000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26197000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26197000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26197000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses @@ -462,12 +462,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101146.718147 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101146.718147 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101146.718147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101146.718147 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,25 +482,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 259 system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25679000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25679000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25679000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25679000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99146.718147 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99146.718147 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 315 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution @@ -514,14 +520,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 468 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.008547 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.092153 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 464 99.15% 99.15% # Request fanout histogram +system.l2bus.snoop_fanout::1 4 0.85% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 468 # Request fanout histogram system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) @@ -531,13 +537,13 @@ system.l2bus.respLayer0.utilization 1.5 # La system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 143.999291 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 117.698664 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 26.300627 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy @@ -567,17 +573,17 @@ system.l2cache.demand_misses::total 394 # nu system.l2cache.overall_misses::cpu.inst 257 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8023000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8023000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24860000 # number of ReadSharedReq miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30091000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24860000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13254000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38114000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24860000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13254000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38114000 # number of overall miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) @@ -600,17 +606,17 @@ system.l2cache.demand_miss_rate::total 0.992443 # mi system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97841.463415 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97841.463415 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96731.517510 # average ReadSharedReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96445.512821 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96736.040609 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96736.040609 # average overall miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -630,17 +636,17 @@ system.l2cache.demand_mshr_misses::total 394 # nu system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6383000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6383000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23851000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10514000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 30234000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10514000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 30234000 # number of overall MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses @@ -652,17 +658,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.992443 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77841.463415 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77841.463415 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76731.517510 # average ReadSharedReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76445.512821 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index eeac393c4..29a5c5d19 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000056 # Nu sim_ticks 55844000 # Number of ticks simulated final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212931 # Simulator instruction rate (inst/s) -host_op_rate 384017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2076955895 # Simulator tick rate (ticks/s) -host_mem_usage 693340 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 284010 # Simulator instruction rate (inst/s) +host_op_rate 512497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2773065846 # Simulator tick rate (ticks/s) +host_mem_usage 698700 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # B system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3554250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10379250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9764.42 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28514.42 # Average memory access latency per DRAM burst +system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s @@ -313,14 +313,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.671962 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.671962 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079758 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079758 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id @@ -417,14 +417,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 91.240171 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.240171 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.356407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.356407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -500,6 +500,12 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. +system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -513,14 +519,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoop_fanout::samples 428 # Request fanout histogram -system.l2bus.snoop_fanout::mean 1 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::mean 0.002336 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0.048337 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::1 428 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 427 99.77% 99.77% # Request fanout histogram +system.l2bus.snoop_fanout::1 1 0.23% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 428 # Request fanout histogram system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) @@ -530,13 +536,13 @@ system.l2bus.respLayer0.utilization 1.3 # La system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 135.849297 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.899114 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 28.950183 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy @@ -565,15 +571,15 @@ system.l2cache.overall_misses::cpu.data 135 # nu system.l2cache.overall_misses::total 364 # number of overall misses system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22401000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 28127000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22401000 # number of demand (read+write) miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 35992000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22401000 # number of overall miss cycles +system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 35992000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) @@ -598,15 +604,15 @@ system.l2cache.overall_miss_rate::cpu.data 1 # system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97820.960699 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 98691.228070 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98879.120879 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98879.120879 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,15 +634,15 @@ system.l2cache.overall_mshr_misses::cpu.data 135 system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17821000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 22427000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17821000 # number of demand (read+write) MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 28712000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17821000 # number of overall MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 28712000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses @@ -650,15 +656,15 @@ system.l2cache.overall_mshr_miss_rate::cpu.data 1 system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77820.960699 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78691.228070 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index bc3ca9120..81d1f8ac8 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041221500 # Number of ticks simulated -final_tick 147041221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 147041346500 # Number of ticks simulated +final_tick 147041346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1077194 # Simulator instruction rate (inst/s) -host_op_rate 1082547 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1748701394 # Simulator tick rate (ticks/s) -host_mem_usage 444972 # Number of bytes of host memory used -host_seconds 84.09 # Real time elapsed on the host +host_inst_rate 870528 # Simulator instruction rate (inst/s) +host_op_rate 874854 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1413203999 # Simulator tick rate (ticks/s) +host_mem_usage 449664 # Number of bytes of host memory used +host_seconds 104.05 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -22,13 +22,13 @@ system.physmem.num_reads::cpu.inst 577 # Nu system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 251140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6425627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6425621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6676761 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 251140 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 251140 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 251140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6425627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6425621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6676761 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082443 # number of cpu cycles simulated +system.cpu.numCycles 294082693 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576862 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082442.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294082692.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 18732305 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593910 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.593612 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410415500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593910 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 54410450500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593612 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -248,14 +248,14 @@ system.cpu.dcache.demand_misses::cpu.data 946796 # n system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711406000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711406000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711511000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711511000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928589500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928589500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928589500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928589500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928694500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928694500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928694500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928694500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -280,14 +280,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.970151 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.970151 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13010.086793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13010.086793 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.095184 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13655.095184 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.051917 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13655.051917 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.206085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.206085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.162817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.162817 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811180000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10811285000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10811285000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1170574500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1170574500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 120000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 120000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981754500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11981754500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981874500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11981874500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981859500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11981859500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981979500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11981979500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12009.940168 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12009.940168 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12010.056810 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12010.056810 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25114.773971 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25114.773971 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 40000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 40000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.067359 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.067359 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.154003 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.154003 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12655.178259 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12655.178259 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12655.264903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12655.264903 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120565 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.120518 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120565 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120518 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id @@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32034000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32034000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32034000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32034000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32034000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32034000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32054000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32054000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32054000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32054000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32054000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32054000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses @@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53479.131886 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53479.131886 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53479.131886 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53479.131886 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53479.131886 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53512.520868 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53512.520868 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53512.520868 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53512.520868 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53512.520868 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,34 +412,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31435000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 31435000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31435000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 31435000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31435000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 31435000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31455000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31455000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52479.131886 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52479.131886 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52479.131886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52479.131886 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52512.520868 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52512.520868 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52512.520868 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52512.520868 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.852238 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9567.853327 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446176 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172976 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233086 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.447332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233064 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005928 # Average percentage of cache occupancy @@ -586,6 +586,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42520.797227 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42517.103570 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42517.242503 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 256 # Transaction distribution @@ -601,14 +607,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1890101 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000126 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011244 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1890101 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1889862 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 239 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1890101 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887384500 # Layer occupancy (ticks) diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index b23c645a0..053bb8ee0 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000107 # Number of seconds simulated -sim_ticks 107049000 # Number of ticks simulated -final_tick 107049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000108 # Number of seconds simulated +sim_ticks 107711000 # Number of ticks simulated +final_tick 107711000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93620 # Simulator instruction rate (inst/s) -host_op_rate 93620 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10161795 # Simulator tick rate (ticks/s) -host_mem_usage 304708 # Number of bytes of host memory used -host_seconds 10.53 # Real time elapsed on the host -sim_insts 986230 # Number of instructions simulated -sim_ops 986230 # Number of ops (including micro ops) simulated +host_inst_rate 152784 # Simulator instruction rate (inst/s) +host_op_rate 152784 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16568657 # Simulator tick rate (ticks/s) +host_mem_usage 311444 # Number of bytes of host memory used +host_seconds 6.50 # Real time elapsed on the host +sim_insts 993230 # Number of instructions simulated +sim_ops 993230 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5312 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42560 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 83 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 665 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 215228540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101037842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49024279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11957141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1793571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7772142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2989285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7772142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 397574942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 215228540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49024279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1793571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2989285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269035675 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 215228540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101037842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49024279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11957141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1793571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7772142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2989285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7772142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 397574942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213905729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100416856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49317154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11883652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2970913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7724374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1188365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7724374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 395131416 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213905729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49317154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2970913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1188365 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267382162 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213905729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100416856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49317154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11883652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2970913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7724374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1188365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7724374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 395131416 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 666 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue @@ -70,7 +70,7 @@ system.physmem.bytesReadSys 42624 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 87 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 30 # Per bank write bursts @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107021000 # Total gap between requests +system.physmem.totGap 107683000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -120,9 +120,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -216,446 +216,446 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 276.444444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.969078 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 251.786617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 36 25.00% 54.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 28 19.44% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 8.33% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 4.86% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 5.56% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.39% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 2.08% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation -system.physmem.totQLat 6009250 # Total ticks spent queuing -system.physmem.totMemAccLat 18496750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 274.537931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.244268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 251.506931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 44 30.34% 30.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 37 25.52% 55.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 19.31% 75.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 7.59% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 4.83% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 5.52% 93.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation +system.physmem.totQLat 6590000 # Total ticks spent queuing +system.physmem.totMemAccLat 19077500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9022.90 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9894.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27772.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 398.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28644.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 395.73 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 398.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 395.73 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.11 # Data bus utilization in percentage -system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.09 # Data bus utilization in percentage +system.physmem.busUtilRead 3.09 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 511 # Number of row buffer hits during reads +system.physmem.readRowHits 510 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.73 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 160692.19 # Average gap between requests -system.physmem.pageHitRate 76.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 161686.19 # Average gap between requests +system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 37638810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27872250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75978045 # Total energy per rank (pJ) -system.physmem_0.averagePower 748.690472 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47858250 # Time in different power states +system.physmem_0.actBackEnergy 38163780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27411750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76054200 # Total energy per rank (pJ) +system.physmem_0.averagePower 749.440907 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 47737250 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 51979250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 52758750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 32994450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 31946250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 74129175 # Total energy per rank (pJ) -system.physmem_1.averagePower 730.471639 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 55670750 # Time in different power states +system.physmem_1.actBackEnergy 32134320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32700750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 74023545 # Total energy per rank (pJ) +system.physmem_1.averagePower 729.430757 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57587750 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45162250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 43903750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81022 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78376 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 81565 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78921 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78355 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75640 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 78897 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 76181 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.535001 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 96.557537 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 214099 # number of cpu cycles simulated +system.cpu0.numCycles 215423 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19687 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 478911 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81022 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76285 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 164512 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.icacheStallCycles 19725 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 482162 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81565 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76826 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165719 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1992 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 617 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.IcacheSquashes 620 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 187540 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.553647 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.214546 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 188787 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.554000 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.213947 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30407 16.21% 16.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77695 41.43% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 798 0.43% 58.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1205 0.64% 58.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 612 0.33% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 73095 38.98% 98.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 670 0.36% 98.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 402 0.21% 98.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2656 1.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30573 16.19% 16.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78235 41.44% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 796 0.42% 58.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1203 0.64% 58.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 613 0.32% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73639 39.01% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2654 1.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 187540 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.378432 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.236867 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15435 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18383 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 151822 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 650 # Number of cycles decode is unblocking +system.cpu0.fetch.rateDist::total 188787 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.378627 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.238210 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15472 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18515 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152899 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 651 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 468409 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 471677 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16041 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2079 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14982 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 151818 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1370 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 465227 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 867 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 318145 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 927822 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 700792 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 305063 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13082 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4377 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148776 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75241 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72733 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72329 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 389183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.IdleCycles 16075 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2062 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15118 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152899 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1383 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 468509 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 320339 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 934389 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 705719 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 307267 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13072 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4372 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 149868 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75788 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 73280 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72874 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 391921 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 385745 # Number of instructions issued +system.cpu0.iq.iqInstsIssued 388505 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12312 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11729 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedInstsExamined 12295 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11684 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 187540 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.056868 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.126403 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 188787 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.057901 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.125475 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33477 17.85% 17.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4232 2.26% 20.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73531 39.21% 59.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73185 39.02% 98.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1601 0.85% 99.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 889 0.47% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 403 0.21% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33627 17.81% 17.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4227 2.24% 20.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 74093 39.25% 59.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73707 39.04% 98.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1618 0.86% 99.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 402 0.21% 99.88% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 75 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 187540 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 188787 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 61 21.11% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 125 43.25% 64.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 163127 42.29% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 148129 38.40% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74489 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164238 42.27% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 149226 38.41% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 75041 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 385745 # Type of FU issued -system.cpu0.iq.rate 1.801713 # Inst issue rate +system.cpu0.iq.FU_type_0::total 388505 # Type of FU issued +system.cpu0.iq.rate 1.803452 # Inst issue rate system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000749 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 959350 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 402446 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 383893 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 966117 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405167 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 386653 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 386034 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 388794 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71845 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 72393 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2655 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1670 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2043 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 463105 # Number of instructions dispatched to IQ +system.cpu0.iew.iewBlockCycles 2029 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 466388 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148776 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75241 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 149868 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75788 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 990 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1308 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 384734 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147791 # Number of load instructions executed +system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 387494 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 148888 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 73033 # number of nop insts executed -system.cpu0.iew.exec_refs 222131 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76355 # Number of branches executed -system.cpu0.iew.exec_stores 74340 # Number of stores executed -system.cpu0.iew.exec_rate 1.796991 # Inst execution rate -system.cpu0.iew.wb_sent 384301 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 383893 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 227714 # num instructions producing a value -system.cpu0.iew.wb_consumers 230757 # num instructions consuming a value +system.cpu0.iew.exec_nop 73578 # number of nop insts executed +system.cpu0.iew.exec_refs 223779 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76909 # Number of branches executed +system.cpu0.iew.exec_stores 74891 # Number of stores executed +system.cpu0.iew.exec_rate 1.798759 # Inst execution rate +system.cpu0.iew.wb_sent 387061 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 386653 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 229361 # num instructions producing a value +system.cpu0.iew.wb_consumers 232407 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.793063 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986813 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.794855 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986894 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13101 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13078 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 185078 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.431116 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.149204 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 186327 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.432562 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.148979 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33718 18.22% 18.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75423 40.75% 58.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1935 1.05% 60.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 662 0.36% 60.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 535 0.29% 60.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71534 38.65% 99.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 523 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33862 18.17% 18.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75972 40.77% 58.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1939 1.04% 59.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 672 0.36% 60.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 526 0.28% 60.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 72083 38.69% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 527 0.28% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 185078 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 449946 # Number of instructions committed -system.cpu0.commit.committedOps 449946 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186327 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453252 # Number of instructions committed +system.cpu0.commit.committedOps 453252 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219688 # Number of memory references committed -system.cpu0.commit.loads 146121 # Number of loads committed +system.cpu0.commit.refs 221341 # Number of memory references committed +system.cpu0.commit.loads 147223 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75454 # Number of branches committed +system.cpu0.commit.branches 76005 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 303394 # Number of committed integer instructions. +system.cpu0.commit.int_insts 305598 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72186 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 157988 35.11% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 146205 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73567 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72737 16.05% 16.05% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 159090 35.10% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 147307 32.50% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 74118 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 449946 # Class of committed instruction +system.cpu0.commit.op_class_0::total 453252 # Class of committed instruction system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 646481 # The number of ROB reads -system.cpu0.rob.rob_writes 928572 # The number of ROB writes +system.cpu0.rob.rob_reads 651013 # The number of ROB reads +system.cpu0.rob.rob_writes 935136 # The number of ROB writes system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26559 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 377676 # Number of Instructions Simulated -system.cpu0.committedOps 377676 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.566885 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.566885 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.764025 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.764025 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 688304 # number of integer regfile reads -system.cpu0.int_regfile_writes 310378 # number of integer regfile writes +system.cpu0.idleCycles 26636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 380431 # Number of Instructions Simulated +system.cpu0.committedOps 380431 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.566260 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.566260 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.765972 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.765972 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 693268 # number of integer regfile reads +system.cpu0.int_regfile_writes 312587 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 223999 # number of misc regfile reads +system.cpu0.misc_regfile_reads 225648 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.054653 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148243 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.123038 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149358 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 866.918129 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 873.438596 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.054653 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275497 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275497 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.123038 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275631 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275631 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 598124 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 598124 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75326 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75326 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72968 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72968 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 602523 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 602523 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75889 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75889 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73521 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73521 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148294 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148294 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148294 # number of overall hits -system.cpu0.dcache.overall_hits::total 148294 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 561 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 561 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 149410 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149410 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 149410 # number of overall hits +system.cpu0.dcache.overall_hits::total 149410 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 547 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 547 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1118 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1118 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1118 # number of overall misses -system.cpu0.dcache.overall_misses::total 1118 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17156000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17156000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33757980 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 33757980 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1102 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1102 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1102 # number of overall misses +system.cpu0.dcache.overall_misses::total 1102 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16913500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16913500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34798980 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 34798980 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 50913980 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 50913980 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 50913980 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 50913980 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73525 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73525 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 51712480 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 51712480 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 51712480 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 51712480 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 76436 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 76436 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74076 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74076 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149412 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149412 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 149412 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 149412 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007393 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007576 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007576 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 150512 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 150512 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150512 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150512 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007156 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007156 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007492 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007492 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007483 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007483 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007483 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007483 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30581.105169 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30581.105169 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60606.786355 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 60606.786355 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007322 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007322 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007322 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007322 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30920.475320 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30920.475320 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62700.864865 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 62700.864865 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 45540.232558 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 45540.232558 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46926.025408 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46926.025408 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -666,68 +666,68 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 380 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 380 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 758 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 758 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 758 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 758 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 365 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 377 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 377 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 742 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 742 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 742 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 742 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6883000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6883000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8240500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8240500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6860000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8493000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8493000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15123500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15123500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15123500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15123500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002411 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002411 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002407 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002407 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15353000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15353000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15353000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15353000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002381 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002381 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002403 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002403 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002409 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002409 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002409 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37612.021858 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37612.021858 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46556.497175 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46556.497175 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37692.307692 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37692.307692 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47713.483146 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47713.483146 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42009.722222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42009.722222 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 315 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.042514 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 241.163907 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.042514 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470786 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.470786 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.163907 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471023 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471023 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses @@ -743,12 +743,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 784 # system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses system.cpu0.icache.overall_misses::total 784 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40365000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40365000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40365000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40365000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40365000 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40406000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40406000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40406000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40406000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40406000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40406000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses @@ -761,12 +761,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51485.969388 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 51485.969388 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 51485.969388 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51485.969388 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 51485.969388 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51538.265306 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51538.265306 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51538.265306 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51538.265306 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -787,399 +787,399 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31177000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31177000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31177000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31177000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31177000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31177000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31294000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31294000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31294000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31294000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31294000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31294000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51277.960526 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51470.394737 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 50039 # Number of BP lookups -system.cpu1.branchPred.condPredicted 46665 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 42823 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 41749 # Number of BTB hits +system.cpu1.branchPred.lookups 53924 # Number of BP lookups +system.cpu1.branchPred.condPredicted 50532 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 46687 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 45618 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.492002 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 914 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.710283 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 909 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 161348 # number of cpu cycles simulated +system.cpu1.numCycles 162664 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 31303 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 275372 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 50039 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 42663 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 121719 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 29507 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 300555 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 53924 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46527 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 124688 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2705 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 21928 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 155480 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.771109 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.178899 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 20020 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156656 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.918567 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.216659 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 58088 37.36% 37.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 49421 31.79% 69.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6835 4.40% 73.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3518 2.26% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 944 0.61% 76.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 30727 19.76% 96.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1228 0.79% 96.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 804 0.52% 97.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3915 2.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 52489 33.51% 33.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52328 33.40% 66.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5864 3.74% 70.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3542 2.26% 72.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 937 0.60% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 35524 22.68% 96.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1237 0.79% 96.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 797 0.51% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3938 2.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 155480 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.310131 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.706696 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17833 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 58352 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 74506 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3430 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1349 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 260078 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1349 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18539 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 27109 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13862 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 76429 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 18182 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 256857 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 16651 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 156656 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.331505 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.847704 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17844 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50371 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 84089 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 2990 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1352 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 285365 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1352 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18555 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22336 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13775 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 85993 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 14635 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 282118 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 13530 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 180872 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 489824 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 382391 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 167019 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13853 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 22657 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 71171 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 33454 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 33920 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 28372 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 213121 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6586 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 214969 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13076 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 730 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 155480 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.382615 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.383057 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 199297 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 544091 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 423098 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 185456 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13841 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1187 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 19159 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 79883 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38287 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 37783 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 33197 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 235383 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5651 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 236419 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12945 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10680 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 703 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156656 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.509160 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.379040 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 61906 39.82% 39.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21977 14.13% 53.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 32894 21.16% 75.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 32429 20.86% 95.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3365 2.16% 98.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1605 1.03% 99.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 896 0.58% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 208 0.13% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 56139 35.84% 35.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 19247 12.29% 48.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 37725 24.08% 72.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 37266 23.79% 95.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3381 2.16% 98.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1595 1.02% 99.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 897 0.57% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 205 0.13% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 155480 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156656 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 79 23.72% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 45 13.51% 37.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 79 23.65% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 46 13.77% 37.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 106597 49.59% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 75532 35.14% 84.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 32840 15.28% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 115374 48.80% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 83373 35.26% 84.07% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37672 15.93% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 214969 # Type of FU issued -system.cpu1.iq.rate 1.332331 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 333 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001549 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 585768 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 232822 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 213429 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 236419 # Type of FU issued +system.cpu1.iq.rate 1.453419 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 334 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001413 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 629842 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 254017 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 234890 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 215302 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 236753 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 28182 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 33006 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2599 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1503 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7989 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 254448 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 71171 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 33454 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1352 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6792 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 279653 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 149 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 79883 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38287 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1135 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1051 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 213962 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 70077 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1007 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 444 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1061 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 235416 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 78826 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1003 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 34741 # number of nop insts executed -system.cpu1.iew.exec_refs 102825 # number of memory reference insts executed -system.cpu1.iew.exec_branches 44094 # Number of branches executed -system.cpu1.iew.exec_stores 32748 # Number of stores executed -system.cpu1.iew.exec_rate 1.326090 # Inst execution rate -system.cpu1.iew.wb_sent 213711 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 213429 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 120431 # num instructions producing a value -system.cpu1.iew.wb_consumers 127039 # num instructions consuming a value +system.cpu1.iew.exec_nop 38619 # number of nop insts executed +system.cpu1.iew.exec_refs 116410 # number of memory reference insts executed +system.cpu1.iew.exec_branches 48027 # Number of branches executed +system.cpu1.iew.exec_stores 37584 # Number of stores executed +system.cpu1.iew.exec_rate 1.447253 # Inst execution rate +system.cpu1.iew.wb_sent 235168 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 234890 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 134020 # num instructions producing a value +system.cpu1.iew.wb_consumers 140635 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.322787 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.947984 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.444020 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.952963 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13922 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5856 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 152910 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.572631 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.035068 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13740 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4948 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 154106 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.725163 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.084593 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 67472 44.13% 44.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 40678 26.60% 70.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5251 3.43% 74.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6680 4.37% 78.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1520 0.99% 79.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 28236 18.47% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 823 0.54% 98.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 947 0.62% 99.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1303 0.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60830 39.47% 39.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 44602 28.94% 68.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5225 3.39% 71.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5769 3.74% 75.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1531 0.99% 76.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 33080 21.47% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 818 0.53% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 941 0.61% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1310 0.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 152910 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 240471 # Number of instructions committed -system.cpu1.commit.committedOps 240471 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 154106 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 265858 # Number of instructions committed +system.cpu1.commit.committedOps 265858 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 100469 # Number of memory references committed -system.cpu1.commit.loads 68518 # Number of loads committed -system.cpu1.commit.membars 5139 # Number of memory barriers committed -system.cpu1.commit.branches 43053 # Number of branches committed +system.cpu1.commit.refs 114070 # Number of memory references committed +system.cpu1.commit.loads 77284 # Number of loads committed +system.cpu1.commit.membars 4232 # Number of memory barriers committed +system.cpu1.commit.branches 46981 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 165641 # Number of committed integer instructions. +system.cpu1.commit.int_insts 183171 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 33840 14.07% 14.07% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 101023 42.01% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.08% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 73657 30.63% 86.71% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 31951 13.29% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 37769 14.21% 14.21% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 109787 41.30% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.50% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 81516 30.66% 86.16% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 36786 13.84% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 240471 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1303 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 405414 # The number of ROB reads -system.cpu1.rob.rob_writes 511356 # The number of ROB writes -system.cpu1.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.commit.op_class_0::total 265858 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1310 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 431808 # The number of ROB reads +system.cpu1.rob.rob_writes 561746 # The number of ROB writes +system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6008 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 201492 # Number of Instructions Simulated -system.cpu1.committedOps 201492 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.800766 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.800766 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.248804 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.248804 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 368266 # number of integer regfile reads -system.cpu1.int_regfile_writes 172947 # number of integer regfile writes +system.cpu1.committedInsts 223857 # Number of Instructions Simulated +system.cpu1.committedOps 223857 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.726642 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.726642 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.376193 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.376193 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 409049 # number of integer regfile reads +system.cpu1.int_regfile_writes 191377 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 104453 # number of misc regfile reads +system.cpu1.misc_regfile_reads 118040 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.714463 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 38066 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.752806 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 42910 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1312.620690 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1479.655172 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.714463 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050224 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050224 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.752806 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050298 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050298 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 295559 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 295559 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41369 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41369 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 31720 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 31720 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 330593 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 330593 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 45309 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 45309 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 36557 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 36557 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 73089 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 73089 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 73089 # number of overall hits -system.cpu1.dcache.overall_hits::total 73089 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 504 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 504 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 664 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 664 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 664 # number of overall misses -system.cpu1.dcache.overall_misses::total 664 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9769000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9769000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3369500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3369500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 693500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 693500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13138500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13138500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13138500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13138500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41873 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41873 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 31880 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 31880 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 73753 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 73753 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 73753 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 73753 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012036 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.012036 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005019 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.005019 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.788732 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.009003 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.009003 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.009003 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.009003 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19382.936508 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19382.936508 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21059.375000 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21059.375000 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12383.928571 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 12383.928571 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19786.897590 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19786.897590 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19786.897590 # average overall miss latency +system.cpu1.dcache.demand_hits::cpu1.data 81866 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 81866 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 81866 # number of overall hits +system.cpu1.dcache.overall_hits::total 81866 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 489 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 489 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 159 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 159 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 648 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 648 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 648 # number of overall misses +system.cpu1.dcache.overall_misses::total 648 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9556000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9556000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3376000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3376000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 667000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 667000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12932000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12932000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12932000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12932000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 45798 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 45798 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 36716 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 36716 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 82514 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 82514 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 82514 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 82514 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010677 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010677 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004331 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004331 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007853 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007853 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007853 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007853 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19541.922290 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19541.922290 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21232.704403 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21232.704403 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12127.272727 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 12127.272727 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19956.790123 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19956.790123 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1188,106 +1188,106 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 325 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 385 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 385 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 385 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 385 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2195000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2195000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1746000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1746000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 637500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 637500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3941000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3941000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3941000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3941000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004108 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004108 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003356 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003356 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.788732 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.788732 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003783 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003783 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003783 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12761.627907 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12761.627907 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16317.757009 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16317.757009 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11383.928571 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11383.928571 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14125.448029 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14125.448029 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_hits::cpu1.data 378 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 378 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2051500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2051500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1754500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1754500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 612000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 612000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3806000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3806000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3806000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3806000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002887 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12509.146341 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12509.146341 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16551.886792 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16551.886792 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11127.272727 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11127.272727 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 383 # number of replacements -system.cpu1.icache.tags.tagsinuse 84.275379 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21349 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 84.461587 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19439 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 43.042339 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.191532 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.275379 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164600 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.164600 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.461587 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164964 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.164964 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22424 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22424 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21349 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21349 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21349 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21349 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21349 # number of overall hits -system.cpu1.icache.overall_hits::total 21349 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 579 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 579 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 579 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 579 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 579 # number of overall misses -system.cpu1.icache.overall_misses::total 579 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13955500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 13955500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 13955500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 13955500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 13955500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 13955500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21928 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21928 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21928 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21928 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21928 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21928 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026405 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.026405 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026405 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.026405 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026405 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.026405 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24102.763385 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24102.763385 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24102.763385 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24102.763385 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 20516 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 20516 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 19439 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19439 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19439 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19439 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19439 # number of overall hits +system.cpu1.icache.overall_hits::total 19439 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 581 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 581 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 581 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 581 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 581 # number of overall misses +system.cpu1.icache.overall_misses::total 581 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14331000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14331000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14331000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14331000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14331000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14331000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20020 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20020 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20020 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20020 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20020 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20020 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029021 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029021 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029021 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029021 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029021 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029021 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24666.092943 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24666.092943 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24666.092943 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24666.092943 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1296,409 +1296,409 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 83 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 83 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 83 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 83 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11502500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11502500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11502500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11502500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11502500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11502500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022619 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022619 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022619 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23190.524194 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11831000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11831000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11831000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11831000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11831000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11831000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024775 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024775 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024775 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23852.822581 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 42880 # Number of BP lookups -system.cpu2.branchPred.condPredicted 39445 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1259 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 35521 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 34492 # Number of BTB hits +system.cpu2.branchPred.lookups 55489 # Number of BP lookups +system.cpu2.branchPred.condPredicted 52130 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1272 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 48168 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 47221 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.103122 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.033964 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 905 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 160976 # number of cpu cycles simulated +system.cpu2.numCycles 162291 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 36449 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 226588 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 42880 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 35396 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 120624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 28975 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 310103 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 55489 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 48126 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 128617 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2701 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1157 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 27680 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 159581 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.419893 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.036694 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 20027 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 160121 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.936679 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.215928 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 73772 46.23% 46.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 45044 28.23% 74.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 9695 6.08% 80.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3476 2.18% 82.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 968 0.61% 83.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 20661 12.95% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1186 0.74% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 799 0.50% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3980 2.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 52703 32.91% 32.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 53972 33.71% 66.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5883 3.67% 70.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3530 2.20% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 955 0.60% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 37143 23.20% 96.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1222 0.76% 97.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 796 0.50% 97.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3917 2.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 159581 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.266375 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.407589 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17760 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 80804 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 54882 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4787 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1338 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 211151 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1338 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18439 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 40468 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13548 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 56825 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 28953 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 208031 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 26065 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full -system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 143630 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 381000 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 300757 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 129882 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13748 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1262 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 33404 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 53977 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 23458 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 26723 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 18373 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 168634 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 9408 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 173236 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 12983 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10808 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 159581 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.085568 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.335871 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 160121 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.341911 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.910784 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17197 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 51483 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 87022 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3059 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1350 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 295507 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1350 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 17911 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 22825 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13935 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 88104 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 15986 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 292291 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 14001 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 205997 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 564188 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 438175 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 191932 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 14065 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1173 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 20395 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 83226 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 39943 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 39492 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34851 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 243755 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 5682 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 244785 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13094 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10962 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 160121 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.528750 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.374157 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 77748 48.72% 48.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 30232 18.94% 67.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 22868 14.33% 81.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 22470 14.08% 96.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3364 2.11% 98.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1606 1.01% 99.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 879 0.55% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 214 0.13% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 56124 35.05% 35.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 19550 12.21% 47.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39272 24.53% 71.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38854 24.27% 96.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3402 2.12% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1615 1.01% 99.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 887 0.55% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 205 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 159581 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 160121 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 79 23.94% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.94% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 42 12.73% 36.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 89318 51.56% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.56% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 61054 35.24% 86.80% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 22864 13.20% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 118682 48.48% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.48% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 86809 35.46% 83.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 39294 16.05% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 173236 # Type of FU issued -system.cpu2.iq.rate 1.076160 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 330 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001905 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 506398 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 191064 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 171727 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 244785 # Type of FU issued +system.cpu2.iq.rate 1.508309 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 650053 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 262570 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 243225 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 173566 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 245128 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 18193 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 34614 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedStores 1565 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10563 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 81 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 205567 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 53977 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 23458 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1137 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1350 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 6752 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 289758 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 83226 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 39943 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1125 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1053 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1483 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 172231 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 52840 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1005 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1057 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 243760 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 82166 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1025 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 27525 # number of nop insts executed -system.cpu2.iew.exec_refs 75615 # number of memory reference insts executed -system.cpu2.iew.exec_branches 36863 # Number of branches executed -system.cpu2.iew.exec_stores 22775 # Number of stores executed -system.cpu2.iew.exec_rate 1.069917 # Inst execution rate -system.cpu2.iew.wb_sent 171997 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 171727 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 93200 # num instructions producing a value -system.cpu2.iew.wb_consumers 99800 # num instructions consuming a value +system.cpu2.iew.exec_nop 40321 # number of nop insts executed +system.cpu2.iew.exec_refs 121366 # number of memory reference insts executed +system.cpu2.iew.exec_branches 49723 # Number of branches executed +system.cpu2.iew.exec_stores 39200 # Number of stores executed +system.cpu2.iew.exec_rate 1.501993 # Inst execution rate +system.cpu2.iew.wb_sent 243514 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 243225 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 138958 # num instructions producing a value +system.cpu2.iew.wb_consumers 145563 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.066786 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.933868 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.498697 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.954624 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 13823 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 8627 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1259 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 157016 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.220837 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.865055 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 13911 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5038 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1272 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 157537 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.750713 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.089801 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 86039 54.80% 54.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 33434 21.29% 76.09% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5238 3.34% 79.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 9429 6.01% 85.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1533 0.98% 86.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 18255 11.63% 98.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 831 0.53% 98.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1302 0.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 60893 38.65% 38.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46269 29.37% 68.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5250 3.33% 71.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5861 3.72% 75.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1535 0.97% 76.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34623 21.98% 98.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 855 0.54% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 943 0.60% 99.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1308 0.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 157016 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 191691 # Number of instructions committed -system.cpu2.commit.committedOps 191691 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 157537 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 275802 # Number of instructions committed +system.cpu2.commit.committedOps 275802 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 73311 # Number of memory references committed -system.cpu2.commit.loads 51335 # Number of loads committed -system.cpu2.commit.membars 7910 # Number of memory barriers committed -system.cpu2.commit.branches 35845 # Number of branches committed +system.cpu2.commit.refs 118948 # Number of memory references committed +system.cpu2.commit.loads 80570 # Number of loads committed +system.cpu2.commit.membars 4324 # Number of memory barriers committed +system.cpu2.commit.branches 48669 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 131277 # Number of committed integer instructions. +system.cpu2.commit.int_insts 189737 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 26632 13.89% 13.89% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 83838 43.74% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 59245 30.91% 88.54% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 21976 11.46% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 39459 14.31% 14.31% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 113071 41.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.30% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 84894 30.78% 86.08% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 38378 13.92% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 191691 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1302 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 360642 # The number of ROB reads -system.cpu2.rob.rob_writes 413593 # The number of ROB writes -system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1395 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.commit.op_class_0::total 275802 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1308 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 445356 # The number of ROB reads +system.cpu2.rob.rob_writes 582010 # The number of ROB writes +system.cpu2.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 2170 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 157149 # Number of Instructions Simulated -system.cpu2.committedOps 157149 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.024353 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.024353 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.976226 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.976226 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 286558 # number of integer regfile reads -system.cpu2.int_regfile_writes 135654 # number of integer regfile writes +system.cpu2.committedInsts 232019 # Number of Instructions Simulated +system.cpu2.committedOps 232019 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.699473 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.699473 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.429648 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.429648 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 423842 # number of integer regfile reads +system.cpu2.int_regfile_writes 197927 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 77226 # number of misc regfile reads +system.cpu2.misc_regfile_reads 122993 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 23.071332 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 27978 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 24.276146 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 44407 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 999.214286 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1585.964286 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.071332 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045061 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.045061 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.276146 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047414 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.047414 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 226658 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 226658 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 34141 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 34141 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 21749 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 21749 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 55890 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 55890 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 55890 # number of overall hits -system.cpu2.dcache.overall_hits::total 55890 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 483 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 483 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 156 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 156 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 639 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 639 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 639 # number of overall misses -system.cpu2.dcache.overall_misses::total 639 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7783500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7783500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3187000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3187000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 671500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 671500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 10970500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 10970500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 10970500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 10970500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 34624 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 34624 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 21905 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 21905 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 56529 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 56529 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 56529 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 56529 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.013950 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.013950 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007122 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007122 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.732394 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.011304 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.011304 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.011304 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.011304 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16114.906832 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16114.906832 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20429.487179 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20429.487179 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12913.461538 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 12913.461538 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17168.231612 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17168.231612 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17168.231612 # average overall miss latency +system.cpu2.dcache.tags.tag_accesses 343879 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 343879 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 47002 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 47002 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 38151 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 38151 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 85153 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 85153 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 85153 # number of overall hits +system.cpu2.dcache.overall_hits::total 85153 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 527 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 527 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 686 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 686 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 686 # number of overall misses +system.cpu2.dcache.overall_misses::total 686 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9963000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 9963000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 4178000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 4178000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 670500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 670500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 14141000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 14141000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 14141000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 14141000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 47529 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 47529 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 38310 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 38310 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 85839 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 85839 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 85839 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 85839 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.011088 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.011088 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004150 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004150 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007992 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007992 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007992 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007992 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18905.123340 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 18905.123340 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 26276.729560 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 26276.729560 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11973.214286 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 11973.214286 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 20613.702624 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 20613.702624 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1707,517 +1707,517 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 364 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 364 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 172 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 275 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 275 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1811500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1811500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1702500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1702500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 619500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 619500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3514000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3514000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3514000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3514000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004968 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004968 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004702 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004702 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.732394 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004865 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004865 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004865 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10531.976744 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10531.976744 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16529.126214 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16529.126214 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11913.461538 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11913.461538 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12778.181818 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12778.181818 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 367 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 51 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 418 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 418 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 418 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 418 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1620500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1620500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2159500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2159500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 614500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 614500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3780000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3780000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3780000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3780000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003366 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003366 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002819 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002819 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003122 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003122 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10128.125000 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10128.125000 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19995.370370 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19995.370370 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10973.214286 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10973.214286 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 386 # number of replacements -system.cpu2.icache.tags.tagsinuse 77.667456 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 27109 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 80.953803 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19454 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 54.218000 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 38.908000 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.667456 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151694 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.151694 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 80.953803 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.158113 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.158113 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 28180 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 28180 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 27109 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 27109 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 27109 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 27109 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 27109 # number of overall hits -system.cpu2.icache.overall_hits::total 27109 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 571 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 571 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 571 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 571 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 571 # number of overall misses -system.cpu2.icache.overall_misses::total 571 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7541500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7541500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7541500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7541500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7541500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7541500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 27680 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 27680 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 27680 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 27680 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 27680 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 27680 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020629 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.020629 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020629 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.020629 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020629 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.020629 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13207.530648 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13207.530648 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13207.530648 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13207.530648 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked +system.cpu2.icache.tags.tag_accesses 20527 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 20527 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 19454 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19454 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19454 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19454 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19454 # number of overall hits +system.cpu2.icache.overall_hits::total 19454 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses +system.cpu2.icache.overall_misses::total 573 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8014500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8014500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8014500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8014500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8014500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8014500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 20027 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 20027 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 20027 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 20027 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 20027 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 20027 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028611 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.028611 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028611 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.028611 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028611 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.028611 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13986.910995 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13986.910995 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13986.910995 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13986.910995 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 71 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 71 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 71 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6543500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6543500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6543500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6543500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6543500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6543500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.018064 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.018064 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.018064 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13087 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13087 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6952000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6952000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6952000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6952000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6952000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6952000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024966 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.024966 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.024966 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13904 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13904 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 58611 # Number of BP lookups -system.cpu3.branchPred.condPredicted 55067 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 51125 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 50131 # Number of BTB hits +system.cpu3.branchPred.lookups 42820 # Number of BP lookups +system.cpu3.branchPred.condPredicted 39316 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1255 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 35479 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 34386 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.055746 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 96.919304 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 900 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 160611 # number of cpu cycles simulated +system.cpu3.numCycles 161928 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 27021 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 330369 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 58611 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 51037 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 129883 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2715 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 36909 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 226016 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 42820 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 35286 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 121156 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2665 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 18269 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 159439 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 2.072071 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.246890 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 27941 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 160564 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.407638 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.031731 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 47077 29.53% 29.53% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 55913 35.07% 64.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 4932 3.09% 67.69% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3522 2.21% 69.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 934 0.59% 70.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 40952 25.69% 96.17% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1272 0.80% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 798 0.50% 97.47% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 4039 2.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 74840 46.61% 46.61% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 45030 28.04% 74.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 9823 6.12% 80.77% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3413 2.13% 82.90% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 964 0.60% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 20524 12.78% 96.28% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1162 0.72% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 811 0.51% 97.51% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3997 2.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 159439 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.364925 # Number of branch fetches per cycle -system.cpu3.fetch.rate 2.056951 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 16993 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 43740 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 94729 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 2610 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1357 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 315004 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1357 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 17735 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 17944 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 14128 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 95562 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 12703 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 311495 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 10931 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full -system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 220426 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 606441 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 469854 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 206787 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 13639 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1207 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 17457 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 89942 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 43802 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 42282 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 38692 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 261084 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 4750 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 261694 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12498 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 9712 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 614 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 159439 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.641342 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.359128 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 160564 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.264439 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.395781 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17966 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 81801 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 54656 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4799 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1332 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 210555 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1332 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18639 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 40771 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13962 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 56374 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 29476 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 207391 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 26344 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full +system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 143048 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 379530 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 299622 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 129648 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 13400 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1181 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1248 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 33973 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 53782 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 23352 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 26620 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 18276 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 168080 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9470 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 172966 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 9 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12631 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 757 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 160564 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.077240 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.332251 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 50249 31.52% 31.52% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 16842 10.56% 42.08% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 43259 27.13% 69.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 42799 26.84% 96.05% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3393 2.13% 98.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1616 1.01% 99.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 876 0.55% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 194 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 78662 48.99% 48.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 30467 18.97% 67.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 22821 14.21% 82.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 22372 13.93% 96.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3353 2.09% 98.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1614 1.01% 99.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 863 0.54% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 215 0.13% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 159439 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 160564 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 81 26.21% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.21% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 19 6.15% 32.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 67.64% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 82 24.55% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.55% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 43 12.87% 37.43% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 125700 48.03% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 92778 35.45% 83.49% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 43216 16.51% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 89169 51.55% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.55% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 61014 35.28% 86.83% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 22783 13.17% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 261694 # Type of FU issued -system.cpu3.iq.rate 1.629365 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 683137 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 278366 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 260191 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 172966 # Type of FU issued +system.cpu3.iq.rate 1.068166 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 334 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001931 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 506839 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 190218 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 171502 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 262003 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 173300 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 38539 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 18096 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1484 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1454 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1357 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 5389 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 51 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 309030 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 159 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 89942 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 43802 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1332 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 10558 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 205014 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 53782 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 23352 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 441 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1075 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1516 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 260676 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 89042 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1018 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1047 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1476 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 171988 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 52726 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 978 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 43196 # number of nop insts executed -system.cpu3.iew.exec_refs 132177 # number of memory reference insts executed -system.cpu3.iew.exec_branches 52784 # Number of branches executed -system.cpu3.iew.exec_stores 43135 # Number of stores executed -system.cpu3.iew.exec_rate 1.623027 # Inst execution rate -system.cpu3.iew.wb_sent 260451 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 260191 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 149829 # num instructions producing a value -system.cpu3.iew.wb_consumers 156442 # num instructions consuming a value +system.cpu3.iew.exec_nop 27464 # number of nop insts executed +system.cpu3.iew.exec_refs 75422 # number of memory reference insts executed +system.cpu3.iew.exec_branches 36861 # Number of branches executed +system.cpu3.iew.exec_stores 22696 # Number of stores executed +system.cpu3.iew.exec_rate 1.062126 # Inst execution rate +system.cpu3.iew.wb_sent 171762 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 171502 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 92998 # num instructions producing a value +system.cpu3.iew.wb_consumers 99577 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.620007 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.957729 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.059125 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.933931 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 13144 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 4136 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 156952 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.884863 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.121598 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 13412 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 8713 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1255 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 158053 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.211980 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.860135 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 54210 34.54% 34.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 49323 31.43% 65.96% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5280 3.36% 69.33% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 4930 3.14% 72.47% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1531 0.98% 73.45% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 38585 24.58% 98.03% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 839 0.53% 98.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1299 0.83% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 87086 55.10% 55.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 33413 21.14% 76.24% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5238 3.31% 79.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 9506 6.01% 85.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1538 0.97% 86.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 18185 11.51% 98.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 832 0.53% 98.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 959 0.61% 99.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1296 0.82% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 156952 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 295833 # Number of instructions committed -system.cpu3.commit.committedOps 295833 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 158053 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 191557 # Number of instructions committed +system.cpu3.commit.committedOps 191557 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 129866 # Number of memory references committed -system.cpu3.commit.loads 87548 # Number of loads committed -system.cpu3.commit.membars 3423 # Number of memory barriers committed -system.cpu3.commit.branches 51706 # Number of branches committed +system.cpu3.commit.refs 73159 # Number of memory references committed +system.cpu3.commit.loads 51261 # Number of loads committed +system.cpu3.commit.membars 7996 # Number of memory barriers committed +system.cpu3.commit.branches 35851 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 203693 # Number of committed integer instructions. +system.cpu3.commit.int_insts 131131 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 42497 14.37% 14.37% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 120047 40.58% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.94% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 90971 30.75% 85.70% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 42318 14.30% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 26638 13.91% 13.91% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 83764 43.73% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 59257 30.93% 88.57% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 21898 11.43% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 295833 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1299 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 464044 # The number of ROB reads -system.cpu3.rob.rob_writes 620441 # The number of ROB writes -system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1172 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.commit.op_class_0::total 191557 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1296 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 361140 # The number of ROB reads +system.cpu3.rob.rob_writes 412450 # The number of ROB writes +system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1364 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 249913 # Number of Instructions Simulated -system.cpu3.committedOps 249913 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.642668 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.642668 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.556014 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.556014 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 456401 # number of integer regfile reads -system.cpu3.int_regfile_writes 212686 # number of integer regfile writes +system.cpu3.committedInsts 156923 # Number of Instructions Simulated +system.cpu3.committedOps 156923 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.031895 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.031895 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.969091 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.969091 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 285937 # number of integer regfile reads +system.cpu3.int_regfile_writes 135307 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 133817 # number of misc regfile reads +system.cpu3.misc_regfile_reads 77019 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.217896 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 48316 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 23.138417 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 27896 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1725.571429 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 996.285714 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.217896 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047301 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047301 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.138417 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045192 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.045192 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 371433 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 371433 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 49959 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 49959 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 42098 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 42098 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 92057 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 92057 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 92057 # number of overall hits -system.cpu3.dcache.overall_hits::total 92057 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 521 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 521 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 153 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 153 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 674 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 674 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 674 # number of overall misses -system.cpu3.dcache.overall_misses::total 674 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8076500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 8076500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3408500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3408500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 574500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 574500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 11485000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 11485000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 11485000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 11485000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 50480 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 50480 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 42251 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 42251 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 92731 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 92731 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 92731 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 92731 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010321 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010321 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003621 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003621 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805970 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007268 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007268 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007268 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007268 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15501.919386 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 15501.919386 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22277.777778 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 22277.777778 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10638.888889 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 10638.888889 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17040.059347 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17040.059347 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 226271 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 226271 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 34144 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 34144 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 21673 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 21673 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 55817 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 55817 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 55817 # number of overall hits +system.cpu3.dcache.overall_hits::total 55817 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 154 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 154 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 617 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 617 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 617 # number of overall misses +system.cpu3.dcache.overall_misses::total 617 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7346500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 7346500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3280500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3280500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 658000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 658000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 10627000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 10627000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 10627000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 10627000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 34607 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 34607 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 21827 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 21827 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 56434 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 56434 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 56434 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 56434 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.013379 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.013379 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007055 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.732394 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.010933 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.010933 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.010933 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.010933 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15867.170626 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15867.170626 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21301.948052 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 21301.948052 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12653.846154 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 12653.846154 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17223.662885 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17223.662885 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2226,106 +2226,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 369 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 48 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 417 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 417 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 417 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 417 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1413000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1413000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2020500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2020500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 520500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 520500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3433500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3433500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3433500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3433500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003011 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003011 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002485 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002485 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805970 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805970 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002771 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002771 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002771 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9296.052632 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9296.052632 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19242.857143 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19242.857143 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9638.888889 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9638.888889 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13359.922179 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13359.922179 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 299 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 351 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 351 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 164 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 266 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 266 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1762500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1762500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1886000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1886000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 606000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 606000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3648500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3648500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3648500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3648500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004739 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004739 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004673 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004673 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.732394 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004713 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004713 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10746.951220 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10746.951220 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 18490.196078 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 18490.196078 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11653.846154 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11653.846154 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 384 # number of replacements -system.cpu3.icache.tags.tagsinuse 80.866510 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 17696 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 77.554391 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 27370 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 35.534137 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 54.959839 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.866510 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157942 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.157942 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.554391 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151473 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151473 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 18767 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 18767 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 17696 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 17696 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 17696 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 17696 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 17696 # number of overall hits -system.cpu3.icache.overall_hits::total 17696 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 573 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 573 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 573 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 573 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 573 # number of overall misses -system.cpu3.icache.overall_misses::total 573 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7430000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7430000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7430000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7430000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7430000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7430000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 18269 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 18269 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 18269 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 18269 # 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average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 12966.841187 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 12966.841187 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 12966.841187 # average overall miss latency +system.cpu3.icache.tags.tag_accesses 28439 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 28439 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 27370 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 27370 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 27370 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 27370 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 27370 # number of overall hits +system.cpu3.icache.overall_hits::total 27370 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 571 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 571 # 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number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 27941 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 27941 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 27941 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 27941 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020436 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.020436 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020436 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.020436 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020436 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.020436 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13441.330998 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13441.330998 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13441.330998 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13441.330998 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2334,77 +2334,77 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 75 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 75 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 75 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 75 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 73 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 73 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 73 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6421000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6421000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6421000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6421000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6421000 # 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average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12893.574297 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12893.574297 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6616000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6616000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6616000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6616000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6616000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6616000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017823 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.017823 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.017823 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13285.140562 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 418.779018 # Cycle average of tags in use -system.l2c.tags.total_refs 2347 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 419.148333 # Cycle average of tags in use +system.l2c.tags.total_refs 2348 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4.413534 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.786962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 287.801372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.040061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 61.655177 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5.312296 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2.346047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.677363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.443236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.716504 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.788271 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 288.012358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.076849 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 62.302913 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.322223 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3.076380 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.717940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.174188 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.677210 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004392 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000941 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000951 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000022 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006390 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000003 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25618 # Number of tag accesses -system.l2c.tags.data_accesses 25618 # Number of data accesses +system.l2c.tags.tag_accesses 25610 # Number of tag accesses +system.l2c.tags.data_accesses 25610 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 491 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 409 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 490 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits @@ -2413,36 +2413,36 @@ system.l2c.ReadSharedReq_hits::cpu3.data 11 # nu system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 410 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # 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number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 86 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 9 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 7 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 87 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 10 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 5 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses @@ -2451,62 +2451,62 @@ system.l2c.ReadSharedReq_misses::cpu3.data 1 # system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 87 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses system.l2c.demand_misses::total 679 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 362 # 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number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -2544,16 +2544,16 @@ system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.967391 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.966667 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173387 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.175403 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.020000 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses @@ -2562,55 +2562,55 @@ system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173387 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.175403 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.020000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.014056 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.010040 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.289059 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.595395 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173387 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.175403 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.018000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.020000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.014056 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.010040 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.289059 # miss rate for overall accesses -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78617.021277 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81053.191489 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81461.538462 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79708.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 109041.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 81786.259542 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76469.613260 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 74988.372093 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 70222.222222 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 73428.571429 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 76028.017241 # average ReadCleanReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 123791.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 94458.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 86236.641221 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 76461.325967 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 75005.747126 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 70750 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 68400 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 75978.448276 # average ReadCleanReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 79740 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 77214.285714 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82500 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 96500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 96500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 82500 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::total 79761.904762 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76469.613260 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 79115.384615 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74988.372093 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76461.325967 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 80470.414201 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75005.747126 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 79975 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 70222.222222 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 79923.076923 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 73428.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 108076.923077 # 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average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 79975 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 70222.222222 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 79923.076923 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 73428.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 108076.923077 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 77600.883652 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 70750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 121692.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 68400 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 93538.461538 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78425.625920 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2621,33 +2621,33 @@ system.l2c.fast_writes 0 # nu system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 6 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 2 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 5 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 6 # 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number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 45738500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 23885500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 11909500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 5496500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 1399500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 217000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 909000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 364000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 1275000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 45153500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 363500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1452000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 146000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 1086000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 45738500 # number of overall MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.967391 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.966667 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses @@ -2732,104 +2732,110 @@ system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.259259 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20842.105263 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20880.761905 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20886.318182 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20837.022472 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68617.021277 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21722.222222 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21763.157895 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21800 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21809.380952 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21770.080460 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71053.191489 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69708.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 99041.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 71786.259542 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72800 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66273.835920 # average ReadCleanReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 84458.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76236.641221 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72700 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73000 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66278.270510 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69740 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 72500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 534 # Transaction distribution -system.membus.trans_dist::UpgradeReq 292 # Transaction distribution -system.membus.trans_dist::UpgradeResp 89 # Transaction distribution -system.membus.trans_dist::ReadExReq 161 # Transaction distribution +system.membus.trans_dist::UpgradeReq 287 # Transaction distribution +system.membus.trans_dist::UpgradeResp 87 # Transaction distribution +system.membus.trans_dist::ReadExReq 162 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1742 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 233 # Total snoops (count) -system.membus.snoop_fanout::samples 988 # Request fanout histogram +system.membus.snoops 231 # Total snoops (count) +system.membus.snoop_fanout::samples 984 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 988 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 984 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 988 # Request fanout histogram -system.membus.reqLayer0.occupancy 929005 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 984 # Request fanout histogram +system.membus.reqLayer0.occupancy 923503 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.5 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadResp 2782 # Transaction distribution +system.membus.respLayer1.occupancy 3708663 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 4928 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2358 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadResp 2773 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 677 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 295 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 295 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 678 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 394 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 394 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 681 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 672 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6585 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 370 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1145 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1146 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6575 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) @@ -2839,41 +2845,41 @@ system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1026 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4937 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoops 1019 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4928 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.293425 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.231126 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 4937 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1910 38.76% 38.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 975 19.78% 58.54% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 730 14.81% 73.36% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1313 26.64% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4937 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2487961 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4928 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2484958 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 509492 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 505496 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 443468 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 435966 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 752993 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 752494 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 440464 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 426475 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 407479 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 424472 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 6ed919c46..9e7ba2833 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1750110 # Simulator instruction rate (inst/s) -host_op_rate 1750047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 226603798 # Simulator tick rate (ticks/s) -host_mem_usage 303668 # Number of bytes of host memory used +host_inst_rate 1726221 # Simulator instruction rate (inst/s) +host_op_rate 1726160 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 223510854 # Simulator tick rate (ticks/s) +host_mem_usage 306324 # Number of bytes of host memory used host_seconds 0.39 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated @@ -743,9 +743,9 @@ system.cpu3.icache.cache_copies 0 # nu system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use -system.l2c.tags.total_refs 2271 # Total number of references to valid blocks. +system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.394299 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4.076010 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor @@ -770,8 +770,8 @@ system.l2c.tags.occ_task_id_blocks::1024 421 # Oc system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 23864 # Number of tag accesses -system.l2c.tags.data_accesses 23864 # Number of data accesses +system.l2c.tags.tag_accesses 19424 # Number of tag accesses +system.l2c.tags.data_accesses 19424 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits @@ -950,24 +950,30 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1108 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1051 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 838 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 830 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) @@ -979,21 +985,21 @@ system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3918 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 89934d478..f34aec4c9 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000260 # Number of seconds simulated -sim_ticks 260073500 # Number of ticks simulated -final_tick 260073500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000261 # Number of seconds simulated +sim_ticks 260712500 # Number of ticks simulated +final_tick 260712500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1077387 # Simulator instruction rate (inst/s) -host_op_rate 1077364 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 425087977 # Simulator tick rate (ticks/s) -host_mem_usage 303432 # Number of bytes of host memory used -host_seconds 0.61 # Real time elapsed on the host -sim_insts 659129 # Number of instructions simulated -sim_ops 659129 # Number of ops (including micro ops) simulated +host_inst_rate 1018019 # Simulator instruction rate (inst/s) +host_op_rate 1017997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 401917302 # Simulator tick rate (ticks/s) +host_mem_usage 306320 # Number of bytes of host memory used +host_seconds 0.65 # Real time elapsed on the host +sim_insts 660333 # Number of instructions simulated +sim_ops 660333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory @@ -36,164 +36,164 @@ system.physmem.num_reads::cpu2.data 22 # Nu system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 70134020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40603906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 3445180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3937348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 13288551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5413854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 246084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3691264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 140760208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 70134020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 3445180 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 13288551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 246084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 87113835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 70134020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40603906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 3445180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3937348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 13288551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5413854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 246084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3691264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 140760208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69962123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40504387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 3436736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3927698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 13255981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5400585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 245481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3682217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140415208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69962123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 3436736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 13255981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 245481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86900321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69962123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40504387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 3436736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3927698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 13255981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5400585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 245481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3682217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 140415208 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 520147 # number of cpu cycles simulated +system.cpu0.numCycles 521425 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 157434 # Number of instructions committed -system.cpu0.committedOps 157434 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108448 # Number of integer alu accesses +system.cpu0.committedInsts 157788 # Number of instructions committed +system.cpu0.committedOps 157788 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108684 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25842 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108448 # number of integer instructions +system.cpu0.num_conditional_control_insts 25901 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108684 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 313502 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110054 # number of times the integer registers were written +system.cpu0.num_int_register_reads 314210 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110290 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73451 # number of memory refs -system.cpu0.num_load_insts 48627 # Number of load instructions -system.cpu0.num_store_insts 24824 # Number of store instructions +system.cpu0.num_mem_refs 73628 # number of memory refs +system.cpu0.num_load_insts 48745 # Number of load instructions +system.cpu0.num_store_insts 24883 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 520146.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 521424.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26707 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23434 14.88% 14.88% # Class of executed instruction -system.cpu0.op_class::IntAlu 60527 38.43% 53.31% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction -system.cpu0.op_class::MemRead 48711 30.93% 84.24% # Class of executed instruction -system.cpu0.op_class::MemWrite 24824 15.76% 100.00% # Class of executed instruction +system.cpu0.Branches 26766 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23493 14.88% 14.88% # Class of executed instruction +system.cpu0.op_class::IntAlu 60645 38.42% 53.30% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.30% # Class of executed instruction +system.cpu0.op_class::MemRead 48829 30.93% 84.24% # Class of executed instruction +system.cpu0.op_class::MemWrite 24883 15.76% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 157496 # Class of executed instruction +system.cpu0.op_class::total 157850 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.650768 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 72919 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.664312 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73097 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 436.640719 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 437.706587 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.650768 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284474 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284474 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.664312 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284501 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284501 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 294037 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 294037 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48447 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48447 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24590 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24590 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 294744 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 294744 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48566 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48566 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24649 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24649 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73037 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73037 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73037 # number of overall hits -system.cpu0.dcache.overall_hits::total 73037 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 73215 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73215 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73215 # number of overall hits +system.cpu0.dcache.overall_hits::total 73215 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 169 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 169 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses -system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4613500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4613500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6976500 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 352 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 352 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 352 # number of overall misses +system.cpu0.dcache.overall_misses::total 352 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4596500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4596500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7006000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7006000 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11590000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11590000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11590000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11590000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48617 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48617 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24773 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24773 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 11602500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11602500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11602500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11602500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48735 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48735 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24832 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24832 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73390 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73390 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73390 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73390 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003497 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003497 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007387 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007387 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73567 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73567 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73567 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73567 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003468 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003468 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007370 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007370 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004810 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004810 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004810 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004810 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27138.235294 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27138.235294 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38122.950820 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38122.950820 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004785 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004785 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004785 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004785 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27198.224852 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27198.224852 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38284.153005 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38284.153005 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32832.861190 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32832.861190 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32832.861190 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32961.647727 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32961.647727 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,98 +204,98 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 169 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4443500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4443500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6793500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6793500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 352 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 352 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 352 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 352 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4427500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4427500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6823000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6823000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11237000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11237000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11237000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11237000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003497 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003497 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007387 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007387 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11250500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11250500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11250500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11250500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003468 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003468 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007370 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007370 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004810 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004810 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004810 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26138.235294 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26138.235294 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37122.950820 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37122.950820 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004785 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004785 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26198.224852 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26198.224852 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37284.153005 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37284.153005 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31832.861190 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31832.861190 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.583222 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157030 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 212.605336 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157384 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 336.252677 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 337.010707 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.583222 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415202 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.415202 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.605336 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415245 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.415245 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 157964 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 157964 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 157030 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157030 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157030 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157030 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157030 # number of overall hits -system.cpu0.icache.overall_hits::total 157030 # number of overall hits +system.cpu0.icache.tags.tag_accesses 158318 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 158318 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157384 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157384 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157384 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157384 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157384 # number of overall hits +system.cpu0.icache.overall_hits::total 157384 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18042500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18042500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18042500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18042500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18042500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18042500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 157497 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 157497 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 157497 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 157497 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 157497 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 157497 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002965 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002965 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002965 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002965 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002965 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002965 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38634.903640 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38634.903640 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38634.903640 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38634.903640 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18137000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18137000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18137000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18137000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18137000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18137000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 157851 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 157851 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 157851 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 157851 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 157851 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 157851 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002958 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002958 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002958 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002958 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002958 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002958 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38837.259101 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38837.259101 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38837.259101 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38837.259101 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -310,158 +310,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17575500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17575500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17575500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17575500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17575500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17575500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002965 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002965 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002965 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37634.903640 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17670000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17670000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17670000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17670000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17670000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17670000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37837.259101 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 520147 # number of cpu cycles simulated +system.cpu1.numCycles 521425 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 165571 # Number of instructions committed -system.cpu1.committedOps 165571 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111555 # Number of integer alu accesses +system.cpu1.committedInsts 168182 # Number of instructions committed +system.cpu1.committedOps 168182 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110851 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 31016 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111555 # number of integer instructions +system.cpu1.num_conditional_control_insts 32674 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110851 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 284333 # number of times the integer registers were read -system.cpu1.num_int_register_writes 108565 # number of times the integer registers were written +system.cpu1.num_int_register_reads 274889 # number of times the integer registers were read +system.cpu1.num_int_register_writes 104194 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 56707 # number of memory refs -system.cpu1.num_load_insts 41448 # Number of load instructions -system.cpu1.num_store_insts 15259 # Number of store instructions -system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles -system.cpu1.num_busy_cycles 452419.998260 # Number of busy cycles -system.cpu1.not_idle_fraction 0.869793 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.130207 # Percentage of idle cycles -system.cpu1.Branches 32668 # Number of branches fetched -system.cpu1.op_class::No_OpClass 23452 14.16% 14.16% # Class of executed instruction -system.cpu1.op_class::IntAlu 74986 45.28% 59.44% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.44% # Class of executed instruction -system.cpu1.op_class::MemRead 51906 31.34% 90.79% # Class of executed instruction -system.cpu1.op_class::MemWrite 15259 9.21% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 54346 # number of memory refs +system.cpu1.num_load_insts 41092 # Number of load instructions +system.cpu1.num_store_insts 13254 # Number of store instructions +system.cpu1.num_idle_cycles 67743.001740 # Number of idle cycles +system.cpu1.num_busy_cycles 453681.998260 # Number of busy cycles +system.cpu1.not_idle_fraction 0.870081 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.129919 # Percentage of idle cycles +system.cpu1.Branches 34327 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25108 14.93% 14.93% # Class of executed instruction +system.cpu1.op_class::IntAlu 74636 44.37% 59.30% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.30% # Class of executed instruction +system.cpu1.op_class::MemRead 55216 32.82% 92.12% # Class of executed instruction +system.cpu1.op_class::MemWrite 13254 7.88% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 165603 # Class of executed instruction +system.cpu1.op_class::total 168214 # Class of executed instruction system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.035238 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 32753 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.819046 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 28734 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1129.413793 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 990.827586 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.035238 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050850 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050850 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.819046 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052381 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.052381 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 227042 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 227042 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41284 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41284 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 15082 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 15082 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 56366 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 56366 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 56366 # number of overall hits -system.cpu1.dcache.overall_hits::total 56366 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 156 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 156 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 265 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 265 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 265 # number of overall misses -system.cpu1.dcache.overall_misses::total 265 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2383000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2383000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2068000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2068000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 251500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 251500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4451000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4451000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4451000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4451000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41440 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41440 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 15191 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 15191 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 56631 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 56631 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 56631 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 56631 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003764 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007175 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.007175 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.833333 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004679 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004679 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004679 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004679 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15275.641026 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15275.641026 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18972.477064 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18972.477064 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4572.727273 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4572.727273 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16796.226415 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16796.226415 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 217604 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 217604 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 40921 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40921 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 13075 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 13075 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 53996 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 53996 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 53996 # number of overall hits +system.cpu1.dcache.overall_hits::total 53996 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 271 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 271 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 271 # number of overall misses +system.cpu1.dcache.overall_misses::total 271 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2627500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2627500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1987500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1987500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 248500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 248500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4615000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4615000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4615000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4615000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41084 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41084 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 13183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 13183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 54267 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 54267 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 54267 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 54267 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003967 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003967 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008192 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008192 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004994 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004994 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004994 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004994 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16119.631902 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16119.631902 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18402.777778 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18402.777778 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4437.500000 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4437.500000 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17029.520295 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17029.520295 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,99 +470,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2227000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2227000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1959000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1959000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 196500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 196500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4186000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4186000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4186000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4186000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003764 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007175 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007175 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.833333 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004679 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004679 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004679 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14275.641026 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14275.641026 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17972.477064 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17972.477064 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3572.727273 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3572.727273 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15796.226415 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15796.226415 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 271 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 271 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2464500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2464500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1879500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1879500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 192500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 192500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4344000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4344000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4344000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003967 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003967 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008192 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008192 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004994 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004994 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004994 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15119.631902 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15119.631902 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17402.777778 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17402.777778 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3437.500000 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3437.500000 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16029.520295 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16029.520295 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 65.699918 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 165238 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 67.790334 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167849 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 451.469945 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 458.603825 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.699918 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128320 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.128320 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.790334 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.132403 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.132403 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 165970 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 165970 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 165238 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 165238 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 165238 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 165238 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 165238 # number of overall hits -system.cpu1.icache.overall_hits::total 165238 # number of overall hits +system.cpu1.icache.tags.tag_accesses 168581 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 168581 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 167849 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 167849 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 167849 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 167849 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 167849 # number of overall hits +system.cpu1.icache.overall_hits::total 167849 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5351500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5351500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5351500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5351500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5351500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5351500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 165604 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 165604 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 165604 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 165604 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 165604 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 165604 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002210 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002210 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002210 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14621.584699 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14621.584699 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14621.584699 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14621.584699 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14621.584699 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5586500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5586500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5586500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5586500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5586500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5586500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 168215 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 168215 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 168215 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 168215 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 168215 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 168215 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002176 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002176 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002176 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002176 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002176 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002176 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15263.661202 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15263.661202 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15263.661202 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15263.661202 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,158 +577,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4985500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4985500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4985500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4985500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4985500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4985500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13621.584699 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5220500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5220500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5220500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5220500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5220500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5220500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002176 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002176 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002176 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14263.661202 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 520146 # number of cpu cycles simulated +system.cpu2.numCycles 521424 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 160598 # Number of instructions committed -system.cpu2.committedOps 160598 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 111601 # Number of integer alu accesses +system.cpu2.committedInsts 165155 # Number of instructions committed +system.cpu2.committedOps 165155 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110249 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 28506 # number of instructions that are conditional controls -system.cpu2.num_int_insts 111601 # number of integer instructions +system.cpu2.num_conditional_control_insts 31462 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110249 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 294560 # number of times the integer registers were read -system.cpu2.num_int_register_writes 113655 # number of times the integer registers were written +system.cpu2.num_int_register_reads 277329 # number of times the integer registers were read +system.cpu2.num_int_register_writes 105715 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59264 # number of memory refs -system.cpu2.num_load_insts 41473 # Number of load instructions -system.cpu2.num_store_insts 17791 # Number of store instructions -system.cpu2.num_idle_cycles 67981.871041 # Number of idle cycles -system.cpu2.num_busy_cycles 452164.128959 # Number of busy cycles -system.cpu2.not_idle_fraction 0.869302 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.130698 # Percentage of idle cycles -system.cpu2.Branches 30158 # Number of branches fetched -system.cpu2.op_class::No_OpClass 20943 13.04% 13.04% # Class of executed instruction -system.cpu2.op_class::IntAlu 75009 46.70% 59.73% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.73% # Class of executed instruction -system.cpu2.op_class::MemRead 46887 29.19% 88.92% # Class of executed instruction -system.cpu2.op_class::MemWrite 17791 11.08% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 54956 # number of memory refs +system.cpu2.num_load_insts 40791 # Number of load instructions +system.cpu2.num_store_insts 14165 # Number of store instructions +system.cpu2.num_idle_cycles 67997.871331 # Number of idle cycles +system.cpu2.num_busy_cycles 453426.128669 # Number of busy cycles +system.cpu2.not_idle_fraction 0.869592 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.130408 # Percentage of idle cycles +system.cpu2.Branches 33115 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23895 14.47% 14.47% # Class of executed instruction +system.cpu2.op_class::IntAlu 74335 45.00% 59.47% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction +system.cpu2.op_class::MemRead 52792 31.96% 91.42% # Class of executed instruction +system.cpu2.op_class::MemWrite 14165 8.58% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 160630 # Class of executed instruction +system.cpu2.op_class::total 165187 # Class of executed instruction system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.808310 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 37821 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.775093 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 30556 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1304.172414 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1053.655172 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.808310 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054313 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.054313 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.775093 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054248 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.054248 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 237265 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 237265 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 41314 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 41314 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 17614 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 17614 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58928 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58928 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58928 # number of overall hits -system.cpu2.dcache.overall_hits::total 58928 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 151 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 261 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 261 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 261 # number of overall misses -system.cpu2.dcache.overall_misses::total 261 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2416500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2416500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2235500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2235500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 248000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 248000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4652000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4652000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4652000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4652000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 41465 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 41465 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 17724 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 17724 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 65 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 59189 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 59189 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 59189 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 59189 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003642 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003642 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006206 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006206 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.846154 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.846154 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004410 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004410 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004410 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004410 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.311258 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16003.311258 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20322.727273 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20322.727273 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4509.090909 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4509.090909 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17823.754789 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17823.754789 # average overall miss latency +system.cpu2.dcache.tags.tag_accesses 220041 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 220041 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40622 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40622 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 13986 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 13986 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 54608 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 54608 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 54608 # number of overall hits +system.cpu2.dcache.overall_hits::total 54608 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 161 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 161 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses +system.cpu2.dcache.overall_misses::total 269 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2814500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2814500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2046000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2046000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 249500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 249500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4860500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4860500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4860500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4860500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40783 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40783 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 14094 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 14094 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 54877 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 54877 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 54877 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 54877 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003948 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003948 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007663 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.007663 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004902 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004902 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004902 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004902 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17481.366460 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17481.366460 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18944.444444 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18944.444444 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4455.357143 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4455.357143 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 18068.773234 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 18068.773234 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,99 +737,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2265500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2265500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2125500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2125500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4391000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4391000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4391000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4391000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003642 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003642 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006206 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006206 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.846154 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004410 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004410 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004410 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15003.311258 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15003.311258 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19322.727273 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19322.727273 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3509.090909 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3509.090909 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16823.754789 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16823.754789 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 269 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 269 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2653500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2653500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1938000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1938000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4591500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4591500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4591500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4591500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003948 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003948 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007663 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007663 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004902 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004902 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16481.366460 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16481.366460 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17944.444444 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17944.444444 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3455.357143 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3455.357143 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 70.147178 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 160265 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 70.166597 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164822 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 437.882514 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 450.333333 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.147178 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137006 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.137006 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.166597 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137044 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.137044 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 160997 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 160997 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 160265 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 160265 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 160265 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 160265 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 160265 # number of overall hits -system.cpu2.icache.overall_hits::total 160265 # number of overall hits +system.cpu2.icache.tags.tag_accesses 165554 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 165554 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 164822 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 164822 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 164822 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 164822 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 164822 # number of overall hits +system.cpu2.icache.overall_hits::total 164822 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7437500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7437500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7437500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7437500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7437500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7437500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 160631 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 160631 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 160631 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 160631 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 160631 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 160631 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002279 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002279 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002279 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002279 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002279 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002279 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20321.038251 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 20321.038251 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 20321.038251 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20321.038251 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 20321.038251 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7626500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7626500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7626500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7626500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7626500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7626500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165188 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165188 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165188 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165188 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165188 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165188 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002216 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002216 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002216 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002216 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002216 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002216 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20837.431694 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 20837.431694 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 20837.431694 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 20837.431694 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -844,158 +844,158 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7071500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7071500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7071500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7071500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7071500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7071500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002279 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002279 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002279 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002279 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19321.038251 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19321.038251 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 19321.038251 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7260500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7260500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7260500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7260500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7260500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7260500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002216 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002216 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002216 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19837.431694 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 520146 # number of cpu cycles simulated +system.cpu3.numCycles 521424 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 175526 # Number of instructions committed -system.cpu3.committedOps 175526 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 107877 # Number of integer alu accesses +system.cpu3.committedInsts 169208 # Number of instructions committed +system.cpu3.committedOps 169208 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 110441 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 37833 # number of instructions that are conditional controls -system.cpu3.num_int_insts 107877 # number of integer instructions +system.cpu3.num_conditional_control_insts 33391 # number of instructions that are conditional controls +system.cpu3.num_int_insts 110441 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 242346 # number of times the integer registers were read -system.cpu3.num_int_register_writes 89400 # number of times the integer registers were written +system.cpu3.num_int_register_reads 270379 # number of times the integer registers were read +system.cpu3.num_int_register_writes 102142 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 46213 # number of memory refs -system.cpu3.num_load_insts 39592 # Number of load instructions -system.cpu3.num_store_insts 6621 # Number of store instructions -system.cpu3.num_idle_cycles 68237.870548 # Number of idle cycles -system.cpu3.num_busy_cycles 451908.129452 # Number of busy cycles -system.cpu3.not_idle_fraction 0.868810 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.131190 # Percentage of idle cycles -system.cpu3.Branches 39491 # Number of branches fetched -system.cpu3.op_class::No_OpClass 30262 17.24% 17.24% # Class of executed instruction -system.cpu3.op_class::IntAlu 73148 41.67% 58.90% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.90% # Class of executed instruction -system.cpu3.op_class::MemRead 65527 37.32% 96.23% # Class of executed instruction -system.cpu3.op_class::MemWrite 6621 3.77% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 53219 # number of memory refs +system.cpu3.num_load_insts 40883 # Number of load instructions +system.cpu3.num_store_insts 12336 # Number of store instructions +system.cpu3.num_idle_cycles 68253.870839 # Number of idle cycles +system.cpu3.num_busy_cycles 453170.129161 # Number of busy cycles +system.cpu3.not_idle_fraction 0.869101 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.130899 # Percentage of idle cycles +system.cpu3.Branches 35047 # Number of branches fetched +system.cpu3.op_class::No_OpClass 25824 15.26% 15.26% # Class of executed instruction +system.cpu3.op_class::IntAlu 74433 43.98% 59.24% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.24% # Class of executed instruction +system.cpu3.op_class::MemRead 56647 33.47% 92.71% # Class of executed instruction +system.cpu3.op_class::MemWrite 12336 7.29% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 175558 # Class of executed instruction +system.cpu3.op_class::total 169240 # Class of executed instruction system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 26.732151 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 15554 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.991280 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 27009 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 518.466667 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 900.300000 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.732151 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052211 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.052211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.991280 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050764 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050764 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 185088 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 185088 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 39402 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 39402 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 6435 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 6435 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 45837 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 45837 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 45837 # number of overall hits -system.cpu3.dcache.overall_hits::total 45837 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 182 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 182 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 60 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 60 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 287 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 287 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 287 # number of overall misses -system.cpu3.dcache.overall_misses::total 287 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3223000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 3223000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1728500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1728500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 276500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 276500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4951500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4951500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4951500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4951500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 39584 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 39584 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 6540 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 6540 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 46124 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 46124 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 46124 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 46124 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004598 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.004598 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016055 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.016055 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.759494 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.759494 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006222 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.006222 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006222 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.006222 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17708.791209 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17708.791209 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16461.904762 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 16461.904762 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4608.333333 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4608.333333 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17252.613240 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17252.613240 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 213096 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 213096 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40712 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40712 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 12155 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 12155 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 52867 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 52867 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 52867 # number of overall hits +system.cpu3.dcache.overall_hits::total 52867 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 270 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 270 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 270 # number of overall misses +system.cpu3.dcache.overall_misses::total 270 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2676500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2676500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1989500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1989500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 259000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 259000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4666000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4666000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4666000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4666000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 40875 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 40875 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 12262 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 12262 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 53137 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 53137 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 53137 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 53137 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003988 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003988 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008726 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.008726 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005081 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005081 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005081 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005081 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16420.245399 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16420.245399 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18593.457944 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18593.457944 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4465.517241 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4465.517241 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17281.481481 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17281.481481 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1004,99 +1004,99 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 182 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 60 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 287 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 287 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3041000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3041000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1623500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1623500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 216500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 216500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4664500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4664500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4664500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4664500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004598 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004598 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016055 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.759494 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.759494 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.006222 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006222 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.006222 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16708.791209 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16708.791209 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15461.904762 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15461.904762 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3608.333333 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3608.333333 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16252.613240 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16252.613240 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2513500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2513500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1882500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1882500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4396000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4396000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4396000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4396000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003988 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003988 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008726 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005081 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005081 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15420.245399 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15420.245399 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17593.457944 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17593.457944 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3465.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3465.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 67.821849 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 175192 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 65.768661 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 168874 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 477.362398 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 460.147139 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.821849 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132465 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.132465 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.768661 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128454 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.128454 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 175926 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 175926 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 175192 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 175192 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 175192 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 175192 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 175192 # number of overall hits -system.cpu3.icache.overall_hits::total 175192 # number of overall hits +system.cpu3.icache.tags.tag_accesses 169608 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 169608 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 168874 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 168874 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 168874 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 168874 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 168874 # number of overall hits +system.cpu3.icache.overall_hits::total 168874 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5136500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5136500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5136500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5136500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5136500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5136500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 175559 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 175559 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 175559 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 175559 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 175559 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 175559 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002090 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002090 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002090 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002090 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002090 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002090 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13995.912807 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13995.912807 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13995.912807 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13995.912807 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13995.912807 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5371500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5371500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5371500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5371500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5371500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5371500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 169241 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 169241 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 169241 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 169241 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 169241 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 169241 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002169 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002169 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002169 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002169 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002169 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002169 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14636.239782 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14636.239782 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14636.239782 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14636.239782 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1111,56 +1111,56 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4769500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4769500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4769500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4769500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4769500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4769500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002090 # 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mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002169 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002169 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13636.239782 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.351676 # Cycle average of tags in use +system.l2c.tags.tagsinuse 349.411371 # Cycle average of tags in use system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 4 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.890425 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.950289 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.237156 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.367865 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.832949 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 47.203910 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.135421 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.888032 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.845628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.890694 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.985944 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.243981 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.369557 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.864661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 47.217011 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.137141 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.888283 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.814098 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003540 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.000097 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.000720 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005331 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005332 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19677 # Number of tag accesses -system.l2c.tags.data_accesses 19677 # Number of data accesses +system.l2c.tags.tag_accesses 19669 # Number of tag accesses +system.l2c.tags.data_accesses 19669 # Number of data accesses system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits @@ -1194,10 +1194,10 @@ system.l2c.overall_hits::cpu3.inst 358 # nu system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses @@ -1233,44 +1233,44 @@ system.l2c.overall_misses::cpu3.data 16 # nu system.l2c.overall_misses::total 592 # number of overall misses system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 735000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 797000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 795500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3.data 744000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7473500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14964000 # number of ReadCleanReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7472000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 14963500 # number of ReadCleanReq miss cycles system.l2c.ReadCleanReq_miss_latency::cpu1.inst 740000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3341500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 453500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 19499000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3340500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 446500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 19490500 # number of ReadCleanReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.data 3465000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 105000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu2.data 419000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu3.data 104500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 4093500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 14964000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 14963500 # 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number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) @@ -1308,7 +1308,7 @@ system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.974359 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1344,37 +1344,37 @@ system.l2c.overall_miss_rate::cpu3.data 0.640000 # mi system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52500 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53133.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53033.333333 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 53142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52630.281690 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 52505.263158 # average ReadCleanReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52619.718310 # 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average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 50388.888889 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 52195.312500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52804.347826 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 49611.111111 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.data 53031.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52476.351351 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52459.459459 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1400,10 +1400,10 @@ system.l2c.overall_mshr_hits::cpu3.inst 8 # nu system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 11 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses @@ -1437,49 +1437,49 @@ system.l2c.overall_mshr_misses::cpu2.data 22 # n system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1194000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 765000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 850000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 479492 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3288492 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1222000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 700497 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 700497 # 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number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 12114000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 12113500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 7012500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 600000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 680000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 2295500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 944500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 943000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 42500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 646500 # 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number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 646500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 24335500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24333500 # number of overall MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.974359 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1513,88 +1513,94 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 42642.857143 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 42500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 42500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43590.181818 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42707.688312 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 43642.857143 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 43781.062500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 43781.062500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43687.375000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43710.421053 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43133.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43033.333333 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 42630.281690 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 272 # Transaction distribution -system.membus.trans_dist::UpgradeResp 77 # Transaction distribution +system.membus.trans_dist::UpgradeReq 271 # Transaction distribution +system.membus.trans_dist::UpgradeResp 76 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 261 # Total snoops (count) -system.membus.snoop_fanout::samples 914 # Request fanout histogram +system.membus.snoop_fanout::samples 913 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 913 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 914 # Request fanout histogram -system.membus.reqLayer0.occupancy 665648 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 913 # Request fanout histogram +system.membus.reqLayer0.occupancy 664148 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2948008 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2946008 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 3982 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1114 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadResp 2222 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 656 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 846 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5316 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 853 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5311 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) @@ -1604,41 +1610,41 @@ system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1037 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3986 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoops 1034 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3982 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.291562 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.219091 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3986 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1499 37.64% 37.64% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 871 21.87% 59.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 564 14.16% 73.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1048 26.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3986 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1998491 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3982 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1996990 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 503490 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 501990 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 419983 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 431977 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 412483 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 427478 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 467954 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 432477 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 96f88f923..61ea5a710 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1817 +1,1819 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000889 # Number of seconds simulated -sim_ticks 888991000 # Number of ticks simulated -final_tick 888991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000518 # Number of seconds simulated +sim_ticks 518362500 # Number of ticks simulated +final_tick 518362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 170326912 # Simulator tick rate (ticks/s) -host_mem_usage 278304 # Number of bytes of host memory used -host_seconds 5.22 # Real time elapsed on the host +host_tick_rate 97254136 # Simulator tick rate (ticks/s) +host_mem_usage 280792 # Number of bytes of host memory used +host_seconds 5.33 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 77301 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 77008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 78427 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 77571 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 81605 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77234 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 80454 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78765 # Number of bytes read from this memory -system.physmem.bytes_read::total 628365 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 396032 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5354 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5486 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5463 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5457 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5585 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5519 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5444 # Number of bytes written to this memory -system.physmem.bytes_written::total 439804 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10773 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11043 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10839 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10977 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87447 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6188 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5354 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5486 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5463 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5457 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5585 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5519 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5444 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49960 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 86953636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 86624049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 88220241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 87257351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 91795080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 86878270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 90500354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 88600447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 706829428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 445484825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 6022558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6171041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 6145169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 6138420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6146294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 6282403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 6208162 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 6123797 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 494722669 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 445484825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 92976194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 92795090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 94365410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 93395771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 97941374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 93160673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 96708516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 94724244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1201552097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 83556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 80496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 82210 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 83458 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79724 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 80437 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 82031 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 84431 # Number of bytes read from this memory +system.physmem.bytes_read::total 656343 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 416960 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5428 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5478 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5268 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5521 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5505 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5477 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5442 # Number of bytes written to this memory +system.physmem.bytes_written::total 460429 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10676 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10910 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6515 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5428 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5478 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5268 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5521 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5505 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5477 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5442 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49984 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 161192216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 155289011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 158595577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 161003159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 153799706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 155175191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 158250259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 162880224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1266185343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 804379175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10320963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10471436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10567894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10162772 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10650848 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10619981 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10565965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10498445 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 888237479 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 804379175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 171513179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 165760448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 169163472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 171165931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 164450553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 165795172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 168816224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 173378668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2154422822 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99131 # number of read accesses completed -system.cpu0.num_writes 55164 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22535 # number of replacements -system.cpu0.l1c.tags.tagsinuse 395.025918 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13450 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.586338 # Average number of references to valid blocks. +system.cpu0.num_reads 99891 # number of read accesses completed +system.cpu0.num_writes 54838 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22327 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.597191 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13273 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22716 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.584302 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 395.025918 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.771535 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.771535 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338659 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338659 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8591 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8591 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1192 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1192 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9783 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9783 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9783 # number of overall hits -system.cpu0.l1c.overall_hits::total 9783 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36665 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36665 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23983 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23983 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60648 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60648 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60648 # number of overall misses -system.cpu0.l1c.overall_misses::total 60648 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1205183022 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1205183022 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1064148669 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1064148669 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2269331691 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2269331691 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2269331691 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2269331691 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45256 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45256 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25175 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70431 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70431 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70431 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70431 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810169 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.810169 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952651 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.952651 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.861098 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.861098 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.861098 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.861098 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 32870.121969 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 32870.121969 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 44370.957303 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 44370.957303 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 37418.079590 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 37418.079590 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 37418.079590 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 37418.079590 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1129963 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.597191 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.764838 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.764838 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337776 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337776 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8714 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8714 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9862 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9862 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9862 # number of overall hits +system.cpu0.l1c.overall_hits::total 9862 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36629 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36629 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23739 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23739 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60368 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60368 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60368 # number of overall misses +system.cpu0.l1c.overall_misses::total 60368 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 614304512 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 614304512 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 680799251 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 680799251 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1295103763 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1295103763 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1295103763 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1295103763 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45343 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45343 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24887 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24887 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70230 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70230 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807820 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807820 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953871 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953871 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859576 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859576 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859576 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859576 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16770.987797 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16770.987797 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28678.514301 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 28678.514301 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21453.481364 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21453.481364 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21453.481364 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21453.481364 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 764972 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 56549 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61598 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 19.982016 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.418780 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9979 # number of writebacks -system.cpu0.l1c.writebacks::total 9979 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36665 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36665 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23983 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60648 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60648 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9718 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9718 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5355 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5355 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15073 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1168518022 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1168518022 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1040166669 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1040166669 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2208684691 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2208684691 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2208684691 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2208684691 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 789521900 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 789521900 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1493953369 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1493953369 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2283475269 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2283475269 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810169 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810169 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952651 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952651 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.861098 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.861098 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 31870.121969 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 31870.121969 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 43370.998999 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 43370.998999 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 81243.249640 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81243.249640 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 278982.888702 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 278982.888702 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 151494.411796 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 151494.411796 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9814 # number of writebacks +system.cpu0.l1c.writebacks::total 9814 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36629 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36629 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23739 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23739 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60368 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60368 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9828 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5350 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5350 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15178 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15178 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 577676512 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 577676512 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 657061251 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 657061251 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1234737763 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1234737763 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1234737763 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1234737763 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 645410094 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 645410094 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 821386793 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 821386793 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1466796887 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1466796887 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807820 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807820 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953871 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953871 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859576 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859576 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859576 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15771.015097 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15771.015097 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27678.556426 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27678.556426 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65670.542735 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65670.542735 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153530.241682 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153530.241682 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 96639.668402 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 96639.668402 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99860 # number of read accesses completed -system.cpu1.num_writes 55211 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22541 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.711444 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13500 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22934 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.588646 # Average number of references to valid blocks. +system.cpu1.num_reads 99259 # number of read accesses completed +system.cpu1.num_writes 55194 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22288 # number of replacements +system.cpu1.l1c.tags.tagsinuse 392.187813 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13481 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.594322 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.711444 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.772874 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.772874 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338432 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338432 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8752 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8752 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1139 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1139 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9891 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9891 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9891 # number of overall hits -system.cpu1.l1c.overall_hits::total 9891 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36537 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36537 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23971 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23971 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60508 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60508 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60508 # number of overall misses -system.cpu1.l1c.overall_misses::total 60508 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1195916774 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1195916774 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1059745891 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1059745891 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2255662665 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2255662665 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2255662665 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2255662665 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45289 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45289 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25110 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25110 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70399 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70399 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70399 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70399 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806752 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.806752 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954640 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954640 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859501 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859501 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859501 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859501 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 32731.663081 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 32731.663081 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 44209.498602 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 44209.498602 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 37278.750992 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 37278.750992 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 37278.750992 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 37278.750992 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1120827 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 392.187813 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.765992 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.765992 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 337082 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 337082 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8742 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8742 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1127 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1127 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9869 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9869 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9869 # number of overall hits +system.cpu1.l1c.overall_hits::total 9869 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36456 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36456 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23797 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23797 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60253 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses +system.cpu1.l1c.overall_misses::total 60253 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 609449513 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 609449513 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 681132433 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 681132433 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1290581946 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1290581946 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1290581946 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1290581946 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45198 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45198 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24924 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70122 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70122 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70122 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70122 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806584 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.806584 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954783 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954783 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859260 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859260 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859260 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859260 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16717.399413 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16717.399413 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28622.617683 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 28622.617683 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21419.380711 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21419.380711 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21419.380711 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21419.380711 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 761379 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 56192 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61322 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 19.946380 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.416082 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9897 # number of writebacks -system.cpu1.l1c.writebacks::total 9897 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36537 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36537 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23971 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60508 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60508 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60508 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60508 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5487 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5487 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15231 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15231 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1159382774 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1159382774 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1035775891 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1035775891 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2195158665 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2195158665 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2195158665 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2195158665 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 792485431 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 792485431 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1532713252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1532713252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2325198683 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2325198683 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806752 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806752 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954640 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954640 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859501 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859501 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 31731.745190 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 31731.745190 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 43209.540320 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 43209.540320 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 81330.606630 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81330.606630 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 279335.383999 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279335.383999 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 152662.246931 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 152662.246931 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9824 # number of writebacks +system.cpu1.l1c.writebacks::total 9824 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36456 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23797 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9840 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9840 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5428 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15268 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15268 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 572994513 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 572994513 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 657337433 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 657337433 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1230331946 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1230331946 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1230331946 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1230331946 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 646152701 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 646152701 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 842788738 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 842788738 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1488941439 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1488941439 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806584 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806584 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954783 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954783 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859260 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859260 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15717.426843 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15717.426843 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27622.701727 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27622.701727 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65665.924898 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65665.924898 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 155266.900884 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155266.900884 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 97520.398153 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 97520.398153 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99820 # number of read accesses completed -system.cpu2.num_writes 54950 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22307 # number of replacements -system.cpu2.l1c.tags.tagsinuse 395.344704 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13648 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22708 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks. +system.cpu2.num_reads 99508 # number of read accesses completed +system.cpu2.num_writes 54525 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22121 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.684502 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13597 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22507 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.604123 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 395.344704 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.772158 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.772158 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339436 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339436 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8860 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8860 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1133 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1133 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits -system.cpu2.l1c.overall_hits::total 9993 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36664 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36664 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23971 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23971 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60635 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60635 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60635 # number of overall misses -system.cpu2.l1c.overall_misses::total 60635 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1194013761 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1194013761 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1064419870 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1064419870 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2258433631 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2258433631 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2258433631 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2258433631 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45524 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45524 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25104 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25104 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70628 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70628 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70628 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70628 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805377 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805377 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954868 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858512 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858512 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858512 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858512 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 32566.380128 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 32566.380128 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 44404.483334 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 44404.483334 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 37246.369770 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 37246.369770 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 37246.369770 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 37246.369770 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1131174 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.684502 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.766962 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.766962 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338301 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338301 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8815 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8815 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9936 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9936 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9936 # number of overall hits +system.cpu2.l1c.overall_hits::total 9936 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36608 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36608 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23851 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23851 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses +system.cpu2.l1c.overall_misses::total 60459 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 611593894 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 611593894 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 682333894 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 682333894 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1293927788 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1293927788 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1293927788 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1293927788 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45423 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45423 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24972 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70395 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70395 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70395 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70395 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805935 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805935 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955110 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955110 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858854 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858854 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858854 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858854 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16706.563975 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16706.563975 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28608.188084 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 28608.188084 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21401.739824 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21401.739824 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21401.739824 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21401.739824 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 766345 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 56579 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61950 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 19.992824 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.370379 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks -system.cpu2.l1c.writebacks::total 9745 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36664 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36664 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23971 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60635 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60635 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60635 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60635 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9885 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5464 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15349 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15349 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1157350761 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1157350761 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040448870 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040448870 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2197799631 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2197799631 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2197799631 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2197799631 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 800475880 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 800475880 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1507844825 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1507844825 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2308320705 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2308320705 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805377 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805377 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954868 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858512 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858512 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 31566.407402 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 31566.407402 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 43404.483334 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 43404.483334 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 80978.844714 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80978.844714 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 275959.887445 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 275959.887445 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 150388.996352 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 150388.996352 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9721 # number of writebacks +system.cpu2.l1c.writebacks::total 9721 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36608 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23851 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9890 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9890 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5479 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5479 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15369 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 574987894 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 574987894 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 658483894 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 658483894 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1233471788 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1233471788 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1233471788 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1233471788 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 648669577 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 648669577 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 848315711 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 848315711 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1496985288 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1496985288 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805935 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805935 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955110 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955110 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858854 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858854 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15706.618608 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15706.618608 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27608.230011 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27608.230011 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65588.430435 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65588.430435 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154830.390765 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154830.390765 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97402.907671 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97402.907671 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99181 # number of read accesses completed -system.cpu3.num_writes 54913 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22385 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.599023 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13320 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.584749 # Average number of references to valid blocks. +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55096 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22478 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.167313 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13728 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22864 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.600420 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.599023 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770701 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770701 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337671 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337671 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8526 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8526 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1172 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1172 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9698 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9698 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9698 # number of overall hits -system.cpu3.l1c.overall_hits::total 9698 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36662 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36662 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23851 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23851 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60513 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60513 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60513 # number of overall misses -system.cpu3.l1c.overall_misses::total 60513 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1194465114 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1194465114 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1056306776 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1056306776 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2250771890 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2250771890 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2250771890 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2250771890 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45188 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45188 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25023 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25023 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70211 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70211 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70211 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70211 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811322 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.811322 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953163 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953163 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861873 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861873 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861873 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861873 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 32580.467896 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 32580.467896 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 44287.735357 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 44287.735357 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 37194.848875 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 37194.848875 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 37194.848875 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 37194.848875 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1130263 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.167313 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.767905 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.767905 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 339546 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 339546 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8879 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8879 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1139 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1139 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 10018 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 10018 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 10018 # number of overall hits +system.cpu3.l1c.overall_hits::total 10018 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36721 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36721 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23927 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23927 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60648 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60648 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60648 # number of overall misses +system.cpu3.l1c.overall_misses::total 60648 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 620124867 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 620124867 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 683533364 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 683533364 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1303658231 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1303658231 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1303658231 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1303658231 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45600 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45600 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25066 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25066 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70666 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70666 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70666 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70666 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805285 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805285 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954560 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954560 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.858235 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.858235 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.858235 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.858235 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16887.472209 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16887.472209 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28567.449492 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 28567.449492 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21495.485935 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21495.485935 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21495.485935 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21495.485935 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 763846 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 56535 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61681 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 19.992270 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.383813 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9719 # number of writebacks -system.cpu3.l1c.writebacks::total 9719 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36662 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36662 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23851 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60513 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60513 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60513 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60513 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9988 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5458 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15446 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15446 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1157803114 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1157803114 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1032457776 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1032457776 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2190260890 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2190260890 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2190260890 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2190260890 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 807637161 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 807637161 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1532365329 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1532365329 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2340002490 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2340002490 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811322 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811322 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953163 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953163 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861873 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861873 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 31580.467896 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 31580.467896 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 43287.819211 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 43287.819211 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 80860.748999 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80860.748999 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 280755.831623 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 280755.831623 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 151495.694031 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 151495.694031 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 10011 # number of writebacks +system.cpu3.l1c.writebacks::total 10011 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36721 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36721 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23927 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23927 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60648 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60648 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9730 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9730 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5269 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5269 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 14999 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 14999 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 583406867 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 583406867 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 659607364 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 659607364 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243014231 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1243014231 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243014231 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1243014231 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639132205 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639132205 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 818596366 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 818596366 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1457728571 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1457728571 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805285 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805285 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954560 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954560 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.858235 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.858235 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15887.553906 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15887.553906 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27567.491286 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27567.491286 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65686.763104 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65686.763104 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155360.858987 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155360.858987 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97188.383959 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97188.383959 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99531 # number of read accesses completed -system.cpu4.num_writes 55217 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22414 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.784167 # Cycle average of tags in use +system.cpu4.num_reads 98810 # number of read accesses completed +system.cpu4.num_writes 55636 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22565 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.118080 # Cycle average of tags in use system.cpu4.l1c.tags.total_refs 13493 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22803 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.591720 # Average number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22961 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587649 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.784167 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.769110 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.769110 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 47 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337660 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337660 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8661 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8661 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1197 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1197 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9858 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9858 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9858 # number of overall hits -system.cpu4.l1c.overall_hits::total 9858 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36381 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36381 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24008 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24008 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60389 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60389 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60389 # number of overall misses -system.cpu4.l1c.overall_misses::total 60389 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1185615268 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1185615268 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1062060825 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1062060825 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2247676093 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2247676093 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2247676093 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2247676093 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45042 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45042 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25205 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25205 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70247 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70247 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70247 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70247 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807713 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952509 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952509 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859667 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859667 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859667 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859667 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 32588.858690 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 32588.858690 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 44237.788446 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 44237.788446 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 37219.958817 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 37219.958817 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 37219.958817 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 37219.958817 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1133314 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 393.118080 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.767809 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.767809 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338158 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338158 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8694 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8694 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9864 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9864 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9864 # number of overall hits +system.cpu4.l1c.overall_hits::total 9864 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36355 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36355 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24124 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24124 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60479 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60479 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60479 # number of overall misses +system.cpu4.l1c.overall_misses::total 60479 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 612629802 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 612629802 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 686589261 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 686589261 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1299219063 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1299219063 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1299219063 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1299219063 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25294 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25294 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70343 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70343 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70343 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70343 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807010 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807010 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953744 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953744 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859773 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859773 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859773 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859773 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16851.321744 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16851.321744 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28460.838211 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 28460.838211 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21482.151871 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21482.151871 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21482.151871 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21482.151871 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 755009 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 56676 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61034 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 19.996365 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.370302 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9784 # number of writebacks -system.cpu4.l1c.writebacks::total 9784 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36381 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36381 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24008 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24008 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60389 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60389 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60389 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60389 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 10053 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15517 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1149238268 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1149238268 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1038052825 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1038052825 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2187291093 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2187291093 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2187291093 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2187291093 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 813079130 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 813079130 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1517158795 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1517158795 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2330237925 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2330237925 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807713 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952509 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952509 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859667 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859667 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 31588.968637 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 31588.968637 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 43237.788446 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 43237.788446 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 80879.252959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80879.252959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 277664.493960 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 277664.493960 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 150173.224528 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 150173.224528 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 10039 # number of writebacks +system.cpu4.l1c.writebacks::total 10039 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36355 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36355 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24124 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60479 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60479 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60479 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60479 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9580 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9580 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5521 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5521 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15101 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15101 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 576274802 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 576274802 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 662467261 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 662467261 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1238742063 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1238742063 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1238742063 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1238742063 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 630980804 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 630980804 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 867176198 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 867176198 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1498157002 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1498157002 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807010 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807010 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953744 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953744 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859773 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859773 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15851.321744 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15851.321744 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27460.921116 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27460.921116 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65864.384551 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65864.384551 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157068.682847 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157068.682847 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 99209.125356 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 99209.125356 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 55296 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22532 # number of replacements -system.cpu5.l1c.tags.tagsinuse 395.145821 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13497 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22906 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.589234 # Average number of references to valid blocks. +system.cpu5.num_reads 98552 # number of read accesses completed +system.cpu5.num_writes 54926 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22151 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.121942 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13428 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22535 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.595873 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 395.145821 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.771769 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.771769 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337979 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337979 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8739 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8739 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1202 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1202 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9941 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9941 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9941 # number of overall hits -system.cpu5.l1c.overall_hits::total 9941 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36450 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36450 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23918 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23918 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60368 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60368 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60368 # number of overall misses -system.cpu5.l1c.overall_misses::total 60368 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1193062548 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1193062548 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1058341769 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1058341769 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2251404317 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2251404317 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2251404317 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2251404317 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45189 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45189 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25120 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25120 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70309 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70309 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70309 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70309 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806612 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806612 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952150 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952150 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858610 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858610 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858610 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858610 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 32731.482798 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 32731.482798 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 44248.756961 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 44248.756961 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 37294.664673 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 37294.664673 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 37294.664673 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 37294.664673 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1121436 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 392.121942 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.765863 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.765863 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 336693 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 336693 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8529 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8529 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1201 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1201 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9730 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9730 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9730 # number of overall hits +system.cpu5.l1c.overall_hits::total 9730 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36363 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36363 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23944 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23944 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60307 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60307 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60307 # number of overall misses +system.cpu5.l1c.overall_misses::total 60307 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 609487073 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 609487073 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 677626855 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 677626855 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1287113928 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1287113928 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1287113928 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1287113928 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44892 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44892 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25145 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25145 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70037 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70037 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70037 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70037 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.810011 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.810011 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952237 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952237 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.861073 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.861073 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.861073 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.861073 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16761.187828 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16761.187828 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28300.486761 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 28300.486761 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21342.695342 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21342.695342 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21342.695342 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21342.695342 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 765746 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 56172 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61759 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 19.964324 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.398938 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9981 # number of writebacks -system.cpu5.l1c.writebacks::total 9981 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36450 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36450 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23918 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60368 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60368 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9842 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9842 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5587 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5587 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15429 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15429 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1156614548 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1156614548 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1034424769 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1034424769 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2191039317 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2191039317 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2191039317 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2191039317 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 798681353 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 798681353 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1559836698 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1559836698 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2358518051 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2358518051 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806612 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806612 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952150 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952150 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858610 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858610 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 31731.537668 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 31731.537668 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 43248.798771 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 43248.798771 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 81150.310201 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81150.310201 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 279190.388044 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279190.388044 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 152862.664528 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 152862.664528 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9825 # number of writebacks +system.cpu5.l1c.writebacks::total 9825 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36363 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36363 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23944 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60307 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60307 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60307 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60307 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9974 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9974 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5505 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5505 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15479 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15479 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 573124073 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 573124073 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 653684855 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 653684855 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1226808928 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1226808928 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1226808928 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1226808928 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 653819057 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 653819057 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 856353181 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 856353181 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1510172238 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1510172238 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.810011 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.810011 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952237 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952237 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.861073 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.861073 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15761.187828 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15761.187828 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27300.570289 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27300.570289 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65552.341789 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65552.341789 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 155559.160945 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155559.160945 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 97562.648621 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 97562.648621 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99879 # number of read accesses completed -system.cpu6.num_writes 55426 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22371 # number of replacements -system.cpu6.l1c.tags.tagsinuse 395.326557 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13543 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22792 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.594200 # Average number of references to valid blocks. +system.cpu6.num_reads 98949 # number of read accesses completed +system.cpu6.num_writes 55414 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22111 # number of replacements +system.cpu6.l1c.tags.tagsinuse 389.931977 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13393 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22506 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.595086 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 395.326557 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.772122 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.772122 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 339285 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 339285 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8751 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8751 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1170 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9921 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9921 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9921 # number of overall hits -system.cpu6.l1c.overall_hits::total 9921 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36633 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36633 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24021 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24021 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60654 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60654 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60654 # number of overall misses -system.cpu6.l1c.overall_misses::total 60654 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1194061806 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1194061806 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1068136243 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1068136243 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2262198049 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2262198049 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2262198049 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2262198049 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45384 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45384 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25191 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25191 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70575 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70575 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70575 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70575 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807179 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807179 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953555 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953555 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859426 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859426 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859426 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859426 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 32595.250348 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 32595.250348 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 44466.768369 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 44466.768369 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 37296.766067 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 37296.766067 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 37296.766067 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 37296.766067 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1121671 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 389.931977 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.761586 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.761586 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337246 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337246 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8611 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8611 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9755 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9755 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9755 # number of overall hits +system.cpu6.l1c.overall_hits::total 9755 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36346 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36346 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24035 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24035 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60381 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60381 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60381 # number of overall misses +system.cpu6.l1c.overall_misses::total 60381 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 607533641 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 607533641 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 684112648 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 684112648 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1291646289 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1291646289 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1291646289 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1291646289 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44957 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44957 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25179 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25179 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70136 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70136 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70136 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70136 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808461 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808461 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954565 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954565 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.860913 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.860913 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.860913 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.860913 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16715.282039 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16715.282039 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28463.184855 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 28463.184855 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21391.601481 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21391.601481 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21391.601481 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21391.601481 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 766078 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 56232 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61691 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 19.947201 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.417986 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9808 # number of writebacks -system.cpu6.l1c.writebacks::total 9808 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36633 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36633 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24021 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24021 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60654 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60654 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60654 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60654 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9734 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15253 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1157429806 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1157429806 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1044117243 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1044117243 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2201547049 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2201547049 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2201547049 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2201547049 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 789209928 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 789209928 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1545234814 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1545234814 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2334444742 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2334444742 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807179 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807179 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953555 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953555 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859426 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859426 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 31595.277646 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 31595.277646 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 43466.851630 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 43466.851630 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 81077.658517 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81077.658517 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 279984.564957 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279984.564957 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 153048.235888 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 153048.235888 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9648 # number of writebacks +system.cpu6.l1c.writebacks::total 9648 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36346 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36346 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24035 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24035 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60381 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60381 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60381 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60381 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5478 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5478 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15382 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15382 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 571188641 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 571188641 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 660079648 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 660079648 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1231268289 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1231268289 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1231268289 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1231268289 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 650717068 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 650717068 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 843701696 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 843701696 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1494418764 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494418764 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808461 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808461 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954565 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954565 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.860913 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.860913 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15715.309553 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15715.309553 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27463.268067 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27463.268067 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65702.450323 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65702.450323 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154016.373859 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154016.373859 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97153.735795 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97153.735795 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99237 # number of read accesses completed -system.cpu7.num_writes 54706 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22568 # number of replacements -system.cpu7.l1c.tags.tagsinuse 396.130968 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13545 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22967 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.589759 # Average number of references to valid blocks. +system.cpu7.num_reads 99388 # number of read accesses completed +system.cpu7.num_writes 55153 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22255 # number of replacements +system.cpu7.l1c.tags.tagsinuse 390.416736 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13442 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22659 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.593230 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 396.130968 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.773693 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.773693 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 336 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337631 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337631 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8763 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8763 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1110 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1110 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9873 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9873 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9873 # number of overall hits -system.cpu7.l1c.overall_hits::total 9873 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36422 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36422 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23951 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23951 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60373 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60373 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60373 # number of overall misses -system.cpu7.l1c.overall_misses::total 60373 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1187262746 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1187262746 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1066556279 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1066556279 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2253819025 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2253819025 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2253819025 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2253819025 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45185 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45185 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25061 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70246 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70246 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70246 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70246 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806064 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806064 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955708 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955708 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859451 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859451 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859451 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859451 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 32597.406677 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 32597.406677 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 44530.761931 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 44530.761931 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 37331.572474 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 37331.572474 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 37331.572474 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 37331.572474 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1126172 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 390.416736 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.762533 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.762533 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338136 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338136 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8702 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8702 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1125 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1125 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9827 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9827 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9827 # number of overall hits +system.cpu7.l1c.overall_hits::total 9827 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36623 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36623 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23879 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23879 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60502 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60502 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60502 # number of overall misses +system.cpu7.l1c.overall_misses::total 60502 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 619428018 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 619428018 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 681256931 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 681256931 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1300684949 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1300684949 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1300684949 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1300684949 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45325 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45325 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25004 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25004 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70329 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70329 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70329 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70329 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808009 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.808009 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955007 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955007 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.860271 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.860271 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.860271 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.860271 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16913.634000 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16913.634000 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28529.541899 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 28529.541899 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21498.214092 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21498.214092 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21498.214092 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21498.214092 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 764751 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 56351 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61551 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 19.984951 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.424672 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9950 # number of writebacks -system.cpu7.l1c.writebacks::total 9950 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36422 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36422 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23951 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23951 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60373 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60373 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60373 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60373 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9901 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9901 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5444 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5444 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15345 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15345 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1150841746 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1150841746 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1042608279 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1042608279 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2193450025 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2193450025 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2193450025 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2193450025 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 802753372 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 802753372 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1502766880 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1502766880 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2305520252 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2305520252 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806064 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806064 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955708 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955708 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859451 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859451 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859451 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 31597.434133 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 31597.434133 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 43530.887186 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 43530.887186 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 81078.009494 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81078.009494 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 276040.940485 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 276040.940485 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 150245.699055 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 150245.699055 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9698 # number of writebacks +system.cpu7.l1c.writebacks::total 9698 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36623 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36623 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23879 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23879 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60502 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60502 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60502 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60502 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9744 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5445 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5445 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15189 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15189 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 582807018 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 582807018 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 657378931 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 657378931 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1240185949 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1240185949 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1240185949 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1240185949 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639625650 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639625650 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 835380703 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 835380703 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1475006353 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1475006353 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808009 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808009 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955007 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955007 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.860271 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860271 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.860271 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15913.688611 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15913.688611 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27529.583777 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27529.583777 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20498.263677 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65643.026478 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65643.026478 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 153421.616713 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153421.616713 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 97110.168741 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 97110.168741 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13238 # number of replacements -system.l2c.tags.tagsinuse 783.486176 # Cycle average of tags in use -system.l2c.tags.total_refs 163749 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14027 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.673843 # Average number of references to valid blocks. +system.l2c.tags.replacements 14059 # number of replacements +system.l2c.tags.tagsinuse 786.833616 # Cycle average of tags in use +system.l2c.tags.total_refs 163279 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14835 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.006336 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 731.907933 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.423018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.356158 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.459637 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.505664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.498026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.297131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.613319 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.425290 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.714754 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006272 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006308 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006353 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006275 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.765123 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.770508 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2093442 # Number of tag accesses -system.l2c.tags.data_accesses 2093442 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77141 # number of Writeback hits -system.l2c.Writeback_hits::total 77141 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 278 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 288 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 234 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 250 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 237 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 267 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 288 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 265 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2107 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1745 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1822 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1757 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1774 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1783 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1866 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1759 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1730 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14236 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10764 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10818 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10858 # 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number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2011 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2018 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16379 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4713 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4655 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4607 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4594 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu4 4660 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4681 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4704 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4691 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37198 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 682 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 677 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 701 # 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number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 61770000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 60743499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 60997499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 60764000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 494388493 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 252681459 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 247510963 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 255306957 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 251987957 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 254124963 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 254900472 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 257627958 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 256511954 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2030652683 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 41112446 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 40920945 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 42356442 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 41376937 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 44597922 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 42076925 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 42377442 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 41033442 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 335852501 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 293793905 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 288431908 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 297663399 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 293364894 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 298722885 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 296977397 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 300005400 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 297545396 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2366505184 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 293793905 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 288431908 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 297663399 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 293364894 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2319 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2356 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2325 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18688 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6380 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6433 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6391 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6443 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6547 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6463 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6421 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51434 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11446 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11495 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11559 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11535 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11447 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11497 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11486 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11393 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 91858 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17826 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17851 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17992 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17926 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17890 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18044 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17949 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17814 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143292 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17826 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17851 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17992 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17926 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17890 # 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miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.887254 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.726489 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.713342 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.726877 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.722422 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.723266 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.714984 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.727835 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.730572 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.723218 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.059584 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.058895 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.060645 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.059211 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.063947 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.059320 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.061640 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.060037 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.060408 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.298272 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.291916 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.298855 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.295660 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.301397 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.297218 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.301521 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.301729 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.298321 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.298272 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.291916 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.298855 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.295660 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.301397 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.297218 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.301521 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.301729 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.298321 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29972.358121 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 30263.732620 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 30704.012422 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29711.153003 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29288.762447 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29602.095029 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29495.889265 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29497.087379 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29816.566733 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 54515.956634 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 54589.978606 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 54599.434773 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54578.288282 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 54533.253863 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54454.277291 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 54767.848214 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54681.721168 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54590.372681 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 60282.178886 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 60444.527326 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 60422.884451 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 60581.166911 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 60926.122951 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61696.370968 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 59855.144068 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 59990.412281 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 60524.869526 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55255.577393 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55350.586836 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55358.638460 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55351.866792 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55401.128524 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55375.237181 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55433.370288 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55357.282977 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55360.731373 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55255.577393 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55350.586836 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55358.638460 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55351.866792 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55401.128524 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55375.237181 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55433.370288 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55357.282977 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55360.731373 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 8992 # number of cycles access was blocked +system.l2c.ReadExReq_misses::cpu5 4574 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4699 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4645 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37147 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 745 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 703 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 745 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 740 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 719 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 741 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 735 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 779 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5907 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5458 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5358 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5352 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5334 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5379 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5315 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5434 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5424 # number of demand (read+write) misses +system.l2c.demand_misses::total 43054 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5458 # number of overall misses +system.l2c.overall_misses::cpu1 5358 # number of overall misses +system.l2c.overall_misses::cpu2 5352 # number of overall misses +system.l2c.overall_misses::cpu3 5334 # number of overall misses +system.l2c.overall_misses::cpu4 5379 # number of overall misses +system.l2c.overall_misses::cpu5 5315 # number of overall misses +system.l2c.overall_misses::cpu6 5434 # number of overall misses +system.l2c.overall_misses::cpu7 5424 # number of overall misses +system.l2c.overall_misses::total 43054 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 60264491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 62631489 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 64255988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 63421482 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 62636494 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 62720987 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 60083486 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 62493486 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 498507903 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 264922404 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 260661407 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 257895914 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 258059392 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 261142926 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 256126416 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 263147923 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 259849424 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2081805806 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 46156062 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 44483916 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 46780409 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 45792918 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 45003906 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 46499399 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 45597417 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 48662406 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 368976433 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 311078466 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 305145323 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 304676323 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 303852310 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 306146832 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 302625815 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 308745340 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 308511830 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2450782239 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 311078466 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 305145323 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 304676323 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 303852310 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 306146832 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 302625815 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 308745340 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 308511830 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2450782239 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 77297 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77297 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2224 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2294 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2420 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2374 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2323 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2353 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2280 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2315 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18583 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6433 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6363 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6387 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6344 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6493 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6361 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6492 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6401 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51274 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11466 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11436 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11641 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11763 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11475 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11510 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11291 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11679 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92261 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17899 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17799 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18028 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18107 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17968 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17871 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17783 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18080 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143535 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17899 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17799 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18028 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18107 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17968 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17871 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17783 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18080 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143535 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.889388 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.883173 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.888430 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.880792 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.875592 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.880153 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.882018 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.871706 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.881397 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.732629 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.731573 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.721309 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.724149 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.717696 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.719069 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.723814 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.725668 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.724480 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.064975 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.061473 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.063998 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.062909 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.062658 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.064379 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.065096 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.066701 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.064025 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.304933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.301028 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.296872 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.294582 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.299366 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.297409 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.305573 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.300000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.299955 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.304933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.301028 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.296872 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.294582 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.299366 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.297409 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.305573 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.300000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.299955 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30467.386754 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 30913.864265 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29886.506047 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 30330.694405 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 30794.736480 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 30285.363110 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 29877.417205 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 30968.030723 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 30435.796019 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 56210.991725 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55996.005800 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55979.143477 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 56173.137135 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 56039.254506 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 55996.155662 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 56000.834858 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55941.748977 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 56042.366974 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61954.445638 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 63277.263158 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62792.495302 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61882.321622 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 62592.358832 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62752.225371 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62037.302041 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62467.786906 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 62464.268326 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56994.955295 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56951.348078 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56927.564088 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 56965.187477 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 56915.194646 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 56938.064911 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56817.324255 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 56879.024705 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 56923.450527 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56994.955295 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56951.348078 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56927.564088 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 56965.187477 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 56915.194646 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 56938.064911 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56817.324255 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 56879.024705 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 56923.450527 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 19361 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1204 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3488 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.468439 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.550745 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6188 # number of writebacks -system.l2c.writebacks::total 6188 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 6515 # number of writebacks +system.l2c.writebacks::total 6515 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 5 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 26 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 12 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 6 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 6 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 46 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1198 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1198 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2044 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2057 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2093 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2098 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2109 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2051 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2068 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2059 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16579 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4627 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4532 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4674 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4616 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4656 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4680 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4700 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4687 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37172 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 678 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 673 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 700 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 679 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 720 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 673 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 702 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 678 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5503 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5305 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5205 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5374 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5295 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5376 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5353 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5402 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5365 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42675 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5305 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5205 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5374 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5295 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5376 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5353 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5402 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5365 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42675 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9717 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9883 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9842 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9901 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78862 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5354 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5486 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5463 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5457 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5585 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5444 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43772 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15071 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15230 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15346 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15445 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15427 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15345 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122634 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 89873000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 90484998 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 92033997 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 92268499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 92811998 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 90292999 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 90927999 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 90564000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 729257490 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 206241460 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 202149464 # 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number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 103 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 1301 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 1301 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1977 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2026 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2150 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2090 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 2034 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2069 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 2011 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 2017 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 16374 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4709 # 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number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu5 731 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu6 730 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu7 770 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 5838 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5447 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5343 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5339 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5323 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5364 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5301 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5425 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5409 # 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number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5477 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5442 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43469 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15178 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15268 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15368 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 14998 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15101 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15479 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15381 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15186 # 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number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 38163918 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 37564408 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 38848899 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 38077918 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 40630907 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 308121940 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 256276966 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 251314824 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 250772825 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 250224810 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 437879200 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3531476593 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 247492955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 251693437 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 254031943 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 244392771 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 255999435 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 255282926 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 253764437 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 253334431 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2015992335 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 689037659 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 694515799 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 699146134 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 682435479 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 687551804 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 703842791 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 699725631 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 691213631 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5547468928 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880276 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877186 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.899441 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.893526 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.898977 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.884433 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.877759 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.885591 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.887147 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725235 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713027 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726566 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.722266 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.722645 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.714831 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.727216 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.729949 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.722713 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059235 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.058547 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.060559 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.058864 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.062899 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.058537 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061118 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.059510 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059908 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.297599 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.291580 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.298688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.295381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.300503 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.296664 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.300964 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.301168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297818 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.297599 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.291580 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.298688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.295381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.300503 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.296664 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.300964 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.301168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297818 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 43969.178082 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 43988.817696 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 43972.287148 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 43979.265491 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44007.585586 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44023.890297 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 43969.051741 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 43984.458475 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43986.820074 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44573.473093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44604.912621 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44600.868207 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44580.796577 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44544.665808 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44462.600855 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44780.204043 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44713.559633 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44607.895405 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 50505.820059 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 50619.531947 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 50442.060000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 50725.974963 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51454.061111 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52219.799406 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 50096.783476 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 50259.501475 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50789.933309 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44221.156633 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44202.582307 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44181.167156 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44181.716159 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44166.713618 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44121.720992 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44175.413191 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44200.616200 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44181.280211 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45634.662682 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45295.386256 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45128.316493 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45396.736119 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45350.016654 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45451.832050 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45361.385758 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45227.220610 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45355.293452 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44723.307213 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44596.221339 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44518.341457 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44611.004856 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44583.390024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44603.257924 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44604.534190 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44564.828283 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 44600.323116 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.888939 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883173 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.888430 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.880371 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.875592 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.879303 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.882018 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871274 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.881128 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.732007 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.730787 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.720839 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723676 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716926 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.718440 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723198 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724731 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.723817 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.064364 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060598 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063139 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062229 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061786 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.063510 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064653 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065930 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063277 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.299237 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.299237 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 45450.420840 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 45460.256170 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 45384.873953 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 45421.041148 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 45371.430678 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 45448.514258 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 45378.159125 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 45405.790778 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45414.855258 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 46229.221491 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46032.345591 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 46000.198523 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 46190.566761 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 46073.560902 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46021.316411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 46020.856869 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45971.206079 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 46067.626088 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52281.249322 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 53772.607504 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 53044.776871 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52136.500000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 52982.239774 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 53144.868673 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52161.531507 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52767.411688 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52778.681055 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44927.218559 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 45002.272561 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 45006.490495 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 45019.805550 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 45047.220146 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44972.916082 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 45028.391963 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44938.341544 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44992.694522 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 46260.365421 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46369.461496 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 46373.118474 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 46391.945900 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 46368.309183 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46372.920254 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46332.743655 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46551.714627 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 46377.702156 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 45397.131308 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45488.328465 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 45493.631832 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 45501.765502 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 45530.216807 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45470.817947 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45492.856836 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45516.504083 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 45486.343181 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 253876 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 250804 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 127987 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 121935 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 78861 # Transaction distribution -system.membus.trans_dist::ReadResp 84355 # Transaction distribution -system.membus.trans_dist::WriteReq 43772 # Transaction distribution -system.membus.trans_dist::WriteResp 43770 # Transaction distribution -system.membus.trans_dist::Writeback 6188 # Transaction distribution -system.membus.trans_dist::CleanEvict 1234 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61487 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50676 # Transaction distribution -system.membus.trans_dist::ReadExReq 49401 # Transaction distribution -system.membus.trans_dist::ReadExResp 3090 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5496 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 428330 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1068167 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1068167 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57121 # Total snoops (count) -system.membus.snoop_fanout::samples 253876 # Request fanout histogram +system.membus.trans_dist::ReadReq 78487 # Transaction distribution +system.membus.trans_dist::ReadResp 84311 # Transaction distribution +system.membus.trans_dist::WriteReq 43469 # Transaction distribution +system.membus.trans_dist::WriteResp 43465 # Transaction distribution +system.membus.trans_dist::Writeback 6515 # Transaction distribution +system.membus.trans_dist::CleanEvict 1324 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61199 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50308 # Transaction distribution +system.membus.trans_dist::ReadExReq 49356 # Transaction distribution +system.membus.trans_dist::ReadExResp 3201 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5828 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427463 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 427463 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1116768 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1116768 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57043 # Total snoops (count) +system.membus.snoop_fanout::samples 255514 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253876 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 255514 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253876 # Request fanout histogram -system.membus.reqLayer0.occupancy 481009549 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 54.1 # Layer utilization (%) -system.membus.respLayer0.occupancy 317350499 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 35.7 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 783985 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 389410 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 391503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 13238 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 4575 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 8663 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78862 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371257 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43772 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43769 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83329 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20018 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29498 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29497 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162169 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162167 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292402 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122283 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122863 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122791 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122959 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122669 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122503 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 981417 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781215 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778494 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776817 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1770963 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1771805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1794946 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778453 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1777585 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14230278 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_fanout::total 255514 # Request fanout histogram +system.membus.reqLayer0.occupancy 292277246 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 56.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 310111858 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 59.8 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663155 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 282754 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 334620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12643 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 6068 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6575 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78490 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370569 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43469 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43464 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 83812 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20730 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29471 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29469 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161822 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161815 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292094 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122083 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122289 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122819 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122567 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122495 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122827 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122446 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 979883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1778056 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1772835 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781127 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1803862 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1797691 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1778038 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1761236 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1781905 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14254750 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 335326 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 797223 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.523507 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.320965 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 800967 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.187618 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.006332 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 184121 23.10% 23.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 277567 34.82% 57.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 172653 21.66% 79.57% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 93165 11.69% 91.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 44731 5.61% 96.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 17914 2.25% 99.11% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 5826 0.73% 99.84% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 1211 0.15% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 35 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 216572 27.04% 27.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 322054 40.21% 67.25% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 178446 22.28% 89.53% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 65924 8.23% 97.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 15526 1.94% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2251 0.28% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 192 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 797223 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 882991225 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 99.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100686388 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100571959 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 100903359 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 11.4 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100786975 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100705827 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100586898 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 100884775 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 11.3 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100465612 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 11.3 # Layer utilization (%) +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 800967 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 495267856 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.5 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101287347 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101004376 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101361922 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101351771 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101153250 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101246693 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101297808 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101337760 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index d439f20bd..76540bca6 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1806 +1,1811 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000517 # Number of seconds simulated -sim_ticks 516502000 # Number of ticks simulated -final_tick 516502000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000518 # Number of seconds simulated +sim_ticks 517786000 # Number of ticks simulated +final_tick 517786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 87177041 # Simulator tick rate (ticks/s) -host_mem_usage 277532 # Number of bytes of host memory used -host_seconds 5.92 # Real time elapsed on the host +host_tick_rate 99723528 # Simulator tick rate (ticks/s) +host_mem_usage 280036 # Number of bytes of host memory used +host_seconds 5.19 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 77818 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 80958 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 77616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 81564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 77320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77018 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 77760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78103 # Number of bytes read from this memory -system.physmem.bytes_read::total 628157 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 397760 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5585 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5520 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5375 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5451 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5416 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5446 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5475 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5563 # Number of bytes written to this memory -system.physmem.bytes_written::total 441591 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10975 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10902 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11130 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10918 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10679 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10819 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87365 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6215 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5585 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5520 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5375 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5416 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5446 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5475 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5563 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50046 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 150663502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 156742859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 150272409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 157916136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 149699324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 149114621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 150551208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 151215291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1216175349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 770103504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10813124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10687277 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10406542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10553686 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10485923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10544006 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10600153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10770529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 854964744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 770103504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 161476625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 167430136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 160678952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 168469822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 160185246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 159658627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 161151360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 161985820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2071140092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 82733 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82298 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 83808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 81707 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79210 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 80419 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 83957 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 82578 # Number of bytes read from this memory +system.physmem.bytes_read::total 656710 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 415488 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5449 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5329 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5533 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5454 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5382 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5483 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5404 # Number of bytes written to this memory +system.physmem.bytes_written::total 459030 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10913 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10856 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10917 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10895 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11003 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10884 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87442 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6492 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5449 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5329 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5533 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5454 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5382 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5483 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5404 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50034 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 159782227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 158942111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 161858374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 157800713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 152978257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 155313199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 162146138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 159482875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1268303894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 802431893 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10523653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10291897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10685882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10533309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10394256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10589317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10637599 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10436744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 886524549 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 802431893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 170305879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 169234008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 172544256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 168334022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 163372513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 165902516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 172783737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 169919619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2154828443 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99458 # number of read accesses completed -system.cpu0.num_writes 55230 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22190 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.694293 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13468 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22585 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596325 # Average number of references to valid blocks. +system.cpu0.num_reads 99592 # number of read accesses completed +system.cpu0.num_writes 55369 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22465 # number of replacements +system.cpu0.l1c.tags.tagsinuse 392.038302 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13410 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.586768 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.694293 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.765028 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.765028 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337088 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337088 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1212 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1212 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9897 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9897 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9897 # number of overall hits -system.cpu0.l1c.overall_hits::total 9897 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36327 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36327 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23903 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23903 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60230 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60230 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60230 # number of overall misses -system.cpu0.l1c.overall_misses::total 60230 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 590238894 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 590238894 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 671544552 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 671544552 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1261783446 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1261783446 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1261783446 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1261783446 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45012 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45012 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25115 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25115 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70127 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70127 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70127 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70127 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807051 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807051 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951742 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.951742 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858870 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858870 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858870 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858870 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16247.939384 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16247.939384 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28094.571895 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 28094.571895 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20949.417998 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20949.417998 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20949.417998 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20949.417998 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 738586 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 392.038302 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765700 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765700 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338870 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338870 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8751 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9899 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9899 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9899 # number of overall hits +system.cpu0.l1c.overall_hits::total 9899 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36676 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36676 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23894 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23894 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60570 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60570 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60570 # number of overall misses +system.cpu0.l1c.overall_misses::total 60570 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 605837577 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 605837577 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 675142476 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 675142476 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1280980053 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1280980053 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1280980053 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1280980053 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45427 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45427 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25042 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25042 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70469 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70469 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70469 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70469 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807361 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807361 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954157 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954157 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859527 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859527 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859527 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859527 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16518.638265 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16518.638265 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28255.732653 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 28255.732653 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21148.754383 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21148.754383 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21148.754383 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21148.754383 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 743435 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 60679 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61083 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.172020 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.170899 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu0.l1c.writebacks::total 9780 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36327 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23903 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23903 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60230 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60230 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60230 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60230 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9914 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9914 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5586 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5586 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15500 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15500 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 553912894 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 553912894 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 647643552 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 647643552 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1201556446 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1201556446 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1201556446 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1201556446 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 648458134 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 648458134 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 875575663 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 875575663 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1524033797 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1524033797 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807051 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807051 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951742 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951742 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858870 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858870 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858870 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858870 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15247.966912 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15247.966912 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27094.655566 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27094.655566 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19949.467807 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65408.324995 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65408.324995 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 156744.658611 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156744.658611 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 98324.761097 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 98324.761097 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9922 # number of writebacks +system.cpu0.l1c.writebacks::total 9922 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36676 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23894 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23894 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60570 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60570 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60570 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60570 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9773 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5450 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5450 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15223 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15223 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 569161577 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 569161577 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 651248476 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 651248476 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1220410053 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1220410053 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1220410053 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1220410053 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 638102868 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 638102868 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 843396249 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 843396249 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1481499117 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1481499117 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807361 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807361 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954157 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954157 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859527 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859527 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15518.638265 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15518.638265 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27255.732653 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27255.732653 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65292.424844 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65292.424844 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 154751.605321 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154751.605321 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 97319.786967 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 97319.786967 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99343 # number of read accesses completed -system.cpu1.num_writes 54840 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22376 # number of replacements -system.cpu1.l1c.tags.tagsinuse 393.102021 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13319 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.585142 # Average number of references to valid blocks. +system.cpu1.num_reads 99505 # number of read accesses completed +system.cpu1.num_writes 55135 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22526 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.510444 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13408 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22912 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.585196 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 393.102021 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.767777 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.767777 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_blocks::cpu1 393.510444 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.768575 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.768575 # Average percentage of cache occupancy system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 337670 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 337670 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8618 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8618 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1175 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1175 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9793 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9793 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9793 # number of overall hits -system.cpu1.l1c.overall_hits::total 9793 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36716 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36716 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23707 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23707 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60423 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60423 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60423 # number of overall misses -system.cpu1.l1c.overall_misses::total 60423 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 601446212 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 601446212 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 664813201 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 664813201 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1266259413 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1266259413 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1266259413 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1266259413 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45334 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45334 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24882 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24882 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70216 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70216 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70216 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70216 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809900 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.809900 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.952777 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.952777 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860530 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860530 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860530 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860530 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16381.038566 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16381.038566 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28042.907200 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 28042.907200 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20956.579663 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20956.579663 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20956.579663 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20956.579663 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 733404 # number of cycles access was blocked +system.cpu1.l1c.tags.tag_accesses 339206 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 339206 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8687 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8687 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1167 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1167 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9854 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9854 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9854 # number of overall hits +system.cpu1.l1c.overall_hits::total 9854 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36759 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36759 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23925 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23925 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60684 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60684 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60684 # number of overall misses +system.cpu1.l1c.overall_misses::total 60684 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 611192958 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 611192958 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 677073428 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 677073428 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1288266386 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1288266386 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1288266386 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1288266386 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45446 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45446 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25092 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25092 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70538 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70538 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70538 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70538 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808850 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.808850 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953491 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953491 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860302 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860302 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860302 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860302 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16627.028972 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16627.028972 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28299.829801 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 28299.829801 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21229.094753 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21229.094753 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21229.094753 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21229.094753 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 746931 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 60457 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.131002 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.193000 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9757 # number of writebacks -system.cpu1.l1c.writebacks::total 9757 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36716 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36716 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23707 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23707 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60423 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60423 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60423 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60423 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9790 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9790 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5520 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5520 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15310 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15310 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 564731212 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 564731212 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 641108201 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 641108201 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1205839413 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1205839413 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1205839413 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1205839413 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 639869720 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 639869720 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 879270140 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 879270140 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1519139860 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1519139860 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809900 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809900 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.952777 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.952777 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860530 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860530 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860530 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860530 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15381.065802 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15381.065802 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27042.991564 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27042.991564 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19956.629313 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65359.521961 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65359.521961 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159288.068841 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159288.068841 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 99225.333769 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 99225.333769 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9855 # number of writebacks +system.cpu1.l1c.writebacks::total 9855 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36759 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36759 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23925 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23925 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60684 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60684 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60684 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60684 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9724 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9724 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5329 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15053 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15053 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 574433958 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 574433958 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 653148428 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 653148428 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1227582386 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1227582386 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1227582386 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1227582386 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 636306689 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 636306689 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 841464320 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 841464320 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1477771009 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1477771009 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808850 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808850 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953491 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953491 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860302 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860302 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15627.028972 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15627.028972 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27299.829801 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27299.829801 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65436.722439 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65436.722439 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157902.856071 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157902.856071 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 98171.195708 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 98171.195708 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99555 # number of read accesses completed -system.cpu2.num_writes 54722 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22333 # number of replacements -system.cpu2.l1c.tags.tagsinuse 393.011664 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13583 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22742 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.597265 # Average number of references to valid blocks. +system.cpu2.num_reads 99747 # number of read accesses completed +system.cpu2.num_writes 54917 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22440 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.958774 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13419 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22848 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.587316 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 393.011664 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.767601 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.767601 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337922 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337922 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8790 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8790 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1177 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9967 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9967 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9967 # number of overall hits -system.cpu2.l1c.overall_hits::total 9967 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36445 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36445 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23901 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23901 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60346 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60346 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60346 # number of overall misses -system.cpu2.l1c.overall_misses::total 60346 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 601110816 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 601110816 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 668105531 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 668105531 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1269216347 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1269216347 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1269216347 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1269216347 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45235 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45235 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25078 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25078 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70313 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70313 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70313 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70313 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805681 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805681 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953066 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953066 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858248 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858248 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858248 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858248 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16493.642914 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16493.642914 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27953.036735 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 27953.036735 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21032.319408 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21032.319408 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21032.319408 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21032.319408 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 742378 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.958774 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.767498 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.767498 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337058 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337058 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8566 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8566 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1197 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1197 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9763 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9763 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9763 # number of overall hits +system.cpu2.l1c.overall_hits::total 9763 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36656 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36656 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23689 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23689 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses +system.cpu2.l1c.overall_misses::total 60345 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 609273651 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 609273651 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 671190571 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 671190571 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1280464222 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1280464222 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1280464222 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1280464222 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45222 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45222 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24886 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24886 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70108 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70108 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70108 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70108 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.810579 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.810579 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.951901 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.951901 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860743 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860743 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860743 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860743 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16621.389431 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16621.389431 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28333.427793 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 28333.427793 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21219.060767 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21219.060767 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21219.060767 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21219.060767 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 742867 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 60996 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 60931 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.170929 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.191938 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9726 # number of writebacks -system.cpu2.l1c.writebacks::total 9726 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36445 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36445 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23901 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23901 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60346 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60346 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60346 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60346 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9904 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5377 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5377 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15281 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15281 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 564666816 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 564666816 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 644204531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 644204531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1208871347 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1208871347 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1208871347 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1208871347 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 647672238 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 647672238 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 840893759 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 840893759 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1488565997 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1488565997 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805681 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805681 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953066 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953066 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858248 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858248 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858248 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858248 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15493.670353 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15493.670353 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26953.036735 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26953.036735 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20032.335979 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65395.015953 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65395.015953 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 156387.159940 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156387.159940 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97412.865454 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97412.865454 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9836 # number of writebacks +system.cpu2.l1c.writebacks::total 9836 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36656 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36656 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23689 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23689 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9760 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9760 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5535 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5535 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15295 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15295 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 572617651 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 572617651 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 647503571 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 647503571 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1220121222 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1220121222 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1220121222 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1220121222 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638440786 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638440786 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 853548639 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 853548639 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1491989425 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1491989425 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.810579 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.810579 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.951901 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.951901 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860743 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860743 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15621.389431 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15621.389431 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27333.512221 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27333.512221 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65414.014959 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65414.014959 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154209.329539 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154209.329539 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97547.526970 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97547.526970 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99759 # number of read accesses completed -system.cpu3.num_writes 54933 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22211 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.604025 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13361 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22604 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.591090 # Average number of references to valid blocks. +system.cpu3.num_reads 98987 # number of read accesses completed +system.cpu3.num_writes 55311 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22430 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.656254 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13364 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22840 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.585114 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.604025 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.764852 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.764852 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 336889 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 336889 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8685 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8685 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1067 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1067 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9752 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9752 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9752 # number of overall hits -system.cpu3.l1c.overall_hits::total 9752 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36549 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36549 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23764 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23764 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60313 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60313 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60313 # number of overall misses -system.cpu3.l1c.overall_misses::total 60313 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 596458593 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 596458593 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 667670467 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 667670467 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1264129060 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1264129060 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1264129060 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1264129060 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45234 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45234 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24831 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24831 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70065 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70065 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70065 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70065 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807998 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807998 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.957030 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.957030 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860815 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860815 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860815 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860815 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16319.423049 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16319.423049 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28095.878935 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 28095.878935 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20959.479051 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20959.479051 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20959.479051 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20959.479051 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 744732 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.656254 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.766907 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.766907 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337200 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337200 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8601 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8601 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1133 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1133 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9734 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9734 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9734 # number of overall hits +system.cpu3.l1c.overall_hits::total 9734 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36299 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36299 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 24092 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 24092 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60391 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60391 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60391 # number of overall misses +system.cpu3.l1c.overall_misses::total 60391 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 601442350 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 601442350 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 682370713 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 682370713 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1283813063 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1283813063 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1283813063 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1283813063 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44900 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44900 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25225 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25225 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70125 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70125 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70125 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70125 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808441 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808441 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955084 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955084 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861191 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861191 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861191 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861191 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16569.116229 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16569.116229 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28323.539474 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 28323.539474 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21258.350797 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21258.350797 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21258.350797 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21258.350797 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 746578 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61238 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 60969 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.161272 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.245207 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9780 # number of writebacks -system.cpu3.l1c.writebacks::total 9780 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36549 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36549 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23764 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23764 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60313 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60313 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60313 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60313 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 10012 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 10012 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.writebacks::writebacks 9891 # number of writebacks +system.cpu3.l1c.writebacks::total 9891 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36299 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36299 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24092 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 24092 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60391 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60391 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60391 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60391 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9771 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9771 # number of ReadReq MSHR uncacheable system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5455 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15467 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15467 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 559909593 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 559909593 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 643907467 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 643907467 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1203817060 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1203817060 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1203817060 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1203817060 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 654349566 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 654349566 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 848349724 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 848349724 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1502699290 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1502699290 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807998 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807998 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.957030 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.957030 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860815 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860815 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860815 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860815 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15319.423049 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15319.423049 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27095.921015 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27095.921015 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19959.495631 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65356.528765 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65356.528765 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155517.822915 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155517.822915 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97155.187819 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97155.187819 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15226 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15226 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 565143350 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 565143350 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 658281713 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 658281713 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1223425063 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1223425063 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1223425063 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1223425063 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 638944774 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 638944774 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 852450723 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 852450723 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1491395497 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1491395497 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808441 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955084 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955084 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861191 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861191 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15569.116229 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15569.116229 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27323.663996 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27323.663996 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65391.953127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65391.953127 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 156269.610082 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156269.610082 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97950.577762 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97950.577762 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 55127 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22421 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.948683 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13931 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22818 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.610527 # Average number of references to valid blocks. +system.cpu4.num_writes 54901 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22108 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.325245 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13548 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22499 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.602160 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.948683 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.767478 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.767478 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 339409 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 339409 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 9015 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 9015 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1217 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1217 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10232 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10232 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10232 # number of overall hits -system.cpu4.l1c.overall_hits::total 10232 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36534 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36534 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23911 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23911 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60445 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60445 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60445 # number of overall misses -system.cpu4.l1c.overall_misses::total 60445 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 594216920 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 594216920 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 670376038 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 670376038 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1264592958 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1264592958 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1264592958 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1264592958 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45549 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45549 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25128 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25128 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70677 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70677 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70677 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70677 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.802081 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.802081 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.951568 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.951568 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.855229 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.855229 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.855229 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.855229 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16264.764877 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16264.764877 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28036.302873 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 28036.302873 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20921.382381 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20921.382381 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20921.382381 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20921.382381 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 737141 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.325245 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.766260 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.766260 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338175 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338175 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8785 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8785 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1156 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1156 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9941 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9941 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9941 # number of overall hits +system.cpu4.l1c.overall_hits::total 9941 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36616 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36616 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23803 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23803 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60419 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60419 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60419 # number of overall misses +system.cpu4.l1c.overall_misses::total 60419 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 606172682 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 606172682 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 676089465 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 676089465 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1282262147 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1282262147 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1282262147 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1282262147 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45401 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45401 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24959 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70360 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70360 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806502 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.806502 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953684 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953684 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858712 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858712 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858712 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858712 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16554.858040 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16554.858040 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28403.540100 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 28403.540100 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21222.829689 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21222.829689 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21222.829689 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21222.829689 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 752786 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 60832 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61311 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.117652 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.278156 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9985 # number of writebacks -system.cpu4.l1c.writebacks::total 9985 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36534 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36534 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23911 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23911 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60445 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60445 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60445 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60445 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9865 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9865 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5418 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5418 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15283 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15283 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 557683920 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 557683920 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 646466038 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 646466038 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1204149958 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1204149958 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1204149958 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1204149958 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 645821695 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 645821695 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 857369844 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 857369844 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1503191539 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1503191539 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.802081 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.802081 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.951568 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.951568 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.855229 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.855229 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.855229 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.855229 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15264.792248 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15264.792248 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27036.344695 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27036.344695 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19921.415469 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65465.959959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65465.959959 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 158244.710963 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158244.710963 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 98357.098672 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 98357.098672 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9736 # number of writebacks +system.cpu4.l1c.writebacks::total 9736 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36616 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36616 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23803 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23803 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60419 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60419 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60419 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60419 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9898 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9898 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5382 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15280 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15280 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 569559682 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 569559682 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 652287465 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 652287465 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1221847147 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1221847147 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1221847147 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1221847147 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 646717625 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 646717625 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 846861232 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 846861232 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1493578857 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1493578857 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806502 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806502 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953684 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953684 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858712 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858712 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15554.939972 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15554.939972 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27403.582111 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27403.582111 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65338.212265 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65338.212265 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157350.656262 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157350.656262 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 97747.307395 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 97747.307395 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99788 # number of read accesses completed -system.cpu5.num_writes 55138 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22475 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.735284 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13651 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.596817 # Average number of references to valid blocks. +system.cpu5.num_reads 99420 # number of read accesses completed +system.cpu5.num_writes 55050 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22127 # number of replacements +system.cpu5.l1c.tags.tagsinuse 390.223258 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13616 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.604752 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.735284 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.767061 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.767061 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_blocks::cpu5 390.223258 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.762155 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.762155 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 340255 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 340255 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8878 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8878 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1131 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1131 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 10009 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 10009 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 10009 # number of overall hits -system.cpu5.l1c.overall_hits::total 10009 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36858 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36858 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23929 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23929 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60787 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60787 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60787 # number of overall misses -system.cpu5.l1c.overall_misses::total 60787 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 604018831 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 604018831 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 667551562 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 667551562 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1271570393 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1271570393 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1271570393 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1271570393 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45736 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45736 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25060 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25060 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70796 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70796 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70796 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70796 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805886 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.805886 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954868 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858622 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858622 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858622 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858622 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16387.726708 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16387.726708 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27897.177567 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 27897.177567 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20918.459424 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20918.459424 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20918.459424 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20918.459424 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 731203 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338569 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338569 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8830 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8830 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1218 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1218 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 10048 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 10048 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 10048 # number of overall hits +system.cpu5.l1c.overall_hits::total 10048 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36409 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36409 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60404 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60404 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60404 # number of overall misses +system.cpu5.l1c.overall_misses::total 60404 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 603629256 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 603629256 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 675904407 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 675904407 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1279533663 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1279533663 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1279533663 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1279533663 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45239 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45239 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25213 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70452 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70452 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70452 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70452 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804814 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.804814 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951692 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.951692 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.857378 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.857378 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.857378 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.857378 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16579.122085 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16579.122085 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28168.552073 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 28168.552073 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21182.929326 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21182.929326 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21182.929326 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21182.929326 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 750665 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 60676 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61291 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.050943 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.247557 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9872 # number of writebacks -system.cpu5.l1c.writebacks::total 9872 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36858 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36858 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23929 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23929 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60787 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60787 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60787 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60787 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9627 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9627 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5446 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5446 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15073 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567160831 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567160831 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 643622562 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 643622562 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1210783393 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1210783393 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1210783393 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1210783393 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 632098852 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 632098852 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 869172204 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 869172204 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1501271056 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1501271056 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805886 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805886 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954868 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858622 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858622 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858622 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858622 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15387.726708 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15387.726708 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26897.177567 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26897.177567 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19918.459424 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65658.964579 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65658.964579 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 159598.274697 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159598.274697 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 99600.016984 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 99600.016984 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9761 # number of writebacks +system.cpu5.l1c.writebacks::total 9761 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36409 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36409 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60404 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60404 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60404 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60404 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9891 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9891 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5483 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5483 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15374 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15374 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567222256 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567222256 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 651909407 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 651909407 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1219131663 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1219131663 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1219131663 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1219131663 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648234678 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648234678 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 860459231 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 860459231 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1508693909 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1508693909 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804814 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804814 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951692 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951692 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.857378 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.857378 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15579.177017 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15579.177017 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27168.552073 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27168.552073 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65537.830149 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65537.830149 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 156932.196061 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156932.196061 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 98132.815728 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 98132.815728 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99577 # number of read accesses completed -system.cpu6.num_writes 55267 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22184 # number of replacements -system.cpu6.l1c.tags.tagsinuse 392.209079 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13575 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22573 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.601382 # Average number of references to valid blocks. +system.cpu6.num_reads 99130 # number of read accesses completed +system.cpu6.num_writes 55082 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22211 # number of replacements +system.cpu6.l1c.tags.tagsinuse 391.729996 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22620 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.594651 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 392.209079 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.766033 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.766033 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337224 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337224 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8787 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8787 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1092 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1092 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9879 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9879 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9879 # number of overall hits -system.cpu6.l1c.overall_hits::total 9879 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36436 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36436 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23858 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23858 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60294 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60294 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60294 # number of overall misses -system.cpu6.l1c.overall_misses::total 60294 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 592887114 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 592887114 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 676055850 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 676055850 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1268942964 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1268942964 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1268942964 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1268942964 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45223 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45223 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24950 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70173 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70173 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70173 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70173 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805696 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805696 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956232 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956232 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859219 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859219 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859219 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859219 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16272.014326 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16272.014326 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28336.652276 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 28336.652276 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21045.924371 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21045.924371 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21045.924371 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21045.924371 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 742965 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 391.729996 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.765098 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.765098 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338357 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338357 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8673 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8673 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1155 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1155 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9828 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9828 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9828 # number of overall hits +system.cpu6.l1c.overall_hits::total 9828 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36524 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36524 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24020 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24020 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60544 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60544 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60544 # number of overall misses +system.cpu6.l1c.overall_misses::total 60544 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 604615121 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 604615121 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 676363327 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 676363327 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1280978448 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1280978448 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1280978448 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1280978448 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45197 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45197 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25175 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808107 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808107 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954121 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954121 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.860342 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.860342 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.860342 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.860342 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16553.913071 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16553.913071 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28158.340008 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 28158.340008 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21157.809989 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21157.809989 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21157.809989 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21157.809989 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 747919 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61020 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61299 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.175762 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.201162 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9883 # number of writebacks -system.cpu6.l1c.writebacks::total 9883 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36436 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36436 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23858 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23858 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60294 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60294 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60294 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60294 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9920 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9920 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5475 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5475 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15395 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15395 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 556451114 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 556451114 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652198850 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652198850 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1208649964 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1208649964 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1208649964 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1208649964 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 646733639 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 646733639 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 847369233 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 847369233 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1494102872 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494102872 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805696 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805696 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956232 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956232 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859219 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859219 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859219 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859219 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15272.014326 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15272.014326 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27336.694191 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27336.694191 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20045.940956 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65194.923286 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65194.923286 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154770.636164 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154770.636164 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97051.177135 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97051.177135 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9790 # number of writebacks +system.cpu6.l1c.writebacks::total 9790 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36524 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36524 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24020 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24020 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60544 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60544 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9846 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9846 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5510 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5510 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15356 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15356 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 568091121 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 568091121 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652345327 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652345327 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1220436448 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1220436448 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1220436448 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1220436448 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 644948195 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 644948195 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 860679200 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 860679200 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1505627395 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1505627395 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808107 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808107 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954121 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954121 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.860342 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.860342 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15553.913071 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15553.913071 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27158.423272 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27158.423272 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65503.574548 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65503.574548 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156203.121597 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156203.121597 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 98048.150234 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 98048.150234 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99427 # number of read accesses completed -system.cpu7.num_writes 55134 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22242 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.816785 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13453 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22633 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.594398 # Average number of references to valid blocks. +system.cpu7.num_reads 99282 # number of read accesses completed +system.cpu7.num_writes 55000 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22412 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.240178 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13369 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22828 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.585640 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.816785 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.765267 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.765267 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_blocks::cpu7 392.240178 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766094 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766094 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338054 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338054 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8636 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8636 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9784 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9784 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9784 # number of overall hits -system.cpu7.l1c.overall_hits::total 9784 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36700 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36700 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23832 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23832 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60532 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60532 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60532 # number of overall misses -system.cpu7.l1c.overall_misses::total 60532 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 601580634 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 601580634 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 672036114 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 672036114 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1273616748 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1273616748 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1273616748 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1273616748 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45336 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24980 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70316 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70316 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70316 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70316 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809511 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.809511 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954043 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954043 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860857 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860857 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860857 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860857 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16391.842888 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16391.842888 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28198.897029 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 28198.897029 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21040.387696 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21040.387696 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21040.387696 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21040.387696 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 739183 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337994 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337994 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8608 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8608 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1119 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1119 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9727 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9727 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9727 # number of overall hits +system.cpu7.l1c.overall_hits::total 9727 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36557 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36557 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24000 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24000 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60557 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60557 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60557 # number of overall misses +system.cpu7.l1c.overall_misses::total 60557 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 604992547 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 604992547 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 682517760 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 682517760 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1287510307 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1287510307 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1287510307 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1287510307 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45165 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45165 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25119 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70284 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70284 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70284 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70284 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809410 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.809410 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955452 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955452 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.861604 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.861604 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.861604 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.861604 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16549.294171 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16549.294171 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28438.240000 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 28438.240000 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21261.130951 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21261.130951 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21261.130951 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21261.130951 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 748003 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 60836 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61301 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.150421 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.202134 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9689 # number of writebacks -system.cpu7.l1c.writebacks::total 9689 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36700 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36700 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23832 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60532 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60532 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60532 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60532 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9751 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9751 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5566 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5566 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15317 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15317 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 564880634 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 564880634 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 648206114 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 648206114 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1213086748 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1213086748 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1213086748 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1213086748 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 637373819 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 637373819 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 878019147 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 878019147 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1515392966 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1515392966 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809511 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809511 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954043 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954043 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860857 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860857 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860857 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860857 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15391.842888 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15391.842888 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27198.980950 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27198.980950 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20040.420736 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65364.969644 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65364.969644 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157746.882321 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157746.882321 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98935.363714 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98935.363714 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9927 # number of writebacks +system.cpu7.l1c.writebacks::total 9927 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36557 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36557 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24000 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60557 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60557 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60557 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60557 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9747 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9747 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5404 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15151 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15151 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 568436547 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 568436547 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 658518760 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 658518760 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1226955307 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1226955307 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1226955307 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1226955307 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 638135236 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 638135236 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 851560751 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 851560751 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1489695987 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1489695987 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809410 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809410 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955452 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955452 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.861604 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.861604 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15549.321525 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15549.321525 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27438.281667 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27438.281667 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65469.912383 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65469.912383 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157579.709660 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157579.709660 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98323.278133 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98323.278133 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13635 # number of replacements -system.l2c.tags.tagsinuse 787.795797 # Cycle average of tags in use -system.l2c.tags.total_refs 163881 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.364052 # Average number of references to valid blocks. +system.l2c.tags.replacements 14184 # number of replacements +system.l2c.tags.tagsinuse 788.596931 # Cycle average of tags in use +system.l2c.tags.total_refs 165124 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14990 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.015610 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 732.377461 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.931961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.975655 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.944636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.398268 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.695089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.188919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.047720 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.236089 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.715212 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006769 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006812 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006782 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007225 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006538 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007066 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.769332 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 786 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 654 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2092959 # Number of tag accesses -system.l2c.tags.data_accesses 2092959 # Number of data accesses -system.l2c.Writeback_hits::writebacks 77190 # number of Writeback hits -system.l2c.Writeback_hits::total 77190 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 242 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 278 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 299 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 286 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 279 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 254 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 287 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2215 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1757 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1745 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1812 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1725 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1792 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1760 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1718 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1773 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14082 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10725 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10956 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10775 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 10922 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10805 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10917 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10735 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10921 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86756 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12482 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12701 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12597 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12677 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12453 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12694 # number of demand (read+write) hits -system.l2c.demand_hits::total 100838 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12482 # number of overall hits -system.l2c.overall_hits::cpu1 12701 # number of overall hits -system.l2c.overall_hits::cpu2 12587 # number of overall hits -system.l2c.overall_hits::cpu3 12647 # number of overall hits -system.l2c.overall_hits::cpu4 12597 # number of overall hits -system.l2c.overall_hits::cpu5 12677 # number of overall hits -system.l2c.overall_hits::cpu6 12453 # number of overall hits -system.l2c.overall_hits::cpu7 12694 # number of overall hits -system.l2c.overall_hits::total 100838 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2065 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2004 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2022 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2044 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2054 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2029 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2097 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2076 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16391 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4632 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4551 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4580 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4616 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4586 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4561 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4720 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4602 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 36848 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 688 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 704 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 710 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 732 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 671 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 651 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 677 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 715 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5548 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5320 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5255 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5290 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5348 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5257 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5212 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5397 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5317 # number of demand (read+write) misses -system.l2c.demand_misses::total 42396 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5320 # number of overall misses -system.l2c.overall_misses::cpu1 5255 # number of overall misses -system.l2c.overall_misses::cpu2 5290 # number of overall misses -system.l2c.overall_misses::cpu3 5348 # number of overall misses -system.l2c.overall_misses::cpu4 5257 # number of overall misses -system.l2c.overall_misses::cpu5 5212 # number of overall misses -system.l2c.overall_misses::cpu6 5397 # number of overall misses -system.l2c.overall_misses::cpu7 5317 # number of overall misses -system.l2c.overall_misses::total 42396 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 61352981 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 61176995 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 58729489 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 63986497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 59053489 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 58462992 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 64338488 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 61927494 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 489028425 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 253959415 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 249536911 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 250480927 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 252977424 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 251220434 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 249579925 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 257995414 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 252050416 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2017800866 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 42779912 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 43250421 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 44195907 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 44710425 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 41223921 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 40317415 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 42323414 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 44497906 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 343299321 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 296739327 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 292787332 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 294676834 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 297687849 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 292444355 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 289897340 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 300318828 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 296548322 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2361100187 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 296739327 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 292787332 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 294676834 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 297687849 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 292444355 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 289897340 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 300318828 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 296548322 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2361100187 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 77190 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77190 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2307 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2282 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2312 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2343 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2340 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2308 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2363 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18606 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6389 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6392 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6341 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6378 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6321 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6438 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6375 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50930 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11413 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11660 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11485 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11654 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11476 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11568 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11412 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11636 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92304 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17802 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17956 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17877 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17854 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17889 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17850 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18011 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143234 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17802 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17956 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17877 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17995 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17854 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17889 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17850 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18011 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143234 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.895102 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.878177 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.874567 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.872386 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.877778 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.879116 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.891961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.878544 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.880952 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.724996 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.722840 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.716521 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.727961 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.719034 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.721563 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.733147 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.721882 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.723503 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.060282 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.060377 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.061820 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.062811 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.058470 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.056276 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.059324 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.061447 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.060106 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.298843 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.292660 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.295911 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.297194 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.294444 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291352 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.302353 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.295208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.295991 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.298843 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.292660 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.295911 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.297194 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.294444 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291352 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.302353 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.295208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.295991 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29710.886683 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 30527.442615 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29045.246785 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 31304.548434 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28750.481500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28813.697388 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 30681.205532 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29830.199422 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29835.179367 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 54827.162133 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 54831.226324 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 54690.158734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54804.467938 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 54779.859137 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54720.439597 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 54660.045339 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 54769.755758 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54760.119030 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 62180.104651 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61435.257102 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62247.756338 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61079.815574 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61436.543964 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61931.513057 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62516.121123 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62234.833566 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 61878.031903 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55778.068985 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55715.952807 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55704.505482 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55663.397345 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55629.513981 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55621.132003 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55645.511951 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55773.617077 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55691.579088 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55778.068985 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55715.952807 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55704.505482 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55663.397345 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55629.513981 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55621.132003 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55645.511951 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55773.617077 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55691.579088 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 18273 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 730.575268 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.784178 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.707727 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.687216 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.484376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.524449 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.360121 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.299960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.173635 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.713452 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006625 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007527 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007507 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006372 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007188 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007129 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.770114 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 806 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 681 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2105340 # Number of tag accesses +system.l2c.tags.data_accesses 2105340 # Number of data accesses +system.l2c.Writeback_hits::writebacks 77391 # number of Writeback hits +system.l2c.Writeback_hits::total 77391 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 263 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 239 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 258 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 248 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 266 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 263 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 283 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2093 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1731 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1747 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1722 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1763 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1786 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1787 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1783 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14062 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 10988 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 10938 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 10927 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 10853 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 11009 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 10877 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10964 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 87383 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12685 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12575 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12772 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12663 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12614 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12747 # number of demand (read+write) hits +system.l2c.demand_hits::total 101445 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12719 # number of overall hits +system.l2c.overall_hits::cpu1 12685 # number of overall hits +system.l2c.overall_hits::cpu2 12670 # number of overall hits +system.l2c.overall_hits::cpu3 12575 # number of overall hits +system.l2c.overall_hits::cpu4 12772 # number of overall hits +system.l2c.overall_hits::cpu5 12663 # number of overall hits +system.l2c.overall_hits::cpu6 12614 # number of overall hits +system.l2c.overall_hits::cpu7 12747 # number of overall hits +system.l2c.overall_hits::total 101445 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1986 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2040 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2071 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2052 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 2099 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2039 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 2050 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 2087 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 16424 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4684 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4646 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4587 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4709 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4574 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4603 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4641 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4708 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37152 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 746 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 738 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 778 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 755 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 710 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 726 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 763 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 735 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 5951 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 5430 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5365 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5464 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5284 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5329 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5404 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5443 # number of demand (read+write) misses +system.l2c.demand_misses::total 43103 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5430 # number of overall misses +system.l2c.overall_misses::cpu1 5384 # number of overall misses +system.l2c.overall_misses::cpu2 5365 # number of overall misses +system.l2c.overall_misses::cpu3 5464 # number of overall misses +system.l2c.overall_misses::cpu4 5284 # number of overall misses +system.l2c.overall_misses::cpu5 5329 # number of overall misses +system.l2c.overall_misses::cpu6 5404 # number of overall misses +system.l2c.overall_misses::cpu7 5443 # number of overall misses +system.l2c.overall_misses::total 43103 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 59643812 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 60697485 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 64325987 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 61406491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 65507992 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 63321487 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 63031988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 64081491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 502016733 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 260655915 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 258218912 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 254645420 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 260879417 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 253975429 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 255536909 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 257461916 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 261401431 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2062775349 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 45984404 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 45132427 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 48152413 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 46986917 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 43700923 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 45387411 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 47108917 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 45792412 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 368245824 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 306640319 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 303351339 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 302797833 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 307866334 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 297676352 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 300924320 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 304570833 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 307193843 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2431021173 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 306640319 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 303351339 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 302797833 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 307866334 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 297676352 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 300924320 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 304570833 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 307193843 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2431021173 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 77391 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77391 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2249 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2279 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2329 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2325 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2347 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2313 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2370 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18517 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6415 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6393 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6330 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6431 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6337 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6389 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6428 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6491 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51214 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11734 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11676 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11705 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11608 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11719 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11603 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11590 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11699 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 93334 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18149 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18069 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18035 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18039 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18056 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17992 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18018 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18190 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 144548 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18149 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18069 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18035 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18039 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18056 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17992 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18018 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18190 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 144548 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.883059 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.895129 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.889223 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.882581 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.894333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.884599 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.886295 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.880591 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.886969 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.730164 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.726732 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.724645 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.732234 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.721793 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.720457 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.721998 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.725312 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.725427 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.063576 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.063207 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.066467 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.065041 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.060585 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.062570 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.065833 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.062826 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.063760 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.299190 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.297969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.297477 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.302899 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.292645 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.296187 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.299922 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.299230 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.298192 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.299190 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.297969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.297477 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.302899 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.292645 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.296187 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.299922 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.299230 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.298192 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 30032.130916 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29753.669118 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 31060.351038 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29925.190546 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 31209.143402 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 31055.167729 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 30747.311220 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 30705.074748 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 30566.045604 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55648.145816 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55578.758502 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55514.589056 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55400.173498 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55525.891780 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 55515.296328 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55475.525964 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55522.818819 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55522.592297 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61641.292225 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61155.050136 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 61892.561697 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 62234.327152 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61550.595775 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62517.095041 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 61741.699869 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62302.601361 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 61879.654512 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56471.513628 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56343.116456 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56439.484250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 56344.497438 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 56335.418622 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 56469.191218 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56360.257772 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 56438.332353 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 56400.277776 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56471.513628 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56343.116456 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56439.484250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 56344.497438 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 56335.418622 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 56469.191218 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56360.257772 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 56438.332353 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 56400.277776 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17704 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3257 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3172 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5.610378 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.581337 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6215 # number of writebacks -system.l2c.writebacks::total 6215 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 6492 # number of writebacks +system.l2c.writebacks::total 6492 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 7 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 32 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 55 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 87 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1195 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1195 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2064 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2004 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2022 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2044 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2053 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2028 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2097 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2076 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16388 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4627 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4548 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4577 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4615 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4579 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4556 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4715 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4599 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 36816 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 683 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 697 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 705 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 723 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 661 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 644 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 672 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 708 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5493 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5310 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5245 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5282 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5338 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5240 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5200 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5387 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5307 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42309 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5310 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5245 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5282 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5338 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5240 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5200 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5387 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5307 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42309 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9914 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9790 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9904 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 10012 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9864 # 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number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 93067979 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 92238981 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 94104480 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 91562476 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 91964478 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 93840981 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 737657156 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 213700915 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 211685412 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 208764420 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 213671917 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 208164429 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 209421909 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 210919416 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 214243431 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1690571849 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 38320904 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 37446428 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 40065914 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 39278917 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 36377424 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 38015411 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 39226917 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 38343914 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 307075829 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 252021819 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 249131840 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 248830334 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 252950834 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 244541853 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 247437320 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 250146333 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 252587345 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1997647678 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 252021819 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 249131840 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 248830334 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 252950834 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 244541853 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 247437320 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 250146333 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 252587345 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1997647678 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 434119876 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 432203209 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 433941865 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 434763383 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 440636377 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 440018712 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 437840875 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 433521379 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3487045676 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 249140431 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 246794950 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 253993435 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 250261774 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 246746570 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 252474432 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 253706432 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 248671425 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2001789449 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 683260307 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 678998159 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 687935300 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 685025157 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 687382947 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 692493144 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 691547307 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 682192804 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5488835125 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.894668 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.878177 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.874567 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.872386 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.877350 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.878683 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.891961 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878544 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.880791 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.724213 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.722363 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.716051 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.727803 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717937 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720772 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.732370 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721412 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.722875 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059844 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.059777 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.061384 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062039 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.057598 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.055671 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.058885 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060846 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059510 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.295463 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.296638 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.293492 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.290681 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.301793 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.294653 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.295384 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.295463 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.296638 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.293492 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.290681 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.301793 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.294653 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.295384 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44153.813953 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44143.207086 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44154.787339 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44162.909002 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44126.387725 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44141.018245 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44148.535527 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44114.156069 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44143.052905 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44845.994381 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44851.673483 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44703.501857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44814.176381 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44823.200262 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44734.180202 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44683.120679 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44790.805827 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44780.567362 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52327.836018 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51742.355811 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52404.123404 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 51409.993084 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51785.054463 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52146.608696 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52778.891369 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52485.744350 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52131.499181 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 45808.348023 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 45767.365682 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 45731.320523 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 45707.540090 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 45701.403626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 45652.180962 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 45693.025617 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 45817.377614 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 45808.348023 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 45767.365682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 45731.320523 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 45707.540090 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 45701.403626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 45652.180962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 45693.025617 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 45817.377614 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44434.574642 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44385.022778 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44375.893074 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44381.776768 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44449.804846 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44425.871923 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44369.744556 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44358.191365 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44397.556218 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45566.328559 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45522.452536 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45629.941953 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45783.280264 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45522.884970 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45504.485678 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45710.947032 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45702.306849 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45617.859258 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44842.397445 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44795.121555 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44817.054977 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44875.891943 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44830.158377 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44815.584024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44846.723027 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44846.457947 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 44833.789624 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.883059 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.894691 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889223 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882581 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.894333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.883731 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.886295 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880591 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.886807 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.729228 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.725950 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.724171 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.730991 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721161 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.719831 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720909 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724850 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.724646 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.062894 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062264 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.065186 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.064352 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.059903 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.062139 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064884 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.062484 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063010 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297431 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297431 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44922.610775 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44954.132418 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44938.666828 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44950.770468 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44833.006193 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44949.669121 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44860.720976 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44964.533301 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44921.573351 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45682.110945 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45612.025856 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45541.976440 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45452.439268 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45550.203282 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 45536.401174 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 45515.627104 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45535.266950 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 45553.240165 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 51925.344173 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51508.154058 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52511.027523 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52582.218206 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51819.692308 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52725.951456 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52163.453457 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52454.054720 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52214.900357 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44420.329070 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44451.631081 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44461.256660 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44495.280217 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44517.718428 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44486.777070 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44473.425597 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44477.416538 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44473.085348 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45722.229950 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46311.681366 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45905.193385 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45877.502108 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45846.631364 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46046.768557 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46061.443718 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46016.177831 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45972.703971 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44886.368874 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45110.162038 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44983.672268 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44990.487127 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44985.794961 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45043.134123 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45043.138605 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45026.255957 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 45008.529040 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 78781 # Transaction distribution -system.membus.trans_dist::ReadResp 84254 # Transaction distribution -system.membus.trans_dist::WriteReq 43831 # Transaction distribution -system.membus.trans_dist::WriteResp 43828 # Transaction distribution -system.membus.trans_dist::Writeback 6215 # Transaction distribution -system.membus.trans_dist::CleanEvict 1216 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61094 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50117 # Transaction distribution -system.membus.trans_dist::ReadExReq 49522 # Transaction distribution -system.membus.trans_dist::ReadExResp 3101 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5483 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 427442 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1069738 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1069738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57394 # Total snoops (count) -system.membus.snoop_fanout::samples 254906 # Request fanout histogram +system.membus.trans_dist::ReadReq 78406 # Transaction distribution +system.membus.trans_dist::ReadResp 84270 # Transaction distribution +system.membus.trans_dist::WriteReq 43542 # Transaction distribution +system.membus.trans_dist::WriteResp 43539 # Transaction distribution +system.membus.trans_dist::Writeback 6492 # Transaction distribution +system.membus.trans_dist::CleanEvict 1226 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61182 # Transaction distribution +system.membus.trans_dist::UpgradeResp 50391 # Transaction distribution +system.membus.trans_dist::ReadExReq 49587 # Transaction distribution +system.membus.trans_dist::ReadExResp 3167 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5869 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 427671 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1115735 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1115735 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57207 # Total snoops (count) +system.membus.snoop_fanout::samples 255615 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254906 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 255615 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254906 # Request fanout histogram -system.membus.reqLayer0.occupancy 291050214 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 56.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 309370624 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 59.9 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 78782 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371328 # Transaction distribution +system.membus.snoop_fanout::total 255615 # Request fanout histogram +system.membus.reqLayer0.occupancy 293172648 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 56.6 # Layer utilization (%) +system.membus.respLayer0.occupancy 310812284 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 60.0 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663719 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283046 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335146 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12757 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6837 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78408 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370885 # Transaction distribution system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43832 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43827 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 83405 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20435 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29579 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29579 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161223 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161218 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292561 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122537 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122267 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122810 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122506 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 980614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769994 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778957 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1770860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783783 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1787183 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1781792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778193 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14229418 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335158 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 800908 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7.017024 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.129362 # Request fanout histogram +system.toL2Bus.trans_dist::WriteReq 43543 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43537 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 83883 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 20723 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29304 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29302 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162111 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162107 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292494 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122467 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122636 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122530 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122681 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 981273 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1801396 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1791690 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1789116 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1791289 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784816 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1784184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1802670 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14325589 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335027 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 801595 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.188537 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.005333 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 787273 98.30% 98.30% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 13635 1.70% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 216155 26.97% 26.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 322197 40.19% 67.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 179904 22.44% 89.60% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 65286 8.14% 97.75% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 15605 1.95% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2259 0.28% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 176 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 13 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 800908 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 495395322 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101110391 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 801595 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 495500281 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101557213 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101309873 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 101587169 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101121441 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101199500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 101172758 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.5 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101251086 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101216377 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 101367103 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101535375 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.7 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101020631 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 101469413 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101588792 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101318353 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 101399821 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 8965da370..e56af27bf 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133625 # Nu sim_ticks 133625300500 # Number of ticks simulated final_tick 133625300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1195401 # Simulator instruction rate (inst/s) -host_op_rate 1195401 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1808178963 # Simulator tick rate (ticks/s) -host_mem_usage 302688 # Number of bytes of host memory used -host_seconds 73.90 # Real time elapsed on the host +host_inst_rate 1279205 # Simulator instruction rate (inst/s) +host_op_rate 1279205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1934942472 # Simulator tick rate (ticks/s) +host_mem_usage 304832 # Number of bytes of host memory used +host_seconds 69.06 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -482,6 +482,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42558.173224 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3862 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3862 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 282633 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 123022 # Transaction distribution @@ -497,15 +503,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28742016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 131016 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 686435 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.190864 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.392983 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005626 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.074797 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 555419 80.91% 80.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 131016 19.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 682573 99.44% 99.44% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3862 0.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 686435 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 446023500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 22fc38403..11714b3d8 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.127293 # Number of seconds simulated -sim_ticks 127292683500 # Number of ticks simulated -final_tick 127292683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.127296 # Number of seconds simulated +sim_ticks 127296402500 # Number of ticks simulated +final_tick 127296402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 884807 # Simulator instruction rate (inst/s) -host_op_rate 1129650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1600449674 # Simulator tick rate (ticks/s) -host_mem_usage 320712 # Number of bytes of host memory used -host_seconds 79.54 # Real time elapsed on the host +host_inst_rate 692014 # Simulator instruction rate (inst/s) +host_op_rate 883507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1251758978 # Simulator tick rate (ticks/s) +host_mem_usage 324360 # Number of bytes of host memory used +host_seconds 101.69 # Real time elapsed on the host sim_insts 70373629 # Number of instructions simulated sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123820 # Nu system.physmem.num_reads::total 127770 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86115 # Number of write requests responded to by this memory system.physmem.num_writes::total 86115 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1985974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62254010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64239984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1985974 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1985974 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43296754 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43296754 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43296754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1985974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62254010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107536738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1985916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62252191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64238108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1985916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1985916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43295489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43295489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43295489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1985916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62252191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107533597 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254585367 # number of cpu cycles simulated +system.cpu.numCycles 254592805 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373629 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254585366.998000 # Number of busy cycles +system.cpu.num_busy_cycles 254592804.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741486 # Number of branches fetched @@ -215,18 +215,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690084 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389202 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.388470 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42608158 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 266.304316 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061071500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389202 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 1061128500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.388470 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 857 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3190 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 137266 # n system.cpu.dcache.demand_misses::total 137266 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 177392 # number of overall misses system.cpu.dcache.overall_misses::total 177392 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 516863000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 516863000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 519264000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 519264000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689129500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5689129500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6205992500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6205992500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6205992500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6205992500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6208393500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6208393500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6208393500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6208393500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17095.422372 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17095.422372 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17174.836277 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17174.836277 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45211.432547 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45211.432547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34984.624448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34984.624448 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45228.924133 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45228.924133 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34998.159443 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34998.159443 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 472117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 472117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 474518000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 474518000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5582097500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5582097500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1070376500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1070376500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6054214500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6054214500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7124591000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7124591000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6056615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6056615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7126992000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7126992000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -340,24 +340,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16219.492923 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16219.492923 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16301.978837 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16301.978837 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44470.504628 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44470.504628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44529.250366 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44529.250366 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44488.140884 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44488.140884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44544.256803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44544.256803 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.672092 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.673242 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672092 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.673242 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id @@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 412325000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 412325000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 412325000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 412325000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 412325000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 412325000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413643000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413643000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413643000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413643000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413643000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413643000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses @@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21806.907129 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21806.907129 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21806.907129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21806.907129 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21876.613074 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21876.613074 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21876.613074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21876.613074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21876.613074 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,42 +418,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393417000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 393417000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393417000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 393417000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393417000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 393417000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 394735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 394735000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 394735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 394735000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 394735000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 394735000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20806.907129 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20806.907129 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20806.907129 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20806.907129 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20876.613074 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20876.613074 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20876.613074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20876.613074 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 94651 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30350.488546 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30350.483830 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 114091 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 125746 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.907313 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27670.394493 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.496373 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.597680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 27670.382318 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.500039 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.601472 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.844433 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.036545 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.045245 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.926223 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1360 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13873 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id @@ -487,16 +487,16 @@ system.cpu.l2cache.overall_misses::cpu.data 123820 # system.cpu.l2cache.overall_misses::total 127770 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371653500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5371653500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207971500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 207971500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133068500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133068500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207971500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6504722000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6712693500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207971500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6504722000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6712693500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207973500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 207973500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1133133500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1133133500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207973500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6504787000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6712760500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207973500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6504787000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6712760500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 128193 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 128193 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) @@ -525,16 +525,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 system.cpu.l2cache.overall_miss_rate::total 0.714174 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52519.099531 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52519.099531 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.012658 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.012658 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52602.994429 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52602.994429 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52537.320967 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.012658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52533.694072 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52537.320967 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52651.518987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52651.518987 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52606.012071 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52606.012071 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52537.845347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52651.518987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52534.219028 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52537.845347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,16 +561,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 system.cpu.l2cache.overall_mshr_misses::total 127770 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4348853500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4348853500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168471500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168471500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917668500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917668500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168471500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266522000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5434993500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168471500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266522000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5434993500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917733500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917733500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168473500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266587000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5435060500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168473500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266587000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5435060500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses @@ -587,17 +587,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 system.cpu.l2cache.overall_mshr_miss_rate::total 0.714174 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.012658 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.012658 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42602.994429 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42602.994429 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.518987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.518987 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42606.012071 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42606.012071 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.518987 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42534.219028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.845347 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3112 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3082 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 214308 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 49439 # Transaction distribution @@ -613,14 +619,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19654336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 94651 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 446349 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.212056 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.408765 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.023656 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.152418 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 351698 78.79% 78.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 94651 21.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 435820 97.64% 97.64% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10499 2.35% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 446349 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 304042000 # Layer occupancy (ticks) diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index e9eb9ae35..9438e6b22 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.202233 # Number of seconds simulated -sim_ticks 202232894500 # Number of ticks simulated -final_tick 202232894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 202232960500 # Number of ticks simulated +final_tick 202232960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1204132 # Simulator instruction rate (inst/s) -host_op_rate 1219723 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1811881435 # Simulator tick rate (ticks/s) -host_mem_usage 302340 # Number of bytes of host memory used -host_seconds 111.61 # Real time elapsed on the host +host_inst_rate 1135828 # Simulator instruction rate (inst/s) +host_op_rate 1150535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1709104516 # Simulator tick rate (ticks/s) +host_mem_usage 304720 # Number of bytes of host memory used +host_seconds 118.33 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,20 +25,20 @@ system.physmem.num_reads::cpu.data 122297 # Nu system.physmem.num_reads::total 131292 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 85205 # Number of write requests responded to by this memory system.physmem.num_writes::total 85205 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2846619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38702942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41549561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2846619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2846619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26964555 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26964555 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26964555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2846619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38702942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 68514116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2846618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38702929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41549548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2846618 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2846618 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26964546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26964546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26964546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2846618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38702929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 68514094 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404465789 # number of cpu cycles simulated +system.cpu.numCycles 404465921 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -57,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 404465788.998000 # Number of busy cycles +system.cpu.num_busy_cycles 404465920.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12719095 # Number of branches fetched @@ -97,12 +97,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293798 # Class of executed instruction system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.647933 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4087.647896 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 769041500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647933 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 769043500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647896 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475169000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1475169000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475184000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475184000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5620115500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5620115500 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7095284500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7095284500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7095284500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7095284500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7095299500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7095299500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7095299500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7095299500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.009275 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.009275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.338953 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.338953 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47093.742326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47093.742326 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47093.841886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.841886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47093.841886 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -192,16 +192,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429670000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429670000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429685000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429685000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5514951500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5514951500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 390000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 390000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944621500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6944621500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944621500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6944621500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6944636500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944636500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6944636500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -212,24 +212,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.009275 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.009275 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.338953 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.338953 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 26000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 26000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.841886 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.841886 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.814775 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 2004.814767 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 143962972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814775 # Average occupied blocks per requestor +system.cpu.icache.tags.warmup_cycle 143963003500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814767 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.978913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id @@ -253,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809817000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2809817000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2809817000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2809817000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2809817000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2809817000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809868000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2809868000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2809868000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2809868000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2809868000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2809868000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -271,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15023.831166 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15023.831166 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15023.831166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15023.831166 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15024.103858 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15024.103858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15024.103858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15024.103858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15024.103858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -291,34 +291,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622793000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2622793000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622793000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2622793000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622793000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2622793000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622844000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2622844000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622844000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2622844000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622844000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2622844000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14023.831166 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14023.831166 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14024.103858 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14024.103858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14024.103858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14024.103858 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 98298 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30848.444766 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30848.444719 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 433066 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 129294 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.349467 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828940 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810202 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805624 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828709 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3594.810369 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1299.805642 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.792048 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.109705 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.039667 # Average percentage of cache occupancy @@ -471,6 +471,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42539.688716 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 669260 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 331558 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3540 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3540 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 209101 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 220689 # Transaction distribution @@ -486,15 +492,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29542272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 98298 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 767558 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.128066 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.334163 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004784 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.069001 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 669260 87.19% 87.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 98298 12.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 763886 99.52% 99.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3672 0.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 767558 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 458526000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 925ba174e..6c0305fad 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316500 # Number of ticks simulated final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1465795 # Simulator instruction rate (inst/s) -host_op_rate 1465795 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1893656296 # Simulator tick rate (ticks/s) -host_mem_usage 298240 # Number of bytes of host memory used -host_seconds 62.70 # Real time elapsed on the host +host_inst_rate 1432938 # Simulator instruction rate (inst/s) +host_op_rate 1432938 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1851208744 # Simulator tick rate (ticks/s) +host_mem_usage 301400 # Number of bytes of host memory used +host_seconds 64.14 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -472,6 +472,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.190767 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.104932 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6731 # Transaction distribution @@ -487,15 +493,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 17571 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 17571 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 17571 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 17571 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 8892500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index dfc2f4ccb..879b8d2d0 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.230173 # Number of seconds simulated -sim_ticks 230173358500 # Number of ticks simulated -final_tick 230173358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.230174 # Number of seconds simulated +sim_ticks 230173520500 # Number of ticks simulated +final_tick 230173520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1194511 # Simulator instruction rate (inst/s) -host_op_rate 1259316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1599980237 # Simulator tick rate (ticks/s) -host_mem_usage 316228 # Number of bytes of host memory used -host_seconds 143.86 # Real time elapsed on the host +host_inst_rate 1035845 # Simulator instruction rate (inst/s) +host_op_rate 1092042 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1387457275 # Simulator tick rate (ticks/s) +host_mem_usage 319880 # Number of bytes of host memory used +host_seconds 165.90 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 480750 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 960110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480750 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 960110 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460346717 # number of cpu cycles simulated +system.cpu.numCycles 460347041 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842484 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460346716.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460347040.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 40300312 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619267 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.619059 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619267 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619059 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id @@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 1788 # n system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35518000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35518000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95712500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95712500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95712500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95712500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51625 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53530.480984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53530.480984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53500.558971 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53500.558971 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34781000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34830000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34830000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59094500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 59094500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93875500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 93875500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93929500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 93929500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93924500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 93924500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93978500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 93978500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -329,24 +329,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50553.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50625 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50625 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53722.272727 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53722.272727 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52503.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52503.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52503.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52503.912800 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52530.480984 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52530.480984 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52531.302404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52531.302404 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992590 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.992416 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992590 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992416 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id @@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112484000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112484000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112484000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112484000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112484000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112484000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses @@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36867.912160 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36867.912160 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36867.912160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36867.912160 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,34 +408,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109320000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 109320000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109320000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 109320000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109320000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 109320000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109433000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 109433000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109433000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 109433000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109433000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 109433000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35830.875123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35830.875123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35867.912160 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35867.912160 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663321 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.663068 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036732 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588811 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036560 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588729 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy @@ -582,6 +582,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42552.053210 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 1466 # Transaction distribution @@ -597,14 +603,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 6386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.035390 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.184778 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6386 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6160 96.46% 96.46% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 226 3.54% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 6386 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3209000 # Layer occupancy (ticks) diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 221e57a79..b410464ce 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.270563 # Number of seconds simulated -sim_ticks 270563082500 # Number of ticks simulated -final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 270563083500 # Number of ticks simulated +final_tick 270563083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1293394 # Simulator instruction rate (inst/s) -host_op_rate 1293395 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1809017316 # Simulator tick rate (ticks/s) -host_mem_usage 297764 # Number of bytes of host memory used -host_seconds 149.56 # Real time elapsed on the host +host_inst_rate 1207450 # Simulator instruction rate (inst/s) +host_op_rate 1207451 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1688810940 # Simulator tick rate (ticks/s) +host_mem_usage 300136 # Number of bytes of host memory used +host_seconds 160.21 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -31,7 +31,7 @@ system.physmem.bw_total::cpu.data 372793 # To system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541126165 # number of cpu cycles simulated +system.cpu.numCycles 541126167 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles +system.cpu.num_busy_cycles 541126166.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.203933 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1237.203935 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203935 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id @@ -219,12 +219,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.579161 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.579162 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579162 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id @@ -248,12 +248,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310819500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310819500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310819500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310819500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310819500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310819500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -266,12 +266,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.555664 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25294.555664 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25294.555664 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.555664 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25294.555664 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -286,33 +286,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12288 system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298530500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 298530500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298530500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 298530500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298530500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 298530500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 298531500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 298531500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 298531500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 298531500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 298531500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 298531500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.474284 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.474284 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.474284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.474284 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24294.555664 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24294.555664 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24294.555664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24294.555664 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.340822 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2678.340828 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282891 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057483 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy @@ -454,6 +454,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.139005 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.096656 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 10362 # Transaction distribution @@ -469,14 +475,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 24228 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000041 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.006425 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 24228 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24227 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 24228 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 12116000 # Layer occupancy (ticks) diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 395ca7a25..00e1fc087 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953957500 # Number of ticks simulated -final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 250953958500 # Number of ticks simulated +final_tick 250953958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 750520 # Simulator instruction rate (inst/s) -host_op_rate 1257940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1426094126 # Simulator tick rate (ticks/s) -host_mem_usage 340216 # Number of bytes of host memory used -host_seconds 175.97 # Real time elapsed on the host +host_inst_rate 759533 # Simulator instruction rate (inst/s) +host_op_rate 1273047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1443220819 # Simulator tick rate (ticks/s) +host_mem_usage 343748 # Number of bytes of host memory used +host_seconds 173.88 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -32,7 +32,7 @@ system.physmem.bw_total::total 1207552 # To system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907915 # number of cpu cycles simulated +system.cpu.numCycles 501907917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 77165304 # nu system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles +system.cpu.num_busy_cycles 501907916.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched @@ -93,12 +93,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457561 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.457562 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457561 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457562 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id @@ -202,12 +202,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53780.314961 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296632 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.296634 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296632 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296634 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id @@ -231,12 +231,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180320500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180320500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180320500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180320500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180320500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180320500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses @@ -249,12 +249,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38415.104389 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38415.104389 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38415.104389 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38415.104389 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38415.104389 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -269,33 +269,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175625500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175625500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175625500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175625500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175625500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175625500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175626500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 175626500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175626500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 175626500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175626500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 175626500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.891351 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37414.891351 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37414.891351 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37414.891351 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.104389 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37415.104389 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37415.104389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37415.104389 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178650 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2058.178654 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978548 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978552 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178359 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy @@ -443,6 +443,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42506.161972 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.791557 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42504.012672 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2870 # Transaction distribution @@ -458,14 +464,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 9476 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000106 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010273 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9476 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 9475 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 9476 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) |