diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
| commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
| tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/quick | |
| parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
| download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz | |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/quick')
59 files changed, 1827 insertions, 1546 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 1a19512dc..f58899eb3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 35d6ad747..ce1ae8d6f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 538 # Number of BTB hits -global.BPredUnit.BTBLookups 1681 # Number of BTB lookups +global.BPredUnit.BTBHits 562 # Number of BTB hits +global.BPredUnit.BTBLookups 1725 # Number of BTB lookups global.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 412 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1149 # Number of conditional branches predicted -global.BPredUnit.lookups 1984 # Number of BP lookups -global.BPredUnit.usedRAS 275 # Number of times the RAS was used to get a target. -host_inst_rate 62494 # Simulator instruction rate (inst/s) -host_mem_usage 196896 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 50069310 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 121 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1979 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1190 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.condIncorrect 409 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted +global.BPredUnit.lookups 2029 # Number of BP lookups +global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target. +host_inst_rate 9351 # Simulator instruction rate (inst/s) +host_mem_usage 180452 # Number of bytes of host memory used +host_seconds 0.60 # Real time elapsed on the host +host_tick_rate 7988790 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 124 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2030 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1236 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4515000 # Number of ticks simulated +sim_ticks 4806000 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 81 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 85 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 8177 +system.cpu.commit.COM:committed_per_cycle.samples 8660 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 5854 7159.10% - 1 1205 1473.65% - 2 403 492.85% - 3 188 229.91% - 4 133 162.65% - 5 98 119.85% - 6 110 134.52% - 7 105 128.41% - 8 81 99.06% + 0 6353 7336.03% + 1 1192 1376.44% + 2 402 464.20% + 3 185 213.63% + 4 132 152.42% + 5 93 107.39% + 6 110 127.02% + 7 108 124.71% + 8 85 98.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4015 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4234 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.584030 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.584030 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1416 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1055000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.065963 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 635000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065963 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 533 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26660.919540 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5781.609195 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 446 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2319500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.163227 # miss rate for WriteReq accesses +system.cpu.cpi 1.680420 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.680420 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10443.877551 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6357.142857 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1437 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1023500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.063844 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 623000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.063844 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 529 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 27385.057471 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5839.080460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 442 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2382500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.164461 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 503000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.163227 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.164461 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.843931 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.141176 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2049 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18045.454545 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1862 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3374500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.091264 # miss rate for demand accesses -system.cpu.dcache.demand_misses 187 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 311 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1138000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.091264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 187 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18410.810811 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 6113.513514 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1879 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 3406000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.089632 # miss rate for demand accesses +system.cpu.dcache.demand_misses 185 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 314 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1131000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.089632 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2049 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18045.454545 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6085.561497 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18410.810811 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 6113.513514 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1862 # number of overall hits -system.cpu.dcache.overall_miss_latency 3374500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.091264 # miss rate for overall accesses -system.cpu.dcache.overall_misses 187 # number of overall misses -system.cpu.dcache.overall_mshr_hits 311 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1138000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.091264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 187 # number of overall MSHR misses +system.cpu.dcache.overall_hits 1879 # number of overall hits +system.cpu.dcache.overall_miss_latency 3406000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.089632 # miss rate for overall accesses +system.cpu.dcache.overall_misses 185 # number of overall misses +system.cpu.dcache.overall_mshr_hits 314 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1131000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.089632 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,91 +119,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 111.683956 # Cycle average of tags in use -system.cpu.dcache.total_refs 1876 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.245747 # Cycle average of tags in use +system.cpu.dcache.total_refs 1894 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 428 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 164 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11204 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5725 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1989 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 729 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchMispred 80 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 11542 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 6127 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2070 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 788 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 235 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 36 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1984 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1520 # Number of cache lines fetched -system.cpu.fetch.Cycles 3641 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12195 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 444 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.222746 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1520 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 813 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.369148 # Number of inst fetches per cycle +system.cpu.dtb.accesses 2656 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 2596 # DTB hits +system.cpu.dtb.misses 60 # DTB misses +system.cpu.dtb.read_accesses 1652 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 1615 # DTB read hits +system.cpu.dtb.read_misses 37 # DTB read misses +system.cpu.dtb.write_accesses 1004 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 981 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.fetch.Branches 2029 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1542 # Number of cache lines fetched +system.cpu.fetch.Cycles 3746 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 226 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12519 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.214732 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1542 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.324902 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 8907 +system.cpu.fetch.rateDist.samples 9449 system.cpu.fetch.rateDist.min_value 0 - 0 6787 7619.85% - 1 178 199.84% - 2 167 187.49% - 3 149 167.28% - 4 210 235.77% - 5 157 176.27% - 6 180 202.09% - 7 101 113.39% - 8 978 1098.01% + 0 7275 7699.23% + 1 181 191.55% + 2 174 184.15% + 3 146 154.51% + 4 219 231.77% + 5 159 168.27% + 6 189 200.02% + 7 101 106.89% + 8 1005 1063.60% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1497 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7812.101911 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1183 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2453000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.209753 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 314 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1727000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.209753 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1520 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7745.954693 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5443.365696 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1211 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 2393500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.203289 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 309 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1682000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.203289 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 309 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.767516 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.919094 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1497 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7812.101911 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5500 # average overall mshr miss latency -system.cpu.icache.demand_hits 1183 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2453000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.209753 # miss rate for demand accesses -system.cpu.icache.demand_misses 314 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1727000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.209753 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1520 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7745.954693 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5443.365696 # average overall mshr miss latency +system.cpu.icache.demand_hits 1211 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 2393500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.203289 # miss rate for demand accesses +system.cpu.icache.demand_misses 309 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1682000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.203289 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 309 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1497 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7812.101911 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5500 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1520 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7745.954693 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5443.365696 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1183 # number of overall hits -system.cpu.icache.overall_miss_latency 2453000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.209753 # miss rate for overall accesses -system.cpu.icache.overall_misses 314 # number of overall misses -system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1727000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.209753 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses +system.cpu.icache.overall_hits 1211 # number of overall hits +system.cpu.icache.overall_miss_latency 2393500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.203289 # miss rate for overall accesses +system.cpu.icache.overall_misses 309 # number of overall misses +system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1682000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.203289 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 309 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 309 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 165.376334 # Cycle average of tags in use -system.cpu.icache.total_refs 1183 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 164.253671 # Cycle average of tags in use +system.cpu.icache.total_refs 1211 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 88946 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1172 # Number of branches executed -system.cpu.iew.EXEC:nop 45 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.880207 # Inst execution rate -system.cpu.iew.EXEC:refs 2591 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 974 # Number of stores executed +system.cpu.idleCycles 110443 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1199 # Number of branches executed +system.cpu.iew.EXEC:nop 72 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.848450 # Inst execution rate +system.cpu.iew.EXEC:refs 2660 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1006 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5292 # num instructions consuming a value -system.cpu.iew.WB:count 7505 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.745276 # average fanout of values written-back +system.cpu.iew.WB:consumers 5426 # num instructions consuming a value +system.cpu.iew.WB:count 7664 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.742905 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3944 # num instructions producing a value -system.cpu.iew.WB:rate 0.842596 # insts written-back per cycle -system.cpu.iew.WB:sent 7591 # cumulative count of insts sent to commit +system.cpu.iew.WB:producers 4031 # num instructions producing a value +system.cpu.iew.WB:rate 0.811091 # insts written-back per cycle +system.cpu.iew.WB:sent 7781 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1979 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2030 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 194 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1190 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9672 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1617 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 358 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7840 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 173 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1236 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9996 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1654 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8017 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 729 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 788 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1000 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 378 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 66 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.631301 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.631301 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8198 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1051 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 424 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.595089 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.595089 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8383 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5452 66.50% # Type of FU issued + IntAlu 5559 66.31% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -279,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1744 21.27% # Type of FU issued - MemWrite 997 12.16% # Type of FU issued + MemRead 1786 21.31% # Type of FU issued + MemWrite 1033 12.32% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 102 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012442 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.012167 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 0 0.00% # attempts to use FU when none available + IntAlu 1 0.98% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,96 +309,100 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 67 65.69% # attempts to use FU when none available + MemRead 66 64.71% # attempts to use FU when none available MemWrite 35 34.31% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 8907 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9449 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 5630 6320.87% - 1 1096 1230.49% - 2 792 889.19% - 3 582 653.42% - 4 464 520.94% - 5 200 224.54% - 6 99 111.15% - 7 30 33.68% - 8 14 15.72% + 0 6104 6459.94% + 1 1119 1184.25% + 2 811 858.29% + 3 592 626.52% + 4 460 486.82% + 5 212 224.36% + 6 105 111.12% + 7 32 33.87% + 8 14 14.82% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.920400 # Inst issue rate -system.cpu.iq.iqInstsAdded 9604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8198 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.887184 # Inst issue rate +system.cpu.iq.iqInstsAdded 9901 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8383 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3664 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3948 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2365 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4486.301370 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2486.301370 # average ReadExReq mshr miss latency +system.cpu.iq.iqSquashedOperandsExamined 2574 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1572 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 1542 # ITB hits +system.cpu.itb.misses 30 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4548.611111 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2548.611111 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_miss_latency 327500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 181500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 72 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 183500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 414 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4450.242718 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.242718 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1833500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995169 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1009500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995169 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4214.285714 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2214.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 59000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4400.246305 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2400.246305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1786500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 974500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4266.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2266.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 64000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 34000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005025 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002558 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 487 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4455.670103 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2161000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995893 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 479 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4422.594142 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2422.594142 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2114000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997912 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 478 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1191000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995893 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1158000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 478 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 487 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4455.670103 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2455.670103 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 479 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4422.594142 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2422.594142 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2161000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995893 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 485 # number of overall misses +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2114000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997912 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 478 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1191000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995893 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1158000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 478 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -399,29 +415,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 398 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 221.319862 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 218.025629 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 8907 # number of cpu cycles simulated +system.cpu.numCycles 9449 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 5884 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 6291 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 13715 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10735 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8030 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1846 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 729 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 14101 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11035 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8205 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1922 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 788 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 122 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 3979 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 4154 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 276 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 532 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed -system.cpu.timesIdled 54 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 57 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index fe297b10e..2c1517e04 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:40 2007 -M5 executing on zeep +M5 compiled Aug 13 2007 17:39:24 +M5 started Mon Aug 13 17:39:25 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4515000 because target called exit() +Exiting @ tick 4806000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index d025afdec..264bd19de 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=tracer workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -31,6 +33,14 @@ workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.tracer] type=ExeTracer @@ -41,7 +51,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index f87ad2cd6..c89057e77 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 109073 # Simulator instruction rate (inst/s) -host_mem_usage 148564 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 54123810 # Simulator tick rate (ticks/s) +host_inst_rate 274181 # Simulator instruction rate (inst/s) +host_mem_usage 172576 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 135418658 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5642 # Number of instructions simulated +sim_insts 5641 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2820500 # Number of ticks simulated +sim_ticks 2833500 # Number of ticks simulated +system.cpu.dtb.accesses 1801 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.misses 10 # DTB misses +system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 5668 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 5651 # ITB hits +system.cpu.itb.misses 17 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5642 # number of cpu cycles simulated -system.cpu.num_insts 5642 # Number of instructions executed -system.cpu.num_refs 1792 # Number of memory references +system.cpu.numCycles 5668 # number of cpu cycles simulated +system.cpu.num_insts 5641 # Number of instructions executed +system.cpu.num_refs 1801 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 0bec3d18f..9af7c0a45 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2007 03:56:47 -M5 started Fri Aug 3 04:17:12 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 17:36:58 +M5 started Tue Aug 14 17:40:03 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2820500 because target called exit() +Exiting @ tick 2833500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index c95e2e383..78fe6c01f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 @@ -156,7 +166,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 3c7a26090..0908a82c9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 334797 # Simulator instruction rate (inst/s) -host_mem_usage 196348 # Number of bytes of host memory used +host_inst_rate 243703 # Simulator instruction rate (inst/s) +host_mem_usage 179944 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1064082508 # Simulator tick rate (ticks/s) +host_tick_rate 781539770 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5642 # Number of instructions simulated +sim_insts 5641 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18365000 # Number of ticks simulated +sim_ticks 18374000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency @@ -76,53 +76,65 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.396682 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.386256 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 1801 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.misses 10 # DTB misses +system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.icache.ReadReq_accesses 5652 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24956.678700 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22956.678700 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 5375 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.049009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 6359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.049009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.371841 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.404332 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 5652 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24956.678700 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency -system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits +system.cpu.icache.demand_hits 5375 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.049009 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 6359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.049009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 5652 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24956.678700 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5366 # number of overall hits +system.cpu.icache.overall_hits 5375 # number of overall hits system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.049009 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 6359000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.049009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 128.096333 # Cycle average of tags in use -system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 128.084203 # Cycle average of tags in use +system.cpu.icache.total_refs 5375 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 5669 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 5652 # ITB hits +system.cpu.itb.misses 17 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -219,14 +235,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 177.517189 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.499846 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 18365000 # number of cpu cycles simulated -system.cpu.num_insts 5642 # Number of instructions executed -system.cpu.num_refs 1792 # Number of memory references +system.cpu.numCycles 18374000 # number of cpu cycles simulated +system.cpu.num_insts 5641 # Number of instructions executed +system.cpu.num_refs 1801 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 940c4ad1c..67d82b1c5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:41 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 17:58:14 +M5 started Tue Aug 14 17:59:07 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 18365000 because target called exit() +Exiting @ tick 18374000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index f5eb9b8b9..d3406f49b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 536bed0d1..ffd2f7ab7 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 143 # Number of BTB hits -global.BPredUnit.BTBLookups 610 # Number of BTB lookups -global.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 212 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 394 # Number of conditional branches predicted -global.BPredUnit.lookups 779 # Number of BP lookups -global.BPredUnit.usedRAS 155 # Number of times the RAS was used to get a target. -host_inst_rate 72558 # Simulator instruction rate (inst/s) -host_mem_usage 196048 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 63572637 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. +global.BPredUnit.BTBHits 156 # Number of BTB hits +global.BPredUnit.BTBLookups 642 # Number of BTB lookups +global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 213 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 401 # Number of conditional branches predicted +global.BPredUnit.lookups 824 # Number of BP lookups +global.BPredUnit.usedRAS 163 # Number of times the RAS was used to get a target. +host_inst_rate 31893 # Simulator instruction rate (inst/s) +host_mem_usage 179460 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 32096529 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 636 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 698 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 412 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2104000 # Number of ticks simulated +sim_ticks 2410000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 32 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 3945 +system.cpu.commit.COM:committed_per_cycle.samples 4452 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 2992 7584.28% - 1 255 646.39% - 2 335 849.18% - 3 139 352.34% - 4 66 167.30% - 5 69 174.90% - 6 33 83.65% - 7 21 53.23% - 8 35 88.72% + 0 3490 7839.17% + 1 258 579.51% + 2 340 763.70% + 3 140 314.47% + 4 70 157.23% + 5 70 157.23% + 6 32 71.88% + 7 20 44.92% + 8 32 71.88% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1134 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1380 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.747382 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.747382 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 519 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 8729.508197 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5745.901639 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 458 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 532500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.117534 # miss rate for ReadReq accesses +system.cpu.cpi 1.984080 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.984080 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 8639.344262 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5655.737705 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 467 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 527000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.115530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 61 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 350500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.117534 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 345000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.115530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 240 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 18810.810811 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6202.702703 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 18297.297297 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5986.486486 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 203 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 696000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 677000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.154167 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 54 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 229500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 221500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.154167 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 7.929412 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.035294 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 759 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 12535.714286 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency -system.cpu.dcache.demand_hits 661 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1228500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.129117 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 768 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 12285.714286 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency +system.cpu.dcache.demand_hits 670 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1204000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127604 # miss rate for demand accesses system.cpu.dcache.demand_misses 98 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 580000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.129117 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 566500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.127604 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 759 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 12535.714286 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5918.367347 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 768 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 12285.714286 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 661 # number of overall hits -system.cpu.dcache.overall_miss_latency 1228500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.129117 # miss rate for overall accesses +system.cpu.dcache.overall_hits 670 # number of overall hits +system.cpu.dcache.overall_miss_latency 1204000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127604 # miss rate for overall accesses system.cpu.dcache.overall_misses 98 # number of overall misses system.cpu.dcache.overall_mshr_hits 64 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 580000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.129117 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 566500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.127604 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 50.690606 # Cycle average of tags in use -system.cpu.dcache.total_refs 674 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 47.072215 # Cycle average of tags in use +system.cpu.dcache.total_refs 683 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 91 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 93 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 126 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4236 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 809 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 225 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 304 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BranchResolved 135 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4564 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3475 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 283 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 303 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 779 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 691 # Number of cache lines fetched -system.cpu.fetch.Cycles 1534 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 112 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 4961 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 223 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.186766 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 691 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 298 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.189403 # Number of inst fetches per cycle +system.cpu.dtb.accesses 931 # DTB accesses +system.cpu.dtb.acv 1 # DTB access violations +system.cpu.dtb.hits 904 # DTB hits +system.cpu.dtb.misses 27 # DTB misses +system.cpu.dtb.read_accesses 575 # DTB read accesses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_hits 563 # DTB read hits +system.cpu.dtb.read_misses 12 # DTB read misses +system.cpu.dtb.write_accesses 356 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 341 # DTB write hits +system.cpu.dtb.write_misses 15 # DTB write misses +system.cpu.fetch.Branches 824 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 707 # Number of cache lines fetched +system.cpu.fetch.Cycles 1626 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 101 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5268 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 242 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.173986 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 707 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 319 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.112331 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 4171 +system.cpu.fetch.rateDist.samples 4736 system.cpu.fetch.rateDist.min_value 0 - 0 3330 7983.70% - 1 36 86.31% - 2 85 203.79% - 3 57 136.66% - 4 109 261.33% - 5 54 129.47% - 6 40 95.90% - 7 42 100.70% - 8 418 1002.16% + 0 3845 8118.67% + 1 38 80.24% + 2 85 179.48% + 3 63 133.02% + 4 118 249.16% + 5 55 116.13% + 6 42 88.68% + 7 48 101.35% + 8 442 933.28% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 674 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7774.193548 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5451.612903 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 488 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.275964 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 186 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1014000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.275964 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7648.351648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5370.879121 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 510 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1392000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.263006 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 182 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 977500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.263006 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.623656 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.802198 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 674 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7774.193548 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency -system.cpu.icache.demand_hits 488 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.275964 # miss rate for demand accesses -system.cpu.icache.demand_misses 186 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1014000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.275964 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 692 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7648.351648 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency +system.cpu.icache.demand_hits 510 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1392000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.263006 # miss rate for demand accesses +system.cpu.icache.demand_misses 182 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 977500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.263006 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 674 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7774.193548 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5451.612903 # average overall mshr miss latency +system.cpu.icache.overall_accesses 692 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7648.351648 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 488 # number of overall hits -system.cpu.icache.overall_miss_latency 1446000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.275964 # miss rate for overall accesses -system.cpu.icache.overall_misses 186 # number of overall misses -system.cpu.icache.overall_mshr_hits 17 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1014000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.275964 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses +system.cpu.icache.overall_hits 510 # number of overall hits +system.cpu.icache.overall_miss_latency 1392000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.263006 # miss rate for overall accesses +system.cpu.icache.overall_misses 182 # number of overall misses +system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 977500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.263006 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 102.643576 # Cycle average of tags in use -system.cpu.icache.total_refs 488 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 92.900452 # Cycle average of tags in use +system.cpu.icache.total_refs 510 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 26984 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 522 # Number of branches executed -system.cpu.iew.EXEC:nop 242 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.736514 # Inst execution rate -system.cpu.iew.EXEC:refs 896 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 333 # Number of stores executed +system.cpu.idleCycles 56472 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 538 # Number of branches executed +system.cpu.iew.EXEC:nop 274 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.670608 # Inst execution rate +system.cpu.iew.EXEC:refs 934 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 356 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1736 # num instructions consuming a value -system.cpu.iew.WB:count 3002 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.793779 # average fanout of values written-back +system.cpu.iew.WB:consumers 1781 # num instructions consuming a value +system.cpu.iew.WB:count 3084 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.794497 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1378 # num instructions producing a value -system.cpu.iew.WB:rate 0.719731 # insts written-back per cycle -system.cpu.iew.WB:sent 3020 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 147 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1415 # num instructions producing a value +system.cpu.iew.WB:rate 0.651182 # insts written-back per cycle +system.cpu.iew.WB:sent 3123 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 149 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 636 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 698 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 3727 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 563 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 108 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3072 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 412 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4056 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 578 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 105 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3176 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 225 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 221 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 99 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 48 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.572285 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.572285 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3180 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 283 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 118 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.504012 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.504012 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3281 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 2258 71.01% # Type of FU issued + IntAlu 2319 70.68% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -279,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 581 18.27% # Type of FU issued - MemWrite 340 10.69% # Type of FU issued + MemRead 597 18.20% # Type of FU issued + MemWrite 364 11.09% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 36 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011321 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010667 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 2 5.56% # attempts to use FU when none available + IntAlu 1 2.86% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,59 +309,63 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 12 33.33% # attempts to use FU when none available - MemWrite 22 61.11% # attempts to use FU when none available + MemRead 12 34.29% # attempts to use FU when none available + MemWrite 22 62.86% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 4171 +system.cpu.iq.ISSUE:issued_per_cycle.samples 4736 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2877 6897.63% - 1 465 1114.84% - 2 300 719.25% - 3 228 546.63% - 4 154 369.22% - 5 89 213.38% - 6 40 95.90% - 7 14 33.57% - 8 4 9.59% + 0 3384 7145.27% + 1 494 1043.07% + 2 314 663.01% + 3 237 500.42% + 4 163 344.17% + 5 88 185.81% + 6 40 84.46% + 7 12 25.34% + 8 4 8.45% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.762407 # Inst issue rate -system.cpu.iq.iqInstsAdded 3479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3180 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.692779 # Inst issue rate +system.cpu.iq.iqInstsAdded 3776 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3281 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 944 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 1238 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 473 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 742 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 735 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 707 # ITB hits +system.cpu.itb.misses 28 # ITB misses system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4750 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2750 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 114000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 4604.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2604.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 110500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 66000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 62500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 247 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4354.251012 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2354.251012 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1075500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4304.526749 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2304.526749 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1046000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 247 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 581500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 560000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 247 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4250 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2250 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 59500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4178.571429 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2178.571429 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 58500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 30500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -360,32 +376,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4389.298893 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4331.460674 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1189500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1156500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 647500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 622500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4389.298893 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2389.298893 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4331.460674 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1189500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1156500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 271 # number of overall misses +system.cpu.l2cache.overall_misses 267 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 647500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 622500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -398,28 +414,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 233 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 127.304233 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 115.687599 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 4171 # number of cpu cycles simulated +system.cpu.numCycles 4736 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3117 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4657 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4106 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2936 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 738 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 225 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1168 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IdleCycles 3552 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 4989 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4410 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3154 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 808 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 283 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1386 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 84 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 50 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 28 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 57159efac..895bd710c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:41 2007 -M5 executing on zeep +M5 compiled Aug 13 2007 17:39:24 +M5 started Mon Aug 13 17:39:27 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2104000 because target called exit() +Exiting @ tick 2410000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 16ea738bc..ac0ec32b8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=tracer workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -31,6 +33,14 @@ workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.tracer] type=ExeTracer @@ -41,7 +51,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index dfc8b7f6b..28ff448c6 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 34280 # Simulator instruction rate (inst/s) -host_mem_usage 147884 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 17043200 # Simulator tick rate (ticks/s) +host_inst_rate 124133 # Simulator instruction rate (inst/s) +host_mem_usage 171628 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 61574601 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2578 # Number of instructions simulated +sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1288500 # Number of ticks simulated +sim_ticks 1297500 # Number of ticks simulated +system.cpu.dtb.accesses 717 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 709 # DTB hits +system.cpu.dtb.misses 8 # DTB misses +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 2596 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 2585 # ITB hits +system.cpu.itb.misses 11 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2578 # number of cpu cycles simulated -system.cpu.num_insts 2578 # Number of instructions executed -system.cpu.num_refs 710 # Number of memory references +system.cpu.numCycles 2596 # number of cpu cycles simulated +system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 6e78c47eb..89de75b41 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2007 03:56:47 -M5 started Fri Aug 3 04:17:14 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 17:36:58 +M5 started Tue Aug 14 17:40:04 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1288500 because target called exit() +Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index f8e125ea1..48fcc2b94 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 @@ -156,7 +166,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 23e886f55..942cc1b79 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 196854 # Simulator instruction rate (inst/s) -host_mem_usage 195480 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 706389035 # Simulator tick rate (ticks/s) +host_inst_rate 123219 # Simulator instruction rate (inst/s) +host_mem_usage 178996 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 443932267 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2578 # Number of instructions simulated +sim_insts 2577 # Number of instructions simulated sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9431000 # Number of ticks simulated +sim_ticks 9438000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency @@ -76,53 +76,65 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 48.863963 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 48.838317 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 717 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 709 # DTB hits +system.cpu.dtb.misses 8 # DTB misses +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 4075000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 3749000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency -system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 4075000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 3749000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2416 # number of overall hits +system.cpu.icache.overall_hits 2423 # number of overall hits system.cpu.icache.overall_miss_latency 4075000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 3749000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 83.443652 # Cycle average of tags in use -system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 83.395749 # Cycle average of tags in use +system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 2597 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 2586 # ITB hits +system.cpu.itb.misses 11 # ITB misses system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -218,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 106.620093 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 106.559981 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 9431000 # number of cpu cycles simulated -system.cpu.num_insts 2578 # Number of instructions executed -system.cpu.num_refs 710 # Number of memory references +system.cpu.numCycles 9438000 # number of cpu cycles simulated +system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index eb8910969..8d08b94be 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:42 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 17:58:14 +M5 started Tue Aug 14 17:59:08 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 9431000 because target called exit() +Exiting @ tick 9438000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index c6807e6a7..653ab3552 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=tracer workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -31,6 +33,12 @@ workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=MipsDTB + +[system.cpu.itb] +type=MipsITB + [system.cpu.tracer] type=ExeTracer @@ -41,7 +49,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index 98d540d90..23e6b5f2c 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 25511 # Simulator instruction rate (inst/s) -host_mem_usage 149560 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host -host_tick_rate 12728361 # Simulator tick rate (ticks/s) +host_inst_rate 9753 # Simulator instruction rate (inst/s) +host_mem_usage 173424 # Number of bytes of host memory used +host_seconds 0.58 # Real time elapsed on the host +host_tick_rate 4872477 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5657 # Number of instructions simulated +sim_insts 5656 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated sim_ticks 2828000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5657 # number of cpu cycles simulated -system.cpu.num_insts 5657 # Number of instructions executed +system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index 3919c7c81..1cc3f6662 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2007 04:06:41 -M5 started Fri Aug 3 04:31:09 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 22:02:23 +M5 started Tue Aug 14 22:02:24 2007 +M5 executing on nacho command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index f2dee3856..7da6cb048 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,9 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=MipsDTB + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +106,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=MipsITB + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 @@ -156,7 +164,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index a9c46636a..cb408c2ca 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 269189 # Simulator instruction rate (inst/s) -host_mem_usage 197500 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 866482072 # Simulator tick rate (ticks/s) +host_inst_rate 186969 # Simulator instruction rate (inst/s) +host_mem_usage 180780 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 602814418 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5657 # Number of instructions simulated +sim_insts 5656 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated sim_ticks 18463000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) @@ -225,7 +225,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 18463000 # number of cpu cycles simulated -system.cpu.num_insts 5657 # Number of instructions executed +system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index ad6e002b5..08628c4d1 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 17:11:48 -M5 started Sun Aug 12 17:11:50 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:02:23 +M5 started Tue Aug 14 22:02:25 2007 +M5 executing on nacho command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 18463000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index d7237a4af..c019a4e06 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=tracer workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -31,6 +33,14 @@ workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.tracer] type=ExeTracer @@ -41,7 +51,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index ab2e76d2a..5a17e8489 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 15625 # Simulator instruction rate (inst/s) -host_mem_usage 149968 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host -host_tick_rate 7799892 # Simulator tick rate (ticks/s) +host_inst_rate 5187 # Simulator instruction rate (inst/s) +host_mem_usage 173740 # Number of bytes of host memory used +host_seconds 0.93 # Real time elapsed on the host +host_tick_rate 2625893 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4863 # Number of instructions simulated +sim_insts 4833 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2431000 # Number of ticks simulated +sim_ticks 2447500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4863 # number of cpu cycles simulated -system.cpu.num_insts 4863 # Number of instructions executed -system.cpu.num_refs 1269 # Number of memory references +system.cpu.numCycles 4896 # number of cpu cycles simulated +system.cpu.num_insts 4833 # Number of instructions executed +system.cpu.num_refs 1282 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 40d1acccc..5bc4aa638 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2007 04:11:25 -M5 started Fri Aug 3 04:31:18 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 22:08:21 +M5 started Tue Aug 14 22:08:22 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2431000 because target called exit() +Exiting @ tick 2447500 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 719701ccd..4674f8812 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 @@ -156,7 +166,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 8907d716d..ff4bd3dbe 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 277220 # Simulator instruction rate (inst/s) -host_mem_usage 197684 # Number of bytes of host memory used +host_inst_rate 198489 # Simulator instruction rate (inst/s) +host_mem_usage 181156 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 892278360 # Simulator tick rate (ticks/s) +host_tick_rate 645076356 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4863 # Number of instructions simulated +sim_insts 4833 # Number of instructions simulated sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 15912000 # Number of ticks simulated +sim_ticks 15925000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24777.777778 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22777.777778 # average ReadReq mshr miss latency @@ -76,53 +76,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 83.464621 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.440192 # Cycle average of tags in use system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24906.250000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22906.250000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 6376000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 5864000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24906.250000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency -system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits +system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 6376000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 5864000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24906.250000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4608 # number of overall hits +system.cpu.icache.overall_hits 4621 # number of overall hits system.cpu.icache.overall_miss_latency 6376000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 5864000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 114.953503 # Cycle average of tags in use -system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 114.921642 # Cycle average of tags in use +system.cpu.icache.total_refs 4621 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -219,14 +219,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 133.743977 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 133.706132 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15912000 # number of cpu cycles simulated -system.cpu.num_insts 4863 # Number of instructions executed -system.cpu.num_refs 1269 # Number of memory references +system.cpu.numCycles 15925000 # number of cpu cycles simulated +system.cpu.num_insts 4833 # Number of instructions executed +system.cpu.num_refs 1282 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 85df476d4..d947b5fb6 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 12:23:15 -M5 started Sun Aug 12 16:58:40 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:08:21 +M5 started Tue Aug 14 22:08:24 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 15912000 because target called exit() +Exiting @ tick 15925000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5a35877e6..71b1480ab 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload0 workload1 +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload0 workload1 BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 5a48eb9ba..e76204a83 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 691 # Number of BTB hits -global.BPredUnit.BTBLookups 3468 # Number of BTB lookups -global.BPredUnit.RASInCorrect 112 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1111 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2334 # Number of conditional branches predicted -global.BPredUnit.lookups 4040 # Number of BP lookups -global.BPredUnit.usedRAS 559 # Number of times the RAS was used to get a target. -host_inst_rate 99825 # Simulator instruction rate (inst/s) -host_mem_usage 197616 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 48783081 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 44 # Number of conflicting stores. +global.BPredUnit.BTBHits 706 # Number of BTB hits +global.BPredUnit.BTBLookups 3499 # Number of BTB lookups +global.BPredUnit.RASInCorrect 117 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1092 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2350 # Number of conditional branches predicted +global.BPredUnit.lookups 4075 # Number of BP lookups +global.BPredUnit.usedRAS 561 # Number of times the RAS was used to get a target. +host_inst_rate 76336 # Simulator instruction rate (inst/s) +host_mem_usage 181020 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 38800813 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 35 # Number of conflicting stores. memdepunit.memDep.conflictingStores 38 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1952 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 1960 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1112 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1121 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1959 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1940 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1118 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1140 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5506000 # Number of ticks simulated +sim_ticks 5727000 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 153 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 161 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 10938 +system.cpu.commit.COM:committed_per_cycle.samples 11403 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 6318 5776.19% - 1 2129 1946.43% - 2 954 872.19% - 3 501 458.04% - 4 328 299.87% - 5 233 213.02% - 6 214 195.65% - 7 108 98.74% - 8 153 139.88% + 0 6781 5946.68% + 1 2144 1880.21% + 2 950 833.11% + 3 495 434.10% + 4 331 290.27% + 5 216 189.42% + 6 215 188.55% + 7 110 96.47% + 8 161 141.19% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 11281 # Number of instructions committed -system.cpu.commit.COM:count_0 5641 # Number of instructions committed -system.cpu.commit.COM:count_1 5640 # Number of instructions committed +system.cpu.commit.COM:count_0 5640 # Number of instructions committed +system.cpu.commit.COM:count_1 5641 # Number of instructions committed system.cpu.commit.COM:loads 1958 # Number of loads committed system.cpu.commit.COM:loads_0 979 # Number of loads committed system.cpu.commit.COM:loads_1 979 # Number of loads committed @@ -61,133 +61,133 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 859 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 854 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8029 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 5624 # Number of Instructions Simulated -system.cpu.committedInsts_1 5623 # Number of Instructions Simulated +system.cpu.commit.commitSquashedInsts 8053 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 5623 # Number of Instructions Simulated +system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 1.952703 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.953050 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.976438 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2963 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 2963 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 12228.855721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 7833.333333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2762 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2762 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2458000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 2458000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.067837 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 201 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 201 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1574500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 1574500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067837 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 201 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 201 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1252 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1252 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 21841.954023 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 6695.402299 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1078 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1078 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3800500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 3800500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.138978 # miss rate for WriteReq accesses +system.cpu.cpi_0 2.035568 # CPI: Cycles Per Instruction +system.cpu.cpi_1 2.035206 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.017694 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 12119.897959 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 7403.061224 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2738 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2738 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2375500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 2375500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.066803 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 196 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 196 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 1451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.066803 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 196 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 196 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1240 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1240 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency_0 21692.528736 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 6310.344828 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1066 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1066 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3774500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 3774500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.140323 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 174 # number of WriteReq misses system.cpu.dcache.WriteReq_misses_0 174 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 372 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 372 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1165000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1165000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.138978 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_hits 384 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 384 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1098000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 1098000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.140323 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.146974 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.276471 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4215 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4215 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4174 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4174 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 16689.333333 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 16621.621622 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 7305.333333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 6889.189189 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3840 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3804 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 6258500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 6258500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 6150000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 6150000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.088968 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.088644 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 375 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 375 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 370 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 370 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 447 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 447 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 465 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 465 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2739500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 2739500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2549000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 2549000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.088968 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.088644 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 375 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 375 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 370 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4215 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4215 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4174 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4174 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 16689.333333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 16621.621622 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 7305.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 6889.189189 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3840 # number of overall hits -system.cpu.dcache.overall_hits_0 3840 # number of overall hits +system.cpu.dcache.overall_hits 3804 # number of overall hits +system.cpu.dcache.overall_hits_0 3804 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 6258500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 6258500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 6150000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 6150000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.088968 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.088644 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 375 # number of overall misses -system.cpu.dcache.overall_misses_0 375 # number of overall misses +system.cpu.dcache.overall_misses 370 # number of overall misses +system.cpu.dcache.overall_misses_0 370 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 447 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 447 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 465 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 465 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2739500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 2739500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2549000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 2549000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.088968 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.088644 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 375 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 375 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 370 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 370 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -207,149 +207,161 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 340 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 219.667658 # Cycle average of tags in use -system.cpu.dcache.total_refs 3868 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 215.589336 # Cycle average of tags in use +system.cpu.dcache.total_refs 3834 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1907 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 262 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 358 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22173 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 14421 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3707 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1515 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 340 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4040 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2997 # Number of cache lines fetched -system.cpu.fetch.Cycles 7042 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 24368 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1175 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.367875 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2997 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1250 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.218904 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 1981 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 247 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22591 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 15034 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3799 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1569 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 329 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 215 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 5095 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 4970 # DTB hits +system.cpu.dtb.misses 125 # DTB misses +system.cpu.dtb.read_accesses 3183 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 3106 # DTB read hits +system.cpu.dtb.read_misses 77 # DTB read misses +system.cpu.dtb.write_accesses 1912 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 1864 # DTB write hits +system.cpu.dtb.write_misses 48 # DTB write misses +system.cpu.fetch.Branches 4075 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3019 # Number of cache lines fetched +system.cpu.fetch.Cycles 7174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 439 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 24770 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1207 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.356020 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3019 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1267 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.164075 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 10982 +system.cpu.fetch.rateDist.samples 11446 system.cpu.fetch.rateDist.min_value 0 - 0 6938 6317.61% - 1 305 277.73% - 2 235 213.99% - 3 261 237.66% - 4 343 312.33% - 5 297 270.44% - 6 304 276.82% - 7 263 239.48% - 8 2036 1853.94% + 0 7343 6415.34% + 1 306 267.34% + 2 243 212.30% + 3 264 230.65% + 4 343 299.67% + 5 290 253.36% + 6 316 276.08% + 7 260 227.15% + 8 2081 1818.10% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 2933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 2933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 8509.630819 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 6073.033708 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2310 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2310 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 5301500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 5301500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.212411 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 623 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 64 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 64 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 3783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 3783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.212411 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 623 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 623 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 2953 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2953 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 8345.528455 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5903.252033 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2338 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2338 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 5132500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 5132500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.208263 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 615 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 615 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 66 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 3630500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 3630500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.208263 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 615 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 615 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.707865 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.801626 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2933 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 2933 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2953 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2953 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 8509.630819 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 8345.528455 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 6073.033708 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 5903.252033 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2310 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2310 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2338 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2338 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 5301500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 5301500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 5132500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 5132500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.212411 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.208263 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 623 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 623 # number of demand (read+write) misses +system.cpu.icache.demand_misses 615 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 615 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 64 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 66 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 3783500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3630500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 3630500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.212411 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.208263 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 623 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 623 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 615 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 615 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2933 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 2933 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2953 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2953 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 8509.630819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 8345.528455 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 6073.033708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 5903.252033 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2310 # number of overall hits -system.cpu.icache.overall_hits_0 2310 # number of overall hits +system.cpu.icache.overall_hits 2338 # number of overall hits +system.cpu.icache.overall_hits_0 2338 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 5301500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 5301500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 5132500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 5132500 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.212411 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.208263 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 623 # number of overall misses -system.cpu.icache.overall_misses_0 623 # number of overall misses +system.cpu.icache.overall_misses 615 # number of overall misses +system.cpu.icache.overall_misses_0 615 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 64 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 64 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 66 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3783500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 3783500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3630500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 3630500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.212411 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.208263 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 623 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 623 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 615 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 615 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -366,107 +378,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 9 # number of replacements -system.cpu.icache.replacements_0 9 # number of replacements +system.cpu.icache.replacements 7 # number of replacements +system.cpu.icache.replacements_0 7 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 623 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 615 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 319.917416 # Cycle average of tags in use -system.cpu.icache.total_refs 2310 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 319.122278 # Cycle average of tags in use +system.cpu.icache.total_refs 2338 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 18494 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2371 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1190 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1181 # Number of branches executed -system.cpu.iew.EXEC:nop 73 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 36 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.425514 # Inst execution rate -system.cpu.iew.EXEC:refs 5064 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2541 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2523 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1883 # Number of stores executed -system.cpu.iew.EXEC:stores_0 944 # Number of stores executed -system.cpu.iew.EXEC:stores_1 939 # Number of stores executed +system.cpu.idleCycles 6496 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2386 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1188 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1198 # Number of branches executed +system.cpu.iew.EXEC:nop 127 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 61 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.378123 # Inst execution rate +system.cpu.iew.EXEC:refs 5110 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2531 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2579 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1925 # Number of stores executed +system.cpu.iew.EXEC:stores_0 958 # Number of stores executed +system.cpu.iew.EXEC:stores_1 967 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10238 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5115 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5123 # num instructions consuming a value -system.cpu.iew.WB:count 15036 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7510 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7526 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.535845 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.766960 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.768885 # average fanout of values written-back +system.cpu.iew.WB:consumers 10281 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5147 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5134 # num instructions consuming a value +system.cpu.iew.WB:count 15145 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7584 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7561 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.539346 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.768992 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.770354 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7862 # num instructions producing a value -system.cpu.iew.WB:producers_0 3923 # num instructions producing a value -system.cpu.iew.WB:producers_1 3939 # num instructions producing a value -system.cpu.iew.WB:rate 1.369150 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.683846 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.685303 # insts written-back per cycle -system.cpu.iew.WB:sent 15186 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7583 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7603 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 992 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3912 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 367 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2233 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 19338 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3181 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1597 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1584 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 917 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15655 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7913 # num instructions producing a value +system.cpu.iew.WB:producers_0 3958 # num instructions producing a value +system.cpu.iew.WB:producers_1 3955 # num instructions producing a value +system.cpu.iew.WB:rate 1.323170 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.662590 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.660580 # insts written-back per cycle +system.cpu.iew.WB:sent 15343 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7675 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7668 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 991 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 60 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3899 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 435 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2258 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19501 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3185 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1573 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1612 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 923 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15774 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 16 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1515 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1569 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 39 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 70 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 62 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 973 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 300 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 980 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 306 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 45 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 61 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 981 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 309 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 131 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 807 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 185 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.512111 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.512020 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.024130 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8256 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 961 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 328 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 125 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 788 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 203 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.491263 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.491351 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.982614 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8365 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5550 67.22% # Type of FU issued + IntAlu 5650 67.54% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -475,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1728 20.93% # Type of FU issued - MemWrite 973 11.79% # Type of FU issued + MemRead 1721 20.57% # Type of FU issued + MemWrite 989 11.82% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8316 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8332 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5613 67.50% # Type of FU issued + IntAlu 5594 67.14% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -492,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1726 20.76% # Type of FU issued - MemWrite 972 11.69% # Type of FU issued + MemRead 1734 20.81% # Type of FU issued + MemWrite 999 11.99% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16572 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16697 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist No_OpClass 4 0.02% # Type of FU issued - IntAlu 11163 67.36% # Type of FU issued + IntAlu 11244 67.34% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -509,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3454 20.84% # Type of FU issued - MemWrite 1945 11.74% # Type of FU issued + MemRead 3455 20.69% # Type of FU issued + MemWrite 1988 11.91% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 198 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 95 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 103 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011948 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.005733 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.006215 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 193 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 105 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011559 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.005270 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.006289 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 14 7.07% # attempts to use FU when none available + IntAlu 13 6.74% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -531,159 +543,163 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 119 60.10% # attempts to use FU when none available - MemWrite 65 32.83% # attempts to use FU when none available + MemRead 111 57.51% # attempts to use FU when none available + MemWrite 69 35.75% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 10982 +system.cpu.iq.ISSUE:issued_per_cycle.samples 11446 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 4716 4294.30% - 1 1863 1696.41% - 2 1568 1427.79% - 3 1132 1030.78% - 4 836 761.25% - 5 492 448.01% - 6 274 249.50% - 7 79 71.94% - 8 22 20.03% + 0 5082 4439.98% + 1 1881 1643.37% + 2 1650 1441.55% + 3 1151 1005.59% + 4 829 724.27% + 5 503 439.45% + 6 239 208.81% + 7 90 78.63% + 8 21 18.35% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.509015 # Inst issue rate -system.cpu.iq.iqInstsAdded 19223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16572 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4476 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 4770.547945 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 2770.547945 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 696500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 696500 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 1.458763 # Inst issue rate +system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16697 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 7298 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4495 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 3071 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 3019 # ITB hits +system.cpu.itb.misses 52 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 144 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses_0 144 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 4743.055556 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 2743.055556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 683000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 683000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 404500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 404500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 144 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses_0 144 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 395000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 395000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 824 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 824 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 4751.219512 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2751.219512 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3896000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 3896000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.995146 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 820 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 820 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2256000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2256000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.995146 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 820 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 820 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 4482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 2482.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 125500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 125500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses_0 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 811 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 811 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 4691.831683 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2691.831683 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3791000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 3791000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.996301 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 808 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 808 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2175000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2175000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.996301 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 808 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 30 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses_0 30 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 4500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 2500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 135000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 135000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 69500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 69500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 30 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses_0 30 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 75000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 75000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 30 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses_0 30 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005051 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003856 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 970 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 970 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 955 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 955 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 4754.140787 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 4699.579832 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2754.140787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2699.579832 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 4 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4592500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 4592500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 4474000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 4474000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.995876 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.996859 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 966 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 966 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 952 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 952 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2660500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 2660500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 2570000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.995876 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.996859 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 966 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 952 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 952 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 970 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 970 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 955 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 955 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 4754.140787 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 4699.579832 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2754.140787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2699.579832 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_hits_0 4 # number of overall hits +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_hits_0 3 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4592500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 4592500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 4474000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 4474000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.995876 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.996859 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 966 # number of overall misses -system.cpu.l2cache.overall_misses_0 966 # number of overall misses +system.cpu.l2cache.overall_misses 952 # number of overall misses +system.cpu.l2cache.overall_misses_0 952 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2660500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 2660500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2570000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 2570000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.995876 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.996859 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 966 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 966 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 952 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 952 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -703,33 +719,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 792 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 778 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 429.647178 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 424.676856 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 10982 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 592 # Number of cycles rename is blocking +system.cpu.numCycles 11446 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 641 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 14764 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 762 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26692 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21016 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15806 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3542 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1515 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 817 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7704 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 503 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 15417 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 776 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 27043 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21312 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15958 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3623 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1569 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 844 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7856 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 504 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2234 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 2318 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 7 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 4 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 5b0ff582b..c45cb0224 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:26:55 -M5 started Sun Aug 12 00:29:42 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 15:45:23 +M5 started Tue Aug 14 15:45:27 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5506000 because target called exit() +Exiting @ tick 5727000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index bfef15018..8c35e4da1 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 0f88834b5..eae7625e9 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 2657 # Number of BTB hits -global.BPredUnit.BTBLookups 6786 # Number of BTB lookups +global.BPredUnit.BTBHits 2711 # Number of BTB hits +global.BPredUnit.BTBLookups 6964 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1999 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 7531 # Number of conditional branches predicted -global.BPredUnit.lookups 7531 # Number of BP lookups +global.BPredUnit.condIncorrect 2012 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 7659 # Number of conditional branches predicted +global.BPredUnit.lookups 7659 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 57578 # Simulator instruction rate (inst/s) -host_mem_usage 198128 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 76965798 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. +host_inst_rate 7502 # Simulator instruction rate (inst/s) +host_mem_usage 186228 # Number of bytes of host memory used +host_seconds 1.39 # Real time elapsed on the host +host_tick_rate 10800438 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3022 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2929 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 3077 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2956 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10976 # Number of instructions simulated +sim_insts 10411 # Number of instructions simulated sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 14690000 # Number of ticks simulated +sim_ticks 14990500 # Number of ticks simulated system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 93 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 87 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 26502 +system.cpu.commit.COM:committed_per_cycle.samples 26989 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 20989 7919.78% - 1 3011 1136.14% - 2 1202 453.55% - 3 588 221.87% - 4 307 115.84% - 5 82 30.94% - 6 195 73.58% - 7 35 13.21% - 8 93 35.09% + 0 21416 7935.08% + 1 3114 1153.80% + 2 1160 429.80% + 3 589 218.24% + 4 306 113.38% + 5 84 31.12% + 6 196 72.62% + 7 37 13.71% + 8 87 32.24% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 1462 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2760 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1999 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2012 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 329 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 13065 # The number of squashed insts skipped by commit -system.cpu.committedInsts 10976 # Number of Instructions Simulated -system.cpu.committedInsts_total 10976 # Number of Instructions Simulated -system.cpu.cpi 2.675656 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.675656 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2253 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9417.910448 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5611.940299 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2186 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 631000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.029738 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 67 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.029738 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses +system.cpu.commit.commitSquashedInsts 13198 # The number of squashed insts skipped by commit +system.cpu.committedInsts 10411 # Number of Instructions Simulated +system.cpu.committedInsts_total 10411 # Number of Instructions Simulated +system.cpu.cpi 2.871770 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.871770 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2274 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 9734.848485 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5560.606061 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2208 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 642500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.029024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 66 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 367000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.029024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1171 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 16509.523810 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5709.523810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 16414.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5623.809524 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1066 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1733500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1723500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089667 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 121 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 599500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 590500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089667 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 21.418301 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.703947 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3424 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 13747.093023 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5671.511628 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3252 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2364500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.050234 # miss rate for demand accesses -system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 141 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 975500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.050234 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 172 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 3445 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13836.257310 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5599.415205 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3274 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2366000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.049637 # miss rate for demand accesses +system.cpu.dcache.demand_misses 171 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 957500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.049637 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 3424 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 13747.093023 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5671.511628 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 3445 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13836.257310 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5599.415205 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3252 # number of overall hits -system.cpu.dcache.overall_miss_latency 2364500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.050234 # miss rate for overall accesses -system.cpu.dcache.overall_misses 172 # number of overall misses -system.cpu.dcache.overall_mshr_hits 141 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 975500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.050234 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 172 # number of overall MSHR misses +system.cpu.dcache.overall_hits 3274 # number of overall hits +system.cpu.dcache.overall_miss_latency 2366000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.049637 # miss rate for overall accesses +system.cpu.dcache.overall_misses 171 # number of overall misses +system.cpu.dcache.overall_mshr_hits 146 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 957500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.049637 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 153 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 112.521037 # Cycle average of tags in use -system.cpu.dcache.total_refs 3277 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 111.288485 # Cycle average of tags in use +system.cpu.dcache.total_refs 3299 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4038 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 37564 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 12395 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 10006 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2866 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 63 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 7531 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4872 # Number of cache lines fetched -system.cpu.fetch.Cycles 15997 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 41653 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2060 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.256436 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2657 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.418312 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 3945 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 38084 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 12820 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 10159 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2909 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 65 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 7659 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4927 # Number of cache lines fetched +system.cpu.fetch.Cycles 16219 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 589 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 42202 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2099 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.256171 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4927 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 2711 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.411533 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 29368 +system.cpu.fetch.rateDist.samples 29898 system.cpu.fetch.rateDist.min_value 0 - 0 18244 6212.20% - 1 4822 1641.92% - 2 611 208.05% - 3 702 239.04% - 4 788 268.32% - 5 623 212.14% - 6 599 203.96% - 7 190 64.70% - 8 2789 949.67% + 0 18628 6230.52% + 1 4885 1633.89% + 2 619 207.04% + 3 712 238.14% + 4 788 263.56% + 5 640 214.06% + 6 611 204.36% + 7 195 65.22% + 8 2820 943.21% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 4851 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7514.784946 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5338.709677 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4479 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2795500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.076685 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 372 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1986000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.076685 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 372 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 4907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7495.945946 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5325.675676 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 4537 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 2773500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.075402 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 370 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1970500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.075402 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12.040323 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12.262162 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4851 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7514.784946 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5338.709677 # average overall mshr miss latency -system.cpu.icache.demand_hits 4479 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2795500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.076685 # miss rate for demand accesses -system.cpu.icache.demand_misses 372 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1986000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.076685 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 4907 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7495.945946 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5325.675676 # average overall mshr miss latency +system.cpu.icache.demand_hits 4537 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 2773500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.075402 # miss rate for demand accesses +system.cpu.icache.demand_misses 370 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 20 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1970500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.075402 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4851 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7514.784946 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5338.709677 # average overall mshr miss latency +system.cpu.icache.overall_accesses 4907 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7495.945946 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5325.675676 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4479 # number of overall hits -system.cpu.icache.overall_miss_latency 2795500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.076685 # miss rate for overall accesses -system.cpu.icache.overall_misses 372 # number of overall misses -system.cpu.icache.overall_mshr_hits 21 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1986000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.076685 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 372 # number of overall MSHR misses +system.cpu.icache.overall_hits 4537 # number of overall hits +system.cpu.icache.overall_miss_latency 2773500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.075402 # miss rate for overall accesses +system.cpu.icache.overall_misses 370 # number of overall misses +system.cpu.icache.overall_mshr_hits 20 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1970500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.075402 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 370 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,61 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 372 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 370 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 236.918934 # Cycle average of tags in use -system.cpu.icache.total_refs 4479 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 233.477311 # Cycle average of tags in use +system.cpu.icache.total_refs 4537 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8496 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3046 # Number of branches executed -system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.623842 # Inst execution rate -system.cpu.iew.EXEC:refs 4481 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2103 # Number of stores executed +system.cpu.idleCycles 51980 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3086 # Number of branches executed +system.cpu.iew.EXEC:nop 1794 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.576995 # Inst execution rate +system.cpu.iew.EXEC:refs 4543 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2116 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9128 # num instructions consuming a value -system.cpu.iew.WB:count 17742 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.828330 # average fanout of values written-back +system.cpu.iew.WB:consumers 9189 # num instructions consuming a value +system.cpu.iew.WB:count 16618 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.827620 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7561 # num instructions producing a value -system.cpu.iew.WB:rate 0.604127 # insts written-back per cycle -system.cpu.iew.WB:sent 17903 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2179 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 7605 # num instructions producing a value +system.cpu.iew.WB:rate 0.555823 # insts written-back per cycle +system.cpu.iew.WB:sent 16830 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2216 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3022 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 611 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2901 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2929 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 24042 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2378 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3319 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 18321 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 3077 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 612 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2973 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2956 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 24330 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2427 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2838 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 17251 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2866 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 2909 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 57 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1560 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1631 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 684 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1495 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.373740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.373740 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 21640 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1615 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1658 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 57 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 695 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1521 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.348217 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.348217 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 20089 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 1766 8.16% # Type of FU issued - IntAlu 14389 66.49% # Type of FU issued + No_OpClass 0 0.00% # Type of FU issued + IntAlu 14535 72.35% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2855 13.19% # Type of FU issued - MemWrite 2630 12.15% # Type of FU issued + MemRead 2907 14.47% # Type of FU issued + MemWrite 2647 13.18% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008364 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009358 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 43 23.76% # attempts to use FU when none available + IntAlu 50 26.60% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,53 +296,53 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 23 12.71% # attempts to use FU when none available - MemWrite 115 63.54% # attempts to use FU when none available + MemRead 23 12.23% # attempts to use FU when none available + MemWrite 115 61.17% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 29368 +system.cpu.iq.ISSUE:issued_per_cycle.samples 29898 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 20067 6832.95% - 1 3826 1302.78% - 2 2129 724.94% - 3 1515 515.87% - 4 870 296.24% - 5 480 163.44% - 6 307 104.54% - 7 103 35.07% - 8 71 24.18% + 0 21040 7037.26% + 1 3621 1211.12% + 2 2127 711.42% + 3 1561 522.11% + 4 748 250.18% + 5 407 136.13% + 6 293 98.00% + 7 62 20.74% + 8 39 13.04% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.736856 # Inst issue rate -system.cpu.iq.iqInstsAdded 23431 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 21640 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 611 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 11038 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 7964 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:rate 0.671918 # Inst issue rate +system.cpu.iq.iqInstsAdded 21924 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 20089 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 612 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 10307 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 86 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4430.232558 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2430.232558 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 381000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 4424.418605 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2424.418605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 380500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 86 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 209000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 208500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 86 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 439 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4291.954023 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2291.954023 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 436 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4287.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2287.037037 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1867000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990888 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 435 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 997000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990888 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 435 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 1852000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990826 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 432 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 988000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990826 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 432 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 4421.052632 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2421.052632 # average UpgradeReq mshr miss latency @@ -354,38 +354,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009615 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 525 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4314.779271 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2314.779271 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 522 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4309.845560 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2309.845560 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2248000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992381 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 521 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 2232500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992337 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 518 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1206000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992381 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 521 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992337 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 518 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 525 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4314.779271 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2314.779271 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 522 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4309.845560 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2309.845560 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2248000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992381 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 521 # number of overall misses +system.cpu.l2cache.overall_miss_latency 2232500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992337 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 518 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1206000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992381 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 521 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992337 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 518 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -398,27 +398,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 263.558349 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 259.708792 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 29368 # number of cpu cycles simulated +system.cpu.numCycles 29898 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 13747 # Number of cycles rename is idle -system.cpu.rename.RENAME:RenameLookups 51214 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 29558 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 24111 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8739 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2866 # Number of cycles rename is squashing +system.cpu.rename.RENAME:IdleCycles 14192 # Number of cycles rename is idle +system.cpu.rename.RENAME:RenameLookups 51924 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 30001 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 24487 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 8874 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2909 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 230 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 14243 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 3786 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 643 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4459 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 681 # count of temporary serializing insts renamed -system.cpu.timesIdled 4 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:UndoneMaps 14619 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 3693 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 648 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4472 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 685 # count of temporary serializing insts renamed +system.cpu.timesIdled 20 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index 9ba201750..82d7a93ac 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 00:08:15 -M5 started Tue Aug 14 00:08:28 2007 -M5 executing on zeep -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing +M5 compiled Aug 19 2007 19:19:06 +M5 started Sun Aug 19 19:19:36 2007 +M5 executing on nacho +command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 14690000 because target called exit() +Exiting @ tick 14990500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 5493b952f..f3afb96c0 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -25,11 +27,23 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + +[system.cpu.itb] +type=SparcITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=insttest @@ -37,7 +51,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin output=cout @@ -53,7 +67,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index 468b3f0a1..9a14dd885 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 563720 # Simulator instruction rate (inst/s) -host_mem_usage 149048 # Number of bytes of host memory used +host_inst_rate 464357 # Simulator instruction rate (inst/s) +host_mem_usage 173536 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 276035132 # Simulator tick rate (ticks/s) +host_tick_rate 229778722 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 11001 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5500000 # Number of ticks simulated +sim_insts 10976 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5514000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11001 # number of cpu cycles simulated -system.cpu.num_insts 11001 # Number of instructions executed -system.cpu.num_refs 2760 # Number of memory references +system.cpu.numCycles 11029 # number of cpu cycles simulated +system.cpu.num_insts 10976 # Number of instructions executed +system.cpu.num_refs 2770 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index 01c59e833..1641f2696 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 17:00:07 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 22:08:21 +M5 started Tue Aug 14 22:08:25 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5500000 because target called exit() +Exiting @ tick 5514000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index b2e950872..85d4c9288 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index 351d5ef89..4a899f629 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 459524 # Simulator instruction rate (inst/s) -host_mem_usage 197560 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1004580342 # Simulator tick rate (ticks/s) +host_inst_rate 343655 # Simulator instruction rate (inst/s) +host_mem_usage 180816 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 753768067 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 11001 # Number of instructions simulated +sim_insts 10976 # Number of instructions simulated sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24345000 # Number of ticks simulated +sim_ticks 24355000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency @@ -78,53 +78,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 100.391376 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 100.373888 # Cycle average of tags in use system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 11002 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 11012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24915.194346 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22915.194346 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10719 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 10729 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 7051000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.025723 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.025699 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 6485000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.025723 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.025699 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 37.876325 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 37.911661 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11002 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 11012 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24915.194346 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22915.194346 # average overall mshr miss latency -system.cpu.icache.demand_hits 10719 # number of demand (read+write) hits +system.cpu.icache.demand_hits 10729 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 7051000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.025723 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.025699 # miss rate for demand accesses system.cpu.icache.demand_misses 283 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 6485000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.025723 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.025699 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 11002 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 11012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24915.194346 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22915.194346 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10719 # number of overall hits +system.cpu.icache.overall_hits 10729 # number of overall hits system.cpu.icache.overall_miss_latency 7051000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.025723 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.025699 # miss rate for overall accesses system.cpu.icache.overall_misses 283 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 6485000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.025723 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.025699 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -140,8 +140,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 156.007276 # Cycle average of tags in use -system.cpu.icache.total_refs 10719 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 155.977710 # Cycle average of tags in use +system.cpu.icache.total_refs 10729 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -221,14 +221,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 318 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 178.142170 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.108320 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 24345000 # number of cpu cycles simulated -system.cpu.num_insts 11001 # Number of instructions executed -system.cpu.num_refs 2760 # Number of memory references +system.cpu.numCycles 24355000 # number of cpu cycles simulated +system.cpu.num_insts 10976 # Number of instructions executed +system.cpu.num_refs 2770 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index e268ba0c6..838fa7706 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 00:08:15 -M5 started Tue Aug 14 00:08:29 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:08:21 +M5 started Tue Aug 14 22:08:25 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 24345000 because target called exit() +Exiting @ tick 24355000 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index d9ba4afe5..eabfb44c3 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2271343 # Simulator instruction rate (inst/s) -host_mem_usage 326380 # Number of bytes of host memory used -host_seconds 27.79 # Real time elapsed on the host -host_tick_rate 67296173797 # Simulator tick rate (ticks/s) +host_inst_rate 2322076 # Simulator instruction rate (inst/s) +host_mem_usage 309268 # Number of bytes of host memory used +host_seconds 27.18 # Real time elapsed on the host +host_tick_rate 68811889767 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 63125943 # Number of instructions simulated +sim_insts 63114079 # Number of instructions simulated sim_seconds 1.870335 # Number of seconds simulated sim_ticks 1870335101500 # Number of ticks simulated system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) @@ -240,7 +240,7 @@ system.cpu0.kern.syscall_144 2 0.88% 99.12% # nu system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles system.cpu0.numCycles 57193784 # number of cpu cycles simulated -system.cpu0.num_insts 57190172 # Number of instructions executed +system.cpu0.num_insts 57182116 # Number of instructions executed system.cpu0.num_refs 15322419 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits @@ -457,7 +457,7 @@ system.cpu1.kern.syscall_90 1 1.00% 98.00% # nu system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles system.cpu1.numCycles 5937367 # number of cpu cycles simulated -system.cpu1.num_insts 5935771 # Number of instructions executed +system.cpu1.num_insts 5931963 # Number of instructions executed system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index b97e23c2a..007c73bfe 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 10 2007 16:03:34 -M5 started Fri Aug 10 16:04:07 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 18:18:39 +M5 started Tue Aug 14 18:19:09 2007 +M5 executing on nacho command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second Exiting @ tick 1870335101500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index a4dd50e83..73b22dfec 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2322212 # Simulator instruction rate (inst/s) -host_mem_usage 325356 # Number of bytes of host memory used -host_seconds 25.84 # Real time elapsed on the host -host_tick_rate 70754225205 # Simulator tick rate (ticks/s) +host_inst_rate 2191272 # Simulator instruction rate (inst/s) +host_mem_usage 308228 # Number of bytes of host memory used +host_seconds 27.38 # Real time elapsed on the host +host_tick_rate 66777888282 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 60007317 # Number of instructions simulated +sim_insts 59995479 # Number of instructions simulated sim_seconds 1.828355 # Number of seconds simulated sim_ticks 1828355476000 # Number of ticks simulated system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses) @@ -235,7 +235,7 @@ system.cpu.kern.syscall_144 2 0.61% 99.39% # nu system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles system.cpu.numCycles 60012507 # number of cpu cycles simulated -system.cpu.num_insts 60007317 # Number of instructions executed +system.cpu.num_insts 59995479 # Number of instructions executed system.cpu.num_refs 16302129 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 00122ad9f..45d7ecef6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 10 2007 16:03:34 -M5 started Fri Aug 10 16:03:39 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 18:18:39 +M5 started Tue Aug 14 18:18:41 2007 +M5 executing on nacho command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1828355476000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 69eddfa1f..8b29b06d6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1168071 # Simulator instruction rate (inst/s) -host_mem_usage 295844 # Number of bytes of host memory used -host_seconds 55.50 # Real time elapsed on the host -host_tick_rate 35475030756 # Simulator tick rate (ticks/s) +host_inst_rate 979093 # Simulator instruction rate (inst/s) +host_mem_usage 278732 # Number of bytes of host memory used +host_seconds 66.19 # Real time elapsed on the host +host_tick_rate 29741162851 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 64822650 # Number of instructions simulated +sim_insts 64810685 # Number of instructions simulated sim_seconds 1.968714 # Number of seconds simulated sim_ticks 1968713509000 # Number of ticks simulated system.cpu0.dcache.LoadLockedReq_accesses 151114 # number of LoadLockedReq accesses(hits+misses) @@ -274,7 +274,7 @@ system.cpu0.kern.syscall_144 1 0.47% 99.06% # nu system.cpu0.kern.syscall_147 2 0.94% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.057929 # Percentage of non-idle cycles system.cpu0.numCycles 1967810461000 # number of cpu cycles simulated -system.cpu0.num_insts 50999228 # Number of instructions executed +system.cpu0.num_insts 50990937 # Number of instructions executed system.cpu0.num_refs 13220047 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 60083 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_avg_miss_latency 15361.860059 # average LoadLockedReq miss latency @@ -529,7 +529,7 @@ system.cpu1.kern.syscall_132 2 1.75% 99.12% # nu system.cpu1.kern.syscall_144 1 0.88% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.013720 # Percentage of non-idle cycles system.cpu1.numCycles 1968713509000 # number of cpu cycles simulated -system.cpu1.num_insts 13823422 # Number of instructions executed +system.cpu1.num_insts 13819748 # Number of instructions executed system.cpu1.num_refs 4429865 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 92c2ca4fd..6f89d18ec 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:31:07 -M5 started Sun Aug 12 00:33:04 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 18:18:39 +M5 started Tue Aug 14 18:20:39 2007 +M5 executing on nacho command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second Exiting @ tick 1968713509000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 677926722..8aeb586fd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1148695 # Simulator instruction rate (inst/s) -host_mem_usage 285372 # Number of bytes of host memory used -host_seconds 52.29 # Real time elapsed on the host -host_tick_rate 36880663274 # Simulator tick rate (ticks/s) +host_inst_rate 986602 # Simulator instruction rate (inst/s) +host_mem_usage 268252 # Number of bytes of host memory used +host_seconds 60.87 # Real time elapsed on the host +host_tick_rate 31682591808 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 60069471 # Number of instructions simulated +sim_insts 60057633 # Number of instructions simulated sim_seconds 1.928634 # Number of seconds simulated sim_ticks 1928634086000 # Number of ticks simulated system.cpu.dcache.LoadLockedReq_accesses 200253 # number of LoadLockedReq accesses(hits+misses) @@ -269,7 +269,7 @@ system.cpu.kern.syscall_144 2 0.61% 99.39% # nu system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.069379 # Percentage of non-idle cycles system.cpu.numCycles 1928634086000 # number of cpu cycles simulated -system.cpu.num_insts 60069471 # Number of instructions executed +system.cpu.num_insts 60057633 # Number of instructions executed system.cpu.num_refs 16313038 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 2743905fa..73f1f9652 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 00:31:07 -M5 started Sun Aug 12 00:32:11 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 18:18:39 +M5 started Tue Aug 14 18:19:37 2007 +M5 executing on nacho command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second Exiting @ tick 1928634086000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index a89c6ef26..9db92d8dc 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 @@ -25,15 +27,27 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=EioProcess chkpt= -file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz output=cout system=system diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 5747db5c2..a82f45966 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,17 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 188118 # Simulator instruction rate (inst/s) -host_seconds 2.66 # Real time elapsed on the host -host_tick_rate 94046824 # Simulator tick rate (ticks/s) +host_inst_rate 2121237 # Simulator instruction rate (inst/s) +host_mem_usage 171724 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 1058992833 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 500000 # Number of instructions simulated +sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 249999500 # Number of ticks simulated +sim_ticks 250015500 # Number of ticks simulated +system.cpu.dtb.accesses 180793 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 180775 # DTB hits +system.cpu.dtb.misses 18 # DTB misses +system.cpu.dtb.read_accesses 124443 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 124435 # DTB read hits +system.cpu.dtb.read_misses 8 # DTB read misses +system.cpu.dtb.write_accesses 56350 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 56340 # DTB write hits +system.cpu.dtb.write_misses 10 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 500032 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 500019 # ITB hits +system.cpu.itb.misses 13 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 500000 # number of cpu cycles simulated -system.cpu.num_insts 500000 # Number of instructions executed -system.cpu.num_refs 182204 # Number of memory references +system.cpu.numCycles 500032 # number of cpu cycles simulated +system.cpu.num_insts 500001 # Number of instructions executed +system.cpu.num_refs 182222 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 01450bbce..fee99ba99 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 10 2007 14:06:20 -M5 started Sun Jun 10 14:22:41 2007 -M5 executing on iceaxe -command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +M5 compiled Aug 14 2007 17:58:14 +M5 started Tue Aug 14 17:58:32 2007 +M5 executing on nacho +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 249999500 because a thread reached the max instruction count +Exiting @ tick 250015500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index aa9f81e79..f967fc1b8 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index d9f2463fd..62a259095 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1380632 # Simulator instruction rate (inst/s) -host_mem_usage 195668 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host -host_tick_rate 1946559093 # Simulator tick rate (ticks/s) +host_inst_rate 1285667 # Simulator instruction rate (inst/s) +host_mem_usage 179016 # Number of bytes of host memory used +host_seconds 0.39 # Real time elapsed on the host +host_tick_rate 1812257249 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 500000 # Number of instructions simulated +sim_insts 500001 # Number of instructions simulated sim_seconds 0.000705 # Number of seconds simulated -sim_ticks 705470000 # Number of ticks simulated +sim_ticks 705490000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency @@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 289.564356 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 289.561085 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 180793 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 180775 # DTB hits +system.cpu.dtb.misses 18 # DTB misses +system.cpu.dtb.read_accesses 124443 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 124435 # DTB read hits +system.cpu.dtb.read_misses 8 # DTB read misses +system.cpu.dtb.write_accesses 56350 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 56340 # DTB write hits +system.cpu.dtb.write_misses 10 # DTB write misses +system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 10075000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses @@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # ms system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1239.694789 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency -system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits +system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 10075000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses @@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 403 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 499597 # number of overall hits +system.cpu.icache.overall_hits 499617 # number of overall hits system.cpu.icache.overall_miss_latency 10075000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 266.632904 # Cycle average of tags in use -system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 266.630553 # Cycle average of tags in use +system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 500033 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 500020 # ITB hits +system.cpu.itb.misses 13 # ITB misses system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -218,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 373.548776 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 373.545251 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 705470000 # number of cpu cycles simulated -system.cpu.num_insts 500000 # Number of instructions executed -system.cpu.num_refs 182203 # Number of memory references +system.cpu.numCycles 705490000 # number of cpu cycles simulated +system.cpu.num_insts 500001 # Number of instructions executed +system.cpu.num_refs 182222 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index c055fe4ae..0de340a66 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 13:54:58 -M5 started Tue Aug 14 13:57:54 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 17:58:14 +M5 started Tue Aug 14 17:58:16 2007 +M5 executing on nacho command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 705470000 because a thread reached the max instruction count +Exiting @ tick 705490000 because a thread reached the max instruction count diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 3385f4fea..e39fb749f 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/saidi/work/m5.bb/configs/boot/netperf-server.rcS +readfile=/home/blackga/m5/repos/m5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -179,7 +179,7 @@ read_only=true [drivesys.tsunami] type=Tsunami -children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=drivesys.intrctrl system=drivesys @@ -203,48 +203,8 @@ sim_console=drivesys.sim_console system=drivesys pio=drivesys.iobus.port[25] -[drivesys.tsunami.etherint] -type=NSGigEInt -device=drivesys.tsunami.ethernet -peer=Null - [drivesys.tsunami.ethernet] type=NSGigE -children=configdata -clock=0 -config_latency=20000 -configdata=drivesys.tsunami.ethernet.configdata -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -hardware_address=00:90:00:00:00:01 -intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -platform=drivesys.tsunami -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=drivesys -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -config=drivesys.iobus.port[28] -dma=drivesys.iobus.port[29] -pio=drivesys.iobus.port[27] - -[drivesys.tsunami.ethernet.configdata] -type=PciConfigData BAR0=1 BAR0Size=256 BAR1=0 @@ -277,6 +237,37 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=drivesys.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=drivesys +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=drivesys.iobus.port[28] +dma=drivesys.iobus.port[29] +interface=etherlink.int1 +pio=drivesys.iobus.port[27] [drivesys.tsunami.fake_OROM] type=IsaFake @@ -593,24 +584,6 @@ pio=drivesys.iobus.port[22] [drivesys.tsunami.ide] type=IdeController -children=configdata -config_latency=20000 -configdata=drivesys.tsunami.ide.configdata -disks=drivesys.disk0 drivesys.disk2 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=1000 -platform=drivesys.tsunami -system=drivesys -config=drivesys.iobus.port[30] -dma=drivesys.iobus.port[31] -pio=drivesys.iobus.port[26] - -[drivesys.tsunami.ide.configdata] -type=PciConfigData BAR0=1 BAR0Size=8 BAR1=1 @@ -643,6 +616,19 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +config_latency=20000 +disks=drivesys.disk0 drivesys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=drivesys.tsunami +system=drivesys +config=drivesys.iobus.port[30] +dma=drivesys.iobus.port[31] +pio=drivesys.iobus.port[26] [drivesys.tsunami.io] type=TsunamiIO @@ -693,9 +679,9 @@ type=EtherLink delay=0 delay_var=0 dump=etherdump -int1=testsys.tsunami.etherint -int2=drivesys.tsunami.etherint speed=8000.000000 +int0=testsys.tsunami.ethernet.interface +int1=drivesys.tsunami.ethernet.interface [testsys] type=LinuxAlphaSystem @@ -708,7 +694,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/saidi/work/m5.bb/configs/boot/netperf-stream-client.rcS +readfile=/home/blackga/m5/repos/m5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -873,7 +859,7 @@ read_only=true [testsys.tsunami] type=Tsunami -children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=testsys.intrctrl system=testsys @@ -897,48 +883,8 @@ sim_console=testsys.sim_console system=testsys pio=testsys.iobus.port[25] -[testsys.tsunami.etherint] -type=NSGigEInt -device=testsys.tsunami.ethernet -peer=Null - [testsys.tsunami.ethernet] type=NSGigE -children=configdata -clock=0 -config_latency=20000 -configdata=testsys.tsunami.ethernet.configdata -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -hardware_address=00:90:00:00:00:02 -intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -platform=testsys.tsunami -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=testsys -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -config=testsys.iobus.port[28] -dma=testsys.iobus.port[29] -pio=testsys.iobus.port[27] - -[testsys.tsunami.ethernet.configdata] -type=PciConfigData BAR0=1 BAR0Size=256 BAR1=0 @@ -971,6 +917,37 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:02 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=testsys.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=testsys +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=testsys.iobus.port[28] +dma=testsys.iobus.port[29] +interface=etherlink.int0 +pio=testsys.iobus.port[27] [testsys.tsunami.fake_OROM] type=IsaFake @@ -1287,24 +1264,6 @@ pio=testsys.iobus.port[22] [testsys.tsunami.ide] type=IdeController -children=configdata -config_latency=20000 -configdata=testsys.tsunami.ide.configdata -disks=testsys.disk0 testsys.disk2 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=1000 -platform=testsys.tsunami -system=testsys -config=testsys.iobus.port[30] -dma=testsys.iobus.port[31] -pio=testsys.iobus.port[26] - -[testsys.tsunami.ide.configdata] -type=PciConfigData BAR0=1 BAR0Size=8 BAR1=1 @@ -1337,6 +1296,19 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +config_latency=20000 +disks=testsys.disk0 testsys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=testsys.tsunami +system=testsys +config=testsys.iobus.port[30] +dma=testsys.iobus.port[31] +pio=testsys.iobus.port[26] [testsys.tsunami.io] type=TsunamiIO diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index c63520549..e80f9a2ec 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -77,7 +77,7 @@ drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # nu drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles drivesys.cpu.numCycles 1958954 # number of cpu cycles simulated -drivesys.cpu.num_insts 1958738 # Number of instructions executed +drivesys.cpu.num_insts 1958129 # Number of instructions executed drivesys.cpu.num_refs 626223 # Number of memory references drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). @@ -139,12 +139,12 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 109126509 # Simulator instruction rate (inst/s) -host_mem_usage 477016 # Number of bytes of host memory used -host_seconds 2.51 # Real time elapsed on the host -host_tick_rate 79838467246 # Simulator tick rate (ticks/s) +host_inst_rate 118863353 # Simulator instruction rate (inst/s) +host_mem_usage 459784 # Number of bytes of host memory used +host_seconds 2.30 # Real time elapsed on the host +host_tick_rate 86976188826 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273348482 # Number of instructions simulated +sim_insts 273294782 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses @@ -234,7 +234,7 @@ testsys.cpu.kern.syscall_105 3 3.61% 97.59% # nu testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles testsys.cpu.numCycles 3566060 # number of cpu cycles simulated -testsys.cpu.num_insts 3564494 # Number of instructions executed +testsys.cpu.num_insts 3560518 # Number of instructions executed testsys.cpu.num_refs 1173605 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). @@ -381,12 +381,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 139108642239 # Simulator instruction rate (inst/s) -host_mem_usage 477016 # Number of bytes of host memory used +host_inst_rate 116742751815 # Simulator instruction rate (inst/s) +host_mem_usage 459784 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 375168496 # Simulator tick rate (ticks/s) +host_tick_rate 317182405 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 273348482 # Number of instructions simulated +sim_insts 273294782 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 345be7558..324ab7868 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 10 2007 16:03:34 -M5 started Fri Aug 10 16:06:35 2007 -M5 executing on zeep +M5 compiled Aug 21 2007 15:42:55 +M5 started Tue Aug 21 15:45:44 2007 +M5 executing on nacho command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 4300235844056 because checkpoint |