diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/quick | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/quick')
203 files changed, 4395 insertions, 1676 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 631fa3b25..08fd1ccfb 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -282,9 +282,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -344,10 +343,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -403,9 +401,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 8c9800a70..06d87b670 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:39:49 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b34633a17..b45122ce6 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,23 +4,50 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1989571 # Simulator instruction rate (inst/s) -host_op_rate 1989570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58921958204 # Simulator tick rate (ticks/s) -host_mem_usage 298304 # Number of bytes of host memory used -host_seconds 31.74 # Real time elapsed on the host +host_inst_rate 2870976 # Simulator instruction rate (inst/s) +host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85025108641 # Simulator tick rate (ticks/s) +host_mem_usage 298608 # Number of bytes of host memory used +host_seconds 22.00 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 72297472 # Number of bytes read from this memory -system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10452352 # Number of bytes written to this memory -system.physmem.num_reads 1129648 # Number of read requests responded to by this memory -system.physmem.num_writes 163318 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 38654814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 531994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 44243304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory +system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory +system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory +system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 1051788 # number of replacements system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use system.l2c.total_refs 2341203 # Total number of references to valid blocks. @@ -118,20 +145,26 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # mi system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -169,9 +202,13 @@ system.iocache.demand_accesses::total 41727 # nu system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -275,6 +312,7 @@ system.cpu0.kern.ipl_used::21 1 # fr system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -333,7 +371,7 @@ system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode @@ -397,8 +435,11 @@ system.cpu0.icache.demand_accesses::total 57230132 # n system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,11 +497,17 @@ system.cpu0.dcache.demand_accesses::total 14729930 # n system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,6 +595,7 @@ system.cpu1.kern.ipl_used::0 0.999032 # fr system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed @@ -593,7 +641,7 @@ system.cpu1.kern.mode_good::idle 32 system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode @@ -626,8 +674,11 @@ system.cpu1.icache.demand_accesses::total 5935766 # n system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,11 +736,17 @@ system.cpu1.dcache.demand_accesses::total 1884270 # n system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 3d4adbd35..3950ce4a4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -185,9 +185,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -247,10 +246,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -306,9 +304,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index f348f1381..92dc7ad3d 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:42:39 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:07:23 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 1b6d7ca40..4492aa0b0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,23 +4,40 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1921293 # Simulator instruction rate (inst/s) -host_op_rate 1921291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58540553267 # Simulator tick rate (ticks/s) -host_mem_usage 295828 # Number of bytes of host memory used -host_seconds 31.25 # Real time elapsed on the host +host_inst_rate 2878195 # Simulator instruction rate (inst/s) +host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87696777763 # Simulator tick rate (ticks/s) +host_mem_usage 296144 # Number of bytes of host memory used +host_seconds 20.86 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 71650816 # Number of bytes read from this memory -system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10156864 # Number of bytes written to this memory -system.physmem.num_reads 1119544 # Number of read requests responded to by this memory -system.physmem.num_writes 158701 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 39167743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 44719968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory +system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory +system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory +system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 1045877 # number of replacements system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use system.l2c.total_refs 2291835 # Total number of references to valid blocks. @@ -79,12 +96,17 @@ system.l2c.overall_accesses::cpu.data 2043063 # nu system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -122,9 +144,13 @@ system.iocache.demand_accesses::total 41726 # nu system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -224,6 +250,7 @@ system.cpu.kern.ipl_used::0 0.981732 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -281,7 +308,7 @@ system.cpu.kern.mode_good::idle 171 system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode @@ -345,8 +372,11 @@ system.cpu.icache.demand_accesses::total 60050143 # nu system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,10 +432,15 @@ system.cpu.dcache.demand_accesses::total 15682061 # nu system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 6299f010e..090f52454 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -274,9 +274,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -336,10 +335,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -395,9 +393,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index dc632ce62..b3456c80f 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:25 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:45 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 7ab3bb0af..e92359043 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,23 +4,50 @@ sim_seconds 1.958647 # Nu sim_ticks 1958647095000 # Number of ticks simulated final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 669282 # Simulator instruction rate (inst/s) -host_op_rate 669282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22085281308 # Simulator tick rate (ticks/s) -host_mem_usage 295084 # Number of bytes of host memory used -host_seconds 88.69 # Real time elapsed on the host +host_inst_rate 1245422 # Simulator instruction rate (inst/s) +host_op_rate 1245421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41097010927 # Simulator tick rate (ticks/s) +host_mem_usage 295412 # Number of bytes of host memory used +host_seconds 47.66 # Real time elapsed on the host sim_insts 59355643 # Number of instructions simulated sim_ops 59355643 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30050624 # Number of bytes read from this memory -system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10333120 # Number of bytes written to this memory -system.physmem.num_reads 469541 # Number of read requests responded to by this memory -system.physmem.num_writes 161455 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15342541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 495852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 20618183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 919744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25960192 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 51456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 468416 # Number of bytes read from this memory +system.physmem.bytes_read::total 30050624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 919744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 51456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 971200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10333120 # Number of bytes written to this memory +system.physmem.bytes_written::total 10333120 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14371 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 405628 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7319 # Number of read requests responded to by this memory +system.physmem.num_reads::total 469541 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 161455 # Number of write requests responded to by this memory +system.physmem.num_writes::total 161455 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 469581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13254145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1353391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 239153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15342541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 469581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 495852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5275642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5275642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5275642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 469581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13254145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1353391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 239153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20618183 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 393576 # number of replacements system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use system.l2c.total_refs 2371449 # Total number of references to valid blocks. @@ -142,38 +169,50 @@ system.l2c.ReadReq_miss_rate::cpu0.inst 0.015693 # mi system.l2c.ReadReq_miss_rate::cpu0.data 0.275649 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.009368 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.033331 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.146292 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934476 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.903285 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.929089 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.454545 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.795699 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.706349 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.408381 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.330189 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.403596 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.015693 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.304282 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.009368 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.138621 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.179301 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.015693 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.304282 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.009368 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.138621 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.179301 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52016.667760 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 914.798206 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1575.757576 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1025.780190 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6933.333333 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4216.216216 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4674.157303 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52002.375911 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52012.540780 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52012.540780 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,44 +290,59 @@ system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015693 system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275649 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.033331 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.146287 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934476 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.903285 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.929089 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.454545 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.795699 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706349 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.408381 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330189 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.403596 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.179296 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.179296 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.717580 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.691995 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.375911 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41694 # number of replacements system.iocache.tagsinuse 0.563721 # Cycle average of tags in use @@ -324,13 +378,21 @@ system.iocache.demand_accesses::total 41726 # nu system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137701.766606 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137608.129320 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137608.129320 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked @@ -358,13 +420,21 @@ system.iocache.demand_mshr_miss_latency::total 3571932998 system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -458,6 +528,7 @@ system.cpu0.kern.ipl_used::21 1 # fr system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808938 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -515,7 +586,7 @@ system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.298893 # fraction of useful protection mode switches system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode @@ -585,11 +656,17 @@ system.cpu0.icache.demand_accesses::total 54081252 # n system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016933 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016933 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016933 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14664.130944 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14664.130944 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,11 +690,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016933 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016933 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016933 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1338438 # number of replacements system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use @@ -677,17 +760,29 @@ system.cpu0.dcache.demand_accesses::total 14308776 # n system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122512 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049821 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085698 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002134 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092785 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092785 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7251.219512 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -729,20 +824,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122512 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049821 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085698 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002134 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092785 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092785 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4251.219512 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -820,6 +930,7 @@ system.cpu1.kern.ipl_used::0 0.998923 # fr system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.710351 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -860,7 +971,7 @@ system.cpu1.kern.mode_good::idle 13 system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.599582 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode @@ -899,11 +1010,17 @@ system.cpu1.icache.demand_accesses::total 5286354 # n system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016458 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016458 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016458 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14488.908683 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14488.908683 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14488.908683 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -927,11 +1044,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 999558500 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016458 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11488.517901 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 52960 # number of replacements system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use @@ -991,17 +1114,29 @@ system.cpu1.dcache.demand_accesses::total 1677594 # n system.cpu1.dcache.overall_accesses::cpu1.data 1677594 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035676 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035676 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032042 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032042 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076923 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.076923 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.041975 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.041975 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034296 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034296 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034296 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034296 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14368.630938 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27265.853778 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13318.737271 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12704.950495 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18946.344770 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18946.344770 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1043,20 +1178,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035676 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032042 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076923 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.041975 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034296 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034296 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9704.950495 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index d5815e263..d6cd88975 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -181,9 +181,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -243,10 +242,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -302,9 +300,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 7b3033c70..33fb3404f 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:07 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:23:20 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index d0852c317..42fcfede1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,23 +4,40 @@ sim_seconds 1.915549 # Nu sim_ticks 1915548867000 # Number of ticks simulated final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 646342 # Simulator instruction rate (inst/s) -host_op_rate 646342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22054916762 # Simulator tick rate (ticks/s) -host_mem_usage 292620 # Number of bytes of host memory used -host_seconds 86.85 # Real time elapsed on the host +host_inst_rate 1238015 # Simulator instruction rate (inst/s) +host_op_rate 1238014 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42244373047 # Simulator tick rate (ticks/s) +host_mem_usage 292960 # Number of bytes of host memory used +host_seconds 45.34 # Real time elapsed on the host sim_insts 56137087 # Number of instructions simulated sim_ops 56137087 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 29663360 # Number of bytes read from this memory -system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10122368 # Number of bytes written to this memory -system.physmem.num_reads 463490 # Number of read requests responded to by this memory -system.physmem.num_writes 158162 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 943040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 26067904 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652416 # Number of bytes read from this memory +system.physmem.bytes_read::total 29663360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 943040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 943040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10122368 # Number of bytes written to this memory +system.physmem.bytes_written::total 10122368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 14735 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 407311 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41444 # Number of read requests responded to by this memory +system.physmem.num_reads::total 463490 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 158162 # Number of write requests responded to by this memory +system.physmem.num_writes::total 158162 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 492308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13608582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1384677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15485567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 492308 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 492308 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5284317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5284317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5284317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 492308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13608582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1384677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20769884 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 389289 # number of replacements system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use system.l2c.total_refs 2311163 # Total number of references to valid blocks. @@ -92,20 +109,30 @@ system.l2c.overall_accesses::cpu.data 1390437 # nu system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.150967 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.538462 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.388905 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.182179 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.182179 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52016.540189 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52003.930884 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52013.009194 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52013.009194 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -150,23 +177,36 @@ system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.150967 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.538462 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.388905 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.182179 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.182179 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.522105 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.930884 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40012.996175 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.340325 # Cycle average of tags in use @@ -202,13 +242,21 @@ system.iocache.demand_accesses::total 41725 # nu system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115265.884393 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137714.208847 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137621.133709 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137621.133709 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked @@ -236,13 +284,21 @@ system.iocache.demand_mshr_miss_latency::total 3572392988 system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -332,6 +388,7 @@ system.cpu.kern.ipl_used::0 0.981746 # fr system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814116 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -389,7 +446,7 @@ system.cpu.kern.mode_good::idle 168 system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391657 # fraction of useful protection mode switches system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode @@ -459,11 +516,17 @@ system.cpu.icache.demand_accesses::total 56148907 # nu system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016534 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016534 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016534 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14667.218001 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14667.218001 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14667.218001 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,11 +550,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 10830625500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016534 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016534 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016534 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11666.482290 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11666.482290 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1390115 # number of replacements system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use @@ -547,15 +616,25 @@ system.cpu.dcache.demand_accesses::total 15029535 # nu system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120441 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049462 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085908 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25368.690313 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30323.439631 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14300.331376 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26466.589124 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26466.589124 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,18 +672,31 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120441 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049462 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085908 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22368.647754 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27323.439631 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11300.331376 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index b18e2b725..31269f9bd 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -299,9 +300,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -360,10 +360,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -775,9 +774,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 17a6394ef..be4dcf157 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:25:17 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 911653589000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 96669edc4..002831edb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,32 +4,90 @@ sim_seconds 0.911654 # Nu sim_ticks 911653589000 # Number of ticks simulated final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1682178 # Simulator instruction rate (inst/s) -host_op_rate 2174115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25299801897 # Simulator tick rate (ticks/s) -host_mem_usage 379752 # Number of bytes of host memory used -host_seconds 36.03 # Real time elapsed on the host +host_inst_rate 1520101 # Simulator instruction rate (inst/s) +host_op_rate 1964640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22862175544 # Simulator tick rate (ticks/s) +host_mem_usage 382804 # Number of bytes of host memory used +host_seconds 39.88 # Real time elapsed on the host sim_insts 60615585 # Number of instructions simulated sim_ops 78342060 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 50963556 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1003776 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10224784 # Number of bytes written to this memory -system.physmem.num_reads 5103504 # Number of read requests responded to by this memory -system.physmem.num_writes 869236 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 55902326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1101050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 11215646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 67117972 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 75 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 75 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 75 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 661924 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6760756 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 341852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3873968 # Number of bytes read from this memory +system.physmem.bytes_read::total 50963556 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 661924 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 341852 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1003776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7197696 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 10224784 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16561 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 105709 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 60557 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5103504 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 112464 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory +system.physmem.num_writes::total 869236 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 726070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7415926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 374980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4249386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 55902326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 726070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 374980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1101050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7895209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11215646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7895209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 726070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 7434574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 374980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7551175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67117972 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 127935 # number of replacements system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use system.l2c.total_refs 1477463 # Total number of references to valid blocks. @@ -175,12 +233,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003715 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011465 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.014612 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.073080 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.027957 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.882345 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805848 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.855220 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.845087 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.655949 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.765972 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.590549 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.604811 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.595343 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.003625 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.020038 # miss rate for demand accesses @@ -189,6 +251,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003715 system.l2c.demand_miss_rate::cpu1.itb.walker 0.011465 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.014612 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.274157 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.123526 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.003625 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.020038 # miss rate for overall accesses @@ -197,6 +260,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003715 system.l2c.overall_miss_rate::cpu1.itb.walker 0.011465 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.014612 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.274157 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.123526 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,8 +372,11 @@ system.cpu0.icache.demand_accesses::total 34685670 # n system.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014349 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014349 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014349 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,11 +434,17 @@ system.cpu0.dcache.demand_accesses::total 14721592 # n system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.030010 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.027741 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054599 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040342 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028976 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028976 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,8 +550,11 @@ system.cpu1.icache.demand_accesses::total 26945412 # n system.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013596 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013596 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013596 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -536,11 +612,17 @@ system.cpu1.dcache.demand_accesses::total 9644704 # n system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027294 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029093 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158141 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.149298 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027992 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027992 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 720edf3cb..99dc32f6e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -184,9 +185,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -245,10 +245,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -660,9 +659,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 4b3b38463..f08c091ef 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:24:24 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2332330037000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e1058fc4f..154c8ff44 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.332330 # Nu sim_ticks 2332330037000 # Number of ticks simulated final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1538399 # Simulator instruction rate (inst/s) -host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60412799239 # Simulator tick rate (ticks/s) -host_mem_usage 379756 # Number of bytes of host memory used -host_seconds 38.61 # Real time elapsed on the host +host_inst_rate 1412842 # Simulator instruction rate (inst/s) +host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55482154888 # Simulator tick rate (ticks/s) +host_mem_usage 382804 # Number of bytes of host memory used +host_seconds 42.04 # Real time elapsed on the host sim_insts 59392246 # Number of instructions simulated sim_ops 76665494 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 122661296 # Number of bytes read from this memory -system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9590216 # Number of bytes written to this memory -system.physmem.num_reads 14137091 # Number of read requests responded to by this memory -system.physmem.num_writes 856679 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory +system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory +system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 117012 # number of replacements system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use system.l2c.total_refs 1527554 # Total number of references to valid blocks. @@ -112,16 +143,21 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -233,8 +269,11 @@ system.cpu.icache.demand_accesses::total 60406063 # nu system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,10 +329,15 @@ system.cpu.dcache.demand_accesses::total 23757776 # nu system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index e58e54e5c..08257cec9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -291,9 +292,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -352,10 +352,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -767,9 +766,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index d6c8fa18c..dc9f6d387 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:26:08 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1169707043000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 4dc707863..c1f17df29 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,32 +4,90 @@ sim_seconds 1.169707 # Nu sim_ticks 1169707043000 # Number of ticks simulated final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 754175 # Simulator instruction rate (inst/s) -host_op_rate 964493 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14598169556 # Simulator tick rate (ticks/s) -host_mem_usage 379804 # Number of bytes of host memory used -host_seconds 80.13 # Real time elapsed on the host +host_inst_rate 657704 # Simulator instruction rate (inst/s) +host_op_rate 841119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12730829062 # Simulator tick rate (ticks/s) +host_mem_usage 382856 # Number of bytes of host memory used +host_seconds 91.88 # Real time elapsed on the host sim_insts 60429704 # Number of instructions simulated sim_ops 77281862 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 61898788 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10078928 # Number of bytes written to this memory -system.physmem.num_reads 6478591 # Number of read requests responded to by this memory -system.physmem.num_writes 867017 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 534756 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5211316 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 470236 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5348464 # Number of bytes read from this memory +system.physmem.bytes_read::total 61898788 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 534756 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 470236 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1004992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7051584 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 10078928 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14574 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 81499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 83596 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6478591 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 110181 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 867017 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43029277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 547 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 457171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4455232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 402012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4572482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52918197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457171 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 402012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 859183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6028504 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14534 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2573588 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8616626 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6028504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43029277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4469765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 402012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7146070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 61534823 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 125934 # number of replacements system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use system.l2c.total_refs 1500548 # Total number of references to valid blocks. @@ -211,12 +269,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028163 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.826789 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.710105 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.587311 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses @@ -225,6 +287,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.122213 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses @@ -233,6 +296,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.122213 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency @@ -241,12 +305,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52152.561534 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 7361.740598 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 8935.230618 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52082.720239 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency @@ -255,6 +323,7 @@ system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52096.107637 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency @@ -263,6 +332,7 @@ system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52096.107637 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -372,12 +442,16 @@ system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.028163 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.826789 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710105 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.587311 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses @@ -386,6 +460,7 @@ system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.122213 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses @@ -394,6 +469,7 @@ system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.122213 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency @@ -402,12 +478,16 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40153.009531 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40051.711668 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40039.254171 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40082.720239 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency @@ -416,6 +496,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency @@ -424,16 +505,20 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -541,11 +626,17 @@ system.cpu0.icache.demand_accesses::total 29439615 # n system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013882 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013882 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013882 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14826.735750 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14826.735750 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,13 +664,21 @@ system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013882 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013882 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013882 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11823.686947 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 335831 # number of replacements system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use @@ -639,17 +738,29 @@ system.cpu0.dcache.demand_accesses::total 12319714 # n system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033860 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025969 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060456 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047493 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030342 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030342 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9145.766345 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23054.541807 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23054.541807 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,20 +802,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033860 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025969 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060456 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047474 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030342 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030342 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.558127 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6149.443774 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -806,11 +932,17 @@ system.cpu1.icache.demand_accesses::total 32286236 # n system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14686.743809 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14686.743809 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,13 +970,21 @@ system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014087 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014087 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11684.088965 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 294642 # number of replacements system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use @@ -904,17 +1044,29 @@ system.cpu1.dcache.demand_accesses::total 12098117 # n system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.024175 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030209 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119732 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104658 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026659 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026659 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14503.858110 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 35153.999575 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11199.721298 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7579.207411 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24134.585035 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24134.585035 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -956,20 +1108,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024175 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030209 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119732 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104604 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026659 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026659 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.721298 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4583.110196 # average StoreCondReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -990,7 +1157,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index bdfa88421..6a942652a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -180,9 +181,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -241,10 +241,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -656,9 +655,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index db3a98367..b6cf436ae 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:36:42 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:25:42 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2591419000000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index c192aecc6..20ffbfc50 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.591419 # Nu sim_ticks 2591419000000 # Number of ticks simulated final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 632591 # Simulator instruction rate (inst/s) -host_op_rate 807921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27699122939 # Simulator tick rate (ticks/s) -host_mem_usage 380048 # Number of bytes of host memory used -host_seconds 93.56 # Real time elapsed on the host +host_inst_rate 555808 # Simulator instruction rate (inst/s) +host_op_rate 709857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24337050134 # Simulator tick rate (ticks/s) +host_mem_usage 383104 # Number of bytes of host memory used +host_seconds 106.48 # Real time elapsed on the host sim_insts 59182652 # Number of instructions simulated sim_ops 75585847 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 133632176 # Number of bytes read from this memory -system.physmem.bytes_inst_read 955744 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9600072 # Number of bytes written to this memory -system.physmem.num_reads 15512735 # Number of read requests responded to by this memory -system.physmem.num_writes 856893 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51567182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 368811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3704562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55271744 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 955744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9990864 # Number of bytes read from this memory +system.physmem.bytes_read::total 133632176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 955744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 955744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6584000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 9600072 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 21136 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15512735 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102875 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856893 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47342167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 368811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3855364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51567182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 368811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 368811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2540693 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1163869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3704562 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2540693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47342167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 368811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5019233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55271744 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 117210 # number of replacements system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use system.l2c.total_refs 1536782 # Total number of references to valid blocks. @@ -131,30 +162,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002518 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003377 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016996 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.044928 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.025341 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991025 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991025 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.568473 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.568473 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.002518 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.003377 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.016996 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.252085 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.115451 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.002518 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.003377 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.016996 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.252085 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.115451 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52203.925620 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52113.632350 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52155.074026 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 362.243121 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 362.243121 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52071.302204 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52071.302204 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52086.639310 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52203.925620 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52075.861413 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52086.639310 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,35 +256,48 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002518 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.044928 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.025341 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991025 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.568473 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568473 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.115451 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.115451 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40154.867958 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40054.684779 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40071.298651 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -351,11 +405,17 @@ system.cpu.icache.demand_accesses::total 60464458 # nu system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14703.491239 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14703.491239 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14703.491239 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,13 +443,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.697734 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 627094 # number of replacements system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use @@ -445,15 +513,25 @@ system.cpu.dcache.demand_accesses::total 23787844 # nu system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027178 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024500 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045914 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026027 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15831.273549 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38111.071410 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16292.930625 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24845.068079 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24845.068079 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -491,18 +569,31 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027178 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024500 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045914 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026027 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625 # average LoadLockedReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -523,7 +614,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index a62c40c07..0d2987eae 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:41 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 344f40088..82168f91d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,23 +4,48 @@ sim_seconds 5.112043 # Nu sim_ticks 5112043255000 # Number of ticks simulated final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 704165 # Simulator instruction rate (inst/s) -host_op_rate 1441828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18015373871 # Simulator tick rate (ticks/s) -host_mem_usage 378116 # Number of bytes of host memory used -host_seconds 283.76 # Real time elapsed on the host +host_inst_rate 1304311 # Simulator instruction rate (inst/s) +host_op_rate 2670670 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33369516688 # Simulator tick rate (ticks/s) +host_mem_usage 357276 # Number of bytes of host memory used +host_seconds 153.20 # Real time elapsed on the host sim_insts 199813913 # Number of instructions simulated sim_ops 409133277 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15568704 # Number of bytes read from this memory -system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory -system.physmem.bytes_written 12232896 # Number of bytes written to this memory -system.physmem.num_reads 243261 # Number of read requests responded to by this memory -system.physmem.num_writes 191139 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3045495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 190283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2392956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 5438452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::pc.south_bridge.ide 2786624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 972736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11807616 # Number of bytes read from this memory +system.physmem.bytes_read::total 15568704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 972736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 972736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 12232896 # Number of bytes written to this memory +system.physmem.bytes_written::total 12232896 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 43541 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 15199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 184494 # Number of read requests responded to by this memory +system.physmem.num_reads::total 243261 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 191139 # Number of write requests responded to by this memory +system.physmem.num_writes::total 191139 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 545110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 190283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2309764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3045495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 190283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 190283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2392956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2392956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2392956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 545110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 190283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2309764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5438452 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 164044 # number of replacements system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use system.l2c.total_refs 3332458 # Total number of references to valid blocks. @@ -103,16 +128,21 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.026559 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.982995 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.461240 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.082838 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.082838 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -150,9 +180,13 @@ system.iocache.demand_accesses::total 47625 # nu system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -228,8 +262,11 @@ system.cpu.icache.demand_accesses::total 244157091 # nu system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -273,8 +310,11 @@ system.cpu.itb_walker_cache.demand_accesses::total 12227 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349939 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.349881 # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.349881 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,8 +354,11 @@ system.cpu.dtb_walker_cache.demand_accesses::total 21808 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409620 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409620 # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409620 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -361,9 +404,13 @@ system.cpu.dcache.demand_accesses::total 21764019 # nu system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 70b899ba9..d30404a01 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:05:12 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 92c083c66..9cc951eb3 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,23 +4,48 @@ sim_seconds 5.195470 # Nu sim_ticks 5195470393000 # Number of ticks simulated final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 435377 # Simulator instruction rate (inst/s) -host_op_rate 835677 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16374771456 # Simulator tick rate (ticks/s) -host_mem_usage 374904 # Number of bytes of host memory used -host_seconds 317.29 # Real time elapsed on the host +host_inst_rate 792632 # Simulator instruction rate (inst/s) +host_op_rate 1521406 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29811367673 # Simulator tick rate (ticks/s) +host_mem_usage 354100 # Number of bytes of host memory used +host_seconds 174.28 # Real time elapsed on the host sim_insts 138138472 # Number of instructions simulated sim_ops 265147881 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13764096 # Number of bytes read from this memory -system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10427072 # Number of bytes written to this memory -system.physmem.num_reads 215064 # Number of read requests responded to by this memory -system.physmem.num_writes 162923 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2649249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 187548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2006954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 4656204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::pc.south_bridge.ide 2876352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 974400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9911872 # Number of bytes read from this memory +system.physmem.bytes_read::total 13764096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 974400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 974400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10427072 # Number of bytes written to this memory +system.physmem.bytes_written::total 10427072 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 15225 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 154873 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215064 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 162923 # Number of write requests responded to by this memory +system.physmem.num_writes::total 162923 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 553627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 187548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1907791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2649249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 187548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 187548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2006954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2006954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2006954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 553627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 187548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1907791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4656204 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 136133 # number of replacements system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use system.l2c.total_refs 3363370 # Total number of references to valid blocks. @@ -122,30 +147,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001987 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003286 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.019307 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.027160 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.024110 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.810539 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.810539 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.383769 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383769 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.001987 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.003286 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.019307 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.095954 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.070620 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.001987 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.003286 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.019307 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.095954 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.070620 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52255.016722 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 24673.484295 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52004.897310 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52079.246541 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52079.246541 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,33 +239,46 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001987 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027160 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.024110 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.810539 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.810539 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383769 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383769 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.070620 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.070620 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40254.652764 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40254.930606 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40004.868185 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40079.117884 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47510 # number of replacements system.iocache.tagsinuse 0.120586 # Cycle average of tags in use @@ -266,13 +314,21 @@ system.iocache.demand_accesses::total 47564 # nu system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126274.800948 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 136801.779966 # average WriteReq miss latency system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 136614.983853 # average overall miss latency system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 136614.983853 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked @@ -300,13 +356,21 @@ system.iocache.demand_mshr_miss_latency::total 4024343976 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 4024343976 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74249.973934 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 84796.168622 # average WriteReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -378,11 +442,17 @@ system.cpu.icache.demand_accesses::total 159222590 # nu system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004953 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004953 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.004953 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14812.203135 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14812.203135 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14812.203135 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,11 +476,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 9314744000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004953 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.004953 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.004953 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.878733 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3754 # number of replacements system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use @@ -450,11 +526,17 @@ system.cpu.itb_walker_cache.demand_accesses::total 12223 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376565 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.376503 # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.376503 # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11042.372881 # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11042.372881 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11042.372881 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,11 +560,17 @@ system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376565 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376503 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376503 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8042.372881 # average ReadReq mshr miss latency system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.replacements 7704 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use @@ -518,11 +606,17 @@ system.cpu.dtb_walker_cache.demand_accesses::total 21947 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405340 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405340 # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405340 # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11678.900629 # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11678.900629 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11678.900629 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,11 +640,17 @@ system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.405340 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.405340 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.405340 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8678.844424 # average ReadReq mshr miss latency system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1623424 # number of replacements system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use @@ -594,13 +694,21 @@ system.cpu.dcache.demand_accesses::total 21635359 # nu system.cpu.dcache.overall_accesses::cpu.data 21635359 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098647 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098647 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037778 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037778 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.075163 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075163 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.075163 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075163 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15144.526649 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30172.881044 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18058.802043 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18058.802043 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,16 +742,27 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098647 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037778 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.075163 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.075163 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12144.494227 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27172.847747 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15058.769451 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index fdc643fe0..ab2a707ae 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -11,7 +11,7 @@ mem_mode=atomic memories=drivesys.physmem num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/n/piton/z/nate/work/m5/work/configs/boot/netperf-server.rcS +readfile=/tmp/gem5.ali/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -138,9 +138,8 @@ master=drivesys.membus.slave[3] slave=drivesys.iobus.master[29] [drivesys.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -150,10 +149,9 @@ master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fa slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma [drivesys.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -745,7 +743,7 @@ mem_mode=atomic memories=testsys.physmem num_work_ids=16 pal=/dist/m5/system/binaries/ts_osfpal -readfile=/n/piton/z/nate/work/m5/work/configs/boot/netperf-stream-client.rcS +readfile=/tmp/gem5.ali/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -872,9 +870,8 @@ master=testsys.membus.slave[3] slave=testsys.iobus.master[29] [testsys.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=true @@ -884,10 +881,9 @@ master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_ slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma [testsys.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr index 7390a9ac7..22a941a4b 100755 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr @@ -1,5 +1,7 @@ warn: Sockets disabled, not accepting terminal connections +warn: CoherentBus testsys.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections +warn: CoherentBus drivesys.membus has no snooping ports attached! warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Obsolete M5 ivlb instruction encountered. diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index 03a60d922..b25f011d8 100755 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:38:53 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:20:01 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 7cbeb04be..99c7b577c 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,23 +4,42 @@ sim_seconds 0.200001 # Nu sim_ticks 200000789468 # Number of ticks simulated final_tick 4300236018046 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158529438 # Simulator instruction rate (inst/s) -host_op_rate 158527026 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115976612682 # Simulator tick rate (ticks/s) -host_mem_usage 480288 # Number of bytes of host memory used -host_seconds 1.72 # Real time elapsed on the host +host_inst_rate 165824466 # Simulator instruction rate (inst/s) +host_op_rate 165822505 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121314189503 # Simulator tick rate (ticks/s) +host_mem_usage 480536 # Number of bytes of host memory used +host_seconds 1.65 # Real time elapsed on the host sim_insts 273374833 # Number of instructions simulated sim_ops 273374833 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read 19104208 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read 14257548 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written 3887982 # Number of bytes written to this memory -testsys.physmem.num_reads 4226224 # Number of read requests responded to by this memory -testsys.physmem.num_writes 504418 # Number of write requests responded to by this memory -testsys.physmem.num_other 0 # Number of other requests responded to by this memory -testsys.physmem.bw_read 95520663 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read 71287459 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write 19439833 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total 114960496 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bytes_read::cpu.inst 14257548 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 4845244 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 1416 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 19104208 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 14257548 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 14257548 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 3887080 # Number of bytes written to this memory +testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory +testsys.physmem.bytes_written::total 3887982 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 3564387 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 661796 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 41 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 4226224 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 504387 # Number of write requests responded to by this memory +testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory +testsys.physmem.num_writes::total 504418 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 71287459 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 24226124 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 7080 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 95520663 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 71287459 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 71287459 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 19435323 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::tsunami.ethernet 4510 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::total 19439833 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 71287459 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 43661448 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 11590 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 114960496 # Total bandwidth to/from this memory (bytes/s) testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -109,6 +128,7 @@ testsys.cpu.kern.ipl_used::0 0.998814 # fr testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::31 0.716615 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.839651 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed @@ -150,7 +170,7 @@ testsys.cpu.kern.mode_good::idle 5 testsys.cpu.kern.mode_switch_good::kernel 0.595086 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::total 1.608210 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::total 0.614373 # fraction of useful protection mode switches testsys.cpu.kern.mode_ticks::kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::user 1065606 1.23% 3.32% # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 83963628 96.68% 100.00% # number of ticks spent at the given mode @@ -204,16 +224,35 @@ testsys.tsunami.ethernet.totalRxOrn 0 # to testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post testsys.tsunami.ethernet.postedInterrupts 15 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read 10620314 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read 7834952 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written 1607724 # Number of bytes written to this memory -drivesys.physmem.num_reads 2352907 # Number of read requests responded to by this memory -drivesys.physmem.num_writes 230617 # Number of write requests responded to by this memory -drivesys.physmem.num_other 0 # Number of other requests responded to by this memory -drivesys.physmem.bw_read 53101360 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read 39174605 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write 8038588 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total 61139949 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bytes_read::cpu.inst 7834952 # Number of bytes read from this memory +drivesys.physmem.bytes_read::cpu.data 2784156 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 1206 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 10620314 # Number of bytes read from this memory +drivesys.physmem.bytes_inst_read::cpu.inst 7834952 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_inst_read::total 7834952 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_written::cpu.data 1606660 # Number of bytes written to this memory +drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory +drivesys.physmem.bytes_written::total 1607724 # Number of bytes written to this memory +drivesys.physmem.num_reads::cpu.inst 1958738 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::cpu.data 394136 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 33 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 2352907 # Number of read requests responded to by this memory +drivesys.physmem.num_writes::cpu.data 230580 # Number of write requests responded to by this memory +drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory +drivesys.physmem.num_writes::total 230617 # Number of write requests responded to by this memory +drivesys.physmem.bw_read::cpu.inst 39174605 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 13920725 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 6030 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 53101360 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 39174605 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 39174605 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 8033268 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::tsunami.ethernet 5320 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::total 8038588 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 39174605 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 21953993 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 11350 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 61139949 # Total bandwidth to/from this memory (bytes/s) drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -302,6 +341,7 @@ drivesys.cpu.kern.ipl_used::0 1 # fr drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::31 0.426624 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::total 0.618707 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed @@ -333,7 +373,7 @@ drivesys.cpu.kern.mode_good::idle 3 drivesys.cpu.kern.mode_switch_good::kernel 0.632184 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::idle 0.013761 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::total 1.645945 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::total 0.440882 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks::kernel 263256 0.24% 0.24% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::user 1278343 1.15% 1.39% # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 109686421 98.61% 100.00% # number of ticks spent at the given mode @@ -395,19 +435,13 @@ sim_seconds 0.000001 # Nu sim_ticks 785978 # Number of ticks simulated final_tick 4300236804024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 518678770918 # Simulator instruction rate (inst/s) -host_op_rate 495238879650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1368243673 # Simulator tick rate (ticks/s) -host_mem_usage 480288 # Number of bytes of host memory used +host_inst_rate 831242365640 # Simulator instruction rate (inst/s) +host_op_rate 739004692869 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2025669508 # Simulator tick rate (ticks/s) +host_mem_usage 480536 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host sim_insts 273374833 # Number of instructions simulated sim_ops 273374833 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read 0 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written 0 # Number of bytes written to this memory -testsys.physmem.num_reads 0 # Number of read requests responded to by this memory -testsys.physmem.num_writes 0 # Number of write requests responded to by this memory -testsys.physmem.num_other 0 # Number of other requests responded to by this memory testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -522,12 +556,6 @@ testsys.tsunami.ethernet.totalRxOrn 0 # to testsys.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read 0 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written 0 # Number of bytes written to this memory -drivesys.physmem.num_reads 0 # Number of read requests responded to by this memory -drivesys.physmem.num_writes 0 # Number of write requests responded to by this memory -drivesys.physmem.num_other 0 # Number of other requests responded to by this memory drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index 1a7fdb0b3..5cc0911e9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index 69eabeb32..b9f1a2caf 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:08 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:15:31 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index c4f4b062b..6887d118d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000021 # Nu sim_ticks 21234500 # Number of ticks simulated final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 37422 # Simulator instruction rate (inst/s) -host_op_rate 37415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 124041463 # Simulator tick rate (ticks/s) -host_mem_usage 214024 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 73768 # Simulator instruction rate (inst/s) +host_op_rate 73752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 244499363 # Simulator tick rate (ticks/s) +host_mem_usage 214444 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30016 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 469 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1413548706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 907202901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1413548706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory +system.physmem.bytes_read::total 30016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 469 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 907202901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 506345805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1413548706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 907202901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 907202901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 907202901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 506345805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1413548706 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -155,11 +162,17 @@ system.cpu.icache.demand_accesses::total 908 # nu system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55267.142857 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55267.142857 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55267.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,11 +200,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 16051500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.662252 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use @@ -235,13 +254,21 @@ system.cpu.dcache.demand_accesses::total 2050 # nu system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081857 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289017 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.169268 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.169268 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56778.350515 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54220 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54935.158501 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54935.158501 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -275,13 +302,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 9022500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53821.052632 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53554.794521 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use @@ -335,18 +370,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 168 system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52277.777778 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52349.315068 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52288.912580 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52288.912580 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,18 +422,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40092.171717 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40308.219178 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index f1e336f90..280f44c05 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index a5a801059..bcee17b83 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:05 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:03:27 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index ff51eef95..e9f17ec08 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000012 # Nu sim_ticks 12450500 # Number of ticks simulated final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42940 # Simulator instruction rate (inst/s) -host_op_rate 42933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83690683 # Simulator tick rate (ticks/s) -host_mem_usage 215012 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 73568 # Simulator instruction rate (inst/s) +host_op_rate 73552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 143373020 # Simulator tick rate (ticks/s) +host_mem_usage 215332 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 31360 # Number of bytes read from this memory -system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 490 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory +system.physmem.bytes_read::total 31360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory +system.physmem.num_reads::total 490 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -356,11 +363,17 @@ system.cpu.icache.demand_accesses::total 2367 # nu system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,11 +401,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 11133500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use @@ -436,13 +455,21 @@ system.cpu.dcache.demand_accesses::total 2744 # nu system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,13 +503,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6297500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064140 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064140 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use @@ -536,18 +571,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 176 system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997613 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34424.489796 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34424.489796 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,18 +623,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini index 73aad5a2d..6e91910a0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout index fcc8cf92e..1bf93074b 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:46:44 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index d2827f261..d49eba0fa 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 3215000 # Number of ticks simulated final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 399216 # Simulator instruction rate (inst/s) -host_op_rate 398861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 200076048 # Simulator tick rate (ticks/s) -host_mem_usage 204908 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 1264163 # Simulator instruction rate (inst/s) +host_op_rate 1259559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 630191855 # Simulator tick rate (ticks/s) +host_mem_usage 205200 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10718506998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7980093313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 2082737170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12801244168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7980093313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2738413686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10718506998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7980093313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7980093313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2082737170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2082737170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7980093313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4821150855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12801244168 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index ad599d493..a36a875c9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:34 +Real time: Jun/04/2012 13:42:36 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.34 -Virtual_time_in_minutes: 0.00566667 -Virtual_time_in_hours: 9.44444e-05 -Virtual_time_in_days: 3.93519e-06 +Virtual_time_in_seconds: 0.43 +Virtual_time_in_minutes: 0.00716667 +Virtual_time_in_hours: 0.000119444 +Virtual_time_in_days: 4.97685e-06 Ruby_current_time: 279353 Ruby_start_time: 0 Ruby_cycles: 279353 -mbytes_resident: 48.7227 -mbytes_total: 220.605 -resident_ratio: 0.220859 +mbytes_resident: 49.4727 +mbytes_total: 221.031 +resident_ratio: 0.223827 ruby_cycles_executed: [ 279354 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12930 -page_faults: 0 +page_reclaims: 13079 +page_faults: 9 swaps: 0 -block_inputs: 8 -block_outputs: 88 +block_inputs: 1264 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout index 5a83168a9..0c7f2991f 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 13:42:35 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index f4fb755b0..bae589857 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000279 # Nu sim_ticks 279353 # Number of ticks simulated final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 40898 # Simulator instruction rate (inst/s) -host_op_rate 40895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1783759 # Simulator tick rate (ticks/s) -host_mem_usage 225904 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 12119 # Simulator instruction rate (inst/s) +host_op_rate 12118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 528605 # Simulator tick rate (ticks/s) +host_mem_usage 226340 # Number of bytes of host memory used +host_seconds 0.53 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 123356470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 91840789 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 23969673 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 147326143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91840789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 31515681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 123356470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91840789 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91840789 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 23969673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 23969673 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91840789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 55485354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 147326143 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 122dbb303..cc70c5701 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:38 +Real time: Jun/04/2012 14:41:05 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.36 -Virtual_time_in_minutes: 0.006 -Virtual_time_in_hours: 0.0001 -Virtual_time_in_days: 4.16667e-06 +Virtual_time_in_seconds: 0.44 +Virtual_time_in_minutes: 0.00733333 +Virtual_time_in_hours: 0.000122222 +Virtual_time_in_days: 5.09259e-06 Ruby_current_time: 223694 Ruby_start_time: 0 Ruby_cycles: 223694 -mbytes_resident: 48.6758 -mbytes_total: 220.844 -resident_ratio: 0.220408 +mbytes_resident: 49.4922 +mbytes_total: 221.148 +resident_ratio: 0.223796 ruby_cycles_executed: [ 223695 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12940 -page_faults: 0 +page_reclaims: 13086 +page_faults: 12 swaps: 0 -block_inputs: 8 -block_outputs: 88 +block_inputs: 1728 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index 4a55f22f7..691f6347c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:04 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index b6ec472df..ddb3e7d12 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000224 # Nu sim_ticks 223694 # Number of ticks simulated final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 36304 # Simulator instruction rate (inst/s) -host_op_rate 36301 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1267928 # Simulator tick rate (ticks/s) -host_mem_usage 226148 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 30014 # Simulator instruction rate (inst/s) +host_op_rate 30012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1048235 # Simulator tick rate (ticks/s) +host_mem_usage 226460 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 154049729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 114692392 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 29933749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 183983477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 114692392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39357336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 154049729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 114692392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 114692392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 29933749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 29933749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 114692392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 69291085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 183983477 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 75506a0a9..7f8f438c6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:41 +Real time: Jun/04/2012 14:42:12 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.3 -Virtual_time_in_minutes: 0.005 -Virtual_time_in_hours: 8.33333e-05 -Virtual_time_in_days: 3.47222e-06 +Virtual_time_in_seconds: 0.35 +Virtual_time_in_minutes: 0.00583333 +Virtual_time_in_hours: 9.72222e-05 +Virtual_time_in_days: 4.05093e-06 Ruby_current_time: 231701 Ruby_start_time: 0 Ruby_cycles: 231701 -mbytes_resident: 46.9062 -mbytes_total: 219.027 -resident_ratio: 0.214157 +mbytes_resident: 47.9062 +mbytes_total: 219.422 +resident_ratio: 0.218329 ruby_cycles_executed: [ 231702 ] @@ -127,11 +127,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12491 -page_faults: 0 +page_reclaims: 12630 +page_faults: 12 swaps: 0 -block_inputs: 16 -block_outputs: 88 +block_inputs: 1736 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index b67f551de..63d892f7f 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:41 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:12 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 4bd1591ab..9ad88fcd3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000232 # Nu sim_ticks 231701 # Number of ticks simulated final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 57269 # Simulator instruction rate (inst/s) -host_op_rate 57262 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2071522 # Simulator tick rate (ticks/s) -host_mem_usage 224288 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 50012 # Simulator instruction rate (inst/s) +host_op_rate 50005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1808952 # Simulator tick rate (ticks/s) +host_mem_usage 224692 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 148726160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 110728914 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 28899314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 177625474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 110728914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37997246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 148726160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 110728914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 110728914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 28899314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 28899314 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 110728914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66896561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177625474 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats index 24c3821ed..68ec07392 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:31 +Real time: Jun/04/2012 13:41:27 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.31 -Virtual_time_in_minutes: 0.00516667 -Virtual_time_in_hours: 8.61111e-05 -Virtual_time_in_days: 3.58796e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 208400 Ruby_start_time: 0 Ruby_cycles: 208400 -mbytes_resident: 46.2461 -mbytes_total: 218.586 -resident_ratio: 0.211569 +mbytes_resident: 47.2969 +mbytes_total: 218.926 +resident_ratio: 0.216041 ruby_cycles_executed: [ 208401 ] @@ -126,11 +126,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12336 -page_faults: 10 +page_reclaims: 12505 +page_faults: 5 swaps: 0 -block_inputs: 1632 -block_outputs: 88 +block_inputs: 1000 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 7aaac31e8..f1ba4ed84 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:41:27 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 30017b1e1..842792d27 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000208 # Nu sim_ticks 208400 # Number of ticks simulated final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 60692 # Simulator instruction rate (inst/s) -host_op_rate 60683 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1974491 # Simulator tick rate (ticks/s) -host_mem_usage 223836 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 52133 # Simulator instruction rate (inst/s) +host_op_rate 52125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1696034 # Simulator tick rate (ticks/s) +host_mem_usage 224184 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 165355086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 123109405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 32130518 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 197485605 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 123109405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 42245681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 165355086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 123109405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 123109405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 32130518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 32130518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 123109405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 74376200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 197485605 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats index e165866f9..dd0f48010 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:37:08 +Real time: Jun/04/2012 13:42:47 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.5 -Virtual_time_in_minutes: 0.00833333 -Virtual_time_in_hours: 0.000138889 -Virtual_time_in_days: 5.78704e-06 +Virtual_time_in_seconds: 0.35 +Virtual_time_in_minutes: 0.00583333 +Virtual_time_in_hours: 9.72222e-05 +Virtual_time_in_days: 4.05093e-06 Ruby_current_time: 342698 Ruby_start_time: 0 Ruby_cycles: 342698 -mbytes_resident: 47.6289 -mbytes_total: 219.488 -resident_ratio: 0.217 +mbytes_resident: 48.4648 +mbytes_total: 219.84 +resident_ratio: 0.220455 ruby_cycles_executed: [ 342699 ] @@ -122,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12667 +page_reclaims: 12835 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout index 5e2ce6170..0b4993316 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:08 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:42:46 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 333553551..a6b69bd54 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000343 # Nu sim_ticks 342698 # Number of ticks simulated final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 30902 # Simulator instruction rate (inst/s) -host_op_rate 30898 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1653235 # Simulator tick rate (ticks/s) -host_mem_usage 224760 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 17946 # Simulator instruction rate (inst/s) +host_op_rate 17945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 960252 # Simulator tick rate (ticks/s) +host_mem_usage 225120 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 34460 # Number of bytes read from this memory -system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 6696 # Number of bytes written to this memory -system.physmem.num_reads 7599 # Number of read requests responded to by this memory -system.physmem.num_writes 865 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 100555008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 74864750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 19539069 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 120094077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.physmem.bytes_written::total 6696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.physmem.num_writes::total 865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 74864750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 25690258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 100555008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 74864750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74864750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 19539069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 19539069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 74864750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45229327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 120094077 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index 2cc7bb879..b0aed7d88 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index 87ec501fc..00df1b420 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:42:48 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:52:31 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index cd14cede6..0370e845f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000033 # Nu sim_ticks 33007000 # Number of ticks simulated final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236370 # Simulator instruction rate (inst/s) -host_op_rate 236114 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1215776788 # Simulator tick rate (ticks/s) -host_mem_usage 213800 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 524144 # Simulator instruction rate (inst/s) +host_op_rate 523337 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2693393609 # Simulator tick rate (ticks/s) +host_mem_usage 214140 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28544 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 446 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory +system.physmem.bytes_read::total 28544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 446 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 539037174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 325749084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 864786257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 539037174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 539037174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 539037174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 325749084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 864786257 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total 6415 # nu system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.043492 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.043492 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.043492 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 14745000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043492 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.043492 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.043492 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use @@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total 2050 # nu system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,13 +242,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 8904000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use @@ -275,18 +310,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 168 system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,18 +362,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index e812354d2..3b6b2b818 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 992260cf4..157d28a7a 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:16 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:45:03 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 28a756060..119328db2 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000007 # Nu sim_ticks 7015000 # Number of ticks simulated final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31687 # Simulator instruction rate (inst/s) -host_op_rate 31676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93063477 # Simulator tick rate (ticks/s) -host_mem_usage 214220 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 16156 # Simulator instruction rate (inst/s) +host_op_rate 16154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47467285 # Simulator tick rate (ticks/s) +host_mem_usage 214556 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 17600 # Number of bytes read from this memory -system.physmem.bytes_inst_read 12096 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 275 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2508909480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1724305061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2508909480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 12096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5504 # Number of bytes read from this memory +system.physmem.bytes_read::total 17600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 12096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 12096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 189 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 86 # Number of read requests responded to by this memory +system.physmem.num_reads::total 275 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1724305061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 784604419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2508909480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1724305061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 784604419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2508909480 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -355,11 +362,17 @@ system.cpu.icache.demand_accesses::total 1067 # nu system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.234302 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.234302 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.234302 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35830 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35830 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35830 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,11 +400,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 6695500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177132 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.177132 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.177132 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35425.925926 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use @@ -435,13 +454,21 @@ system.cpu.dcache.demand_accesses::total 972 # nu system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.157817 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184156 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184156 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34359.813084 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39111.111111 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36270.949721 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36270.949721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,13 +502,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3078500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.091445 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.088477 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.088477 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35564.516129 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36395.833333 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use @@ -529,18 +564,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 86 system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34340.637450 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34666.666667 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34369.090909 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34369.090909 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,18 +616,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.410359 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31562.500000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 4f5452325..198cad098 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr index 31ae36f2e..bcbfa5445 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout index d7b73cec1..4dbe62d94 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:01 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:15:42 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 2f22610c9..cc1232526 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 381497 # Simulator instruction rate (inst/s) -host_op_rate 379897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 190598632 # Simulator tick rate (ticks/s) -host_mem_usage 204064 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 760610 # Simulator instruction rate (inst/s) +host_op_rate 756680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379104629 # Simulator tick rate (ticks/s) +host_mem_usage 204432 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 10293641618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7969171484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1586127168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11879768786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7969171484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2324470135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10293641618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7969171484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7969171484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1586127168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1586127168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index bda71aafd..5ef992e40 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:34 +Real time: Jun/04/2012 13:42:36 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.24 -Virtual_time_in_minutes: 0.004 -Virtual_time_in_hours: 6.66667e-05 -Virtual_time_in_days: 2.77778e-06 +Virtual_time_in_seconds: 0.31 +Virtual_time_in_minutes: 0.00516667 +Virtual_time_in_hours: 8.61111e-05 +Virtual_time_in_days: 3.58796e-06 Ruby_current_time: 104867 Ruby_start_time: 0 Ruby_cycles: 104867 -mbytes_resident: 45.8906 -mbytes_total: 218.43 -resident_ratio: 0.210093 +mbytes_resident: 46.8984 +mbytes_total: 218.785 +resident_ratio: 0.214358 ruby_cycles_executed: [ 104868 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12254 -page_faults: 0 +page_reclaims: 12410 +page_faults: 4 swaps: 0 -block_inputs: 0 -block_outputs: 88 +block_inputs: 480 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index 59ad2cc4d..d8d70a93e 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 13:42:35 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index bd57039cb..748d8a973 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000105 # Nu sim_ticks 104867 # Number of ticks simulated final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 38145 # Simulator instruction rate (inst/s) -host_op_rate 38137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1551633 # Simulator tick rate (ticks/s) -host_mem_usage 223676 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 4864 # Simulator instruction rate (inst/s) +host_op_rate 4864 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197908 # Simulator tick rate (ticks/s) +host_mem_usage 224040 # Number of bytes of host memory used +host_seconds 0.53 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 127361324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 98601085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 19624858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 146986182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 98601085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28760239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 127361324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 98601085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 98601085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 19624858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 19624858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 98601085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48385097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 146986182 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 232722c59..0769bb48a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:38 +Real time: Jun/04/2012 14:41:15 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 +Virtual_time_in_seconds: 0.3 +Virtual_time_in_minutes: 0.005 +Virtual_time_in_hours: 8.33333e-05 +Virtual_time_in_days: 3.47222e-06 Ruby_current_time: 85418 Ruby_start_time: 0 Ruby_cycles: 85418 -mbytes_resident: 46.1016 -mbytes_total: 218.602 -resident_ratio: 0.210893 +mbytes_resident: 46.9141 +mbytes_total: 218.969 +resident_ratio: 0.21425 ruby_cycles_executed: [ 85419 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12263 +page_reclaims: 12428 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 80 +block_outputs: 88 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index fe8db74fc..dc8b54148 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:15 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 5143cdcae..07e9173f4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000085 # Nu sim_ticks 85418 # Number of ticks simulated final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 33831 # Simulator instruction rate (inst/s) -host_op_rate 33824 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1120953 # Simulator tick rate (ticks/s) -host_mem_usage 223852 # Number of bytes of host memory used +host_inst_rate 30509 # Simulator instruction rate (inst/s) +host_op_rate 30502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010829 # Simulator tick rate (ticks/s) +host_mem_usage 224228 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 156360486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 121051769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 24093282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 180453769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 121051769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35308717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 156360486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 121051769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 121051769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 24093282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24093282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats index a538bb5ac..1584bb895 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:42 +Real time: Jun/04/2012 14:42:22 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.23 -Virtual_time_in_minutes: 0.00383333 -Virtual_time_in_hours: 6.38889e-05 -Virtual_time_in_days: 2.66204e-06 +Virtual_time_in_seconds: 0.27 +Virtual_time_in_minutes: 0.0045 +Virtual_time_in_hours: 7.5e-05 +Virtual_time_in_days: 3.125e-06 Ruby_current_time: 87899 Ruby_start_time: 0 Ruby_cycles: 87899 -mbytes_resident: 45.1094 -mbytes_total: 217.598 -resident_ratio: 0.207306 +mbytes_resident: 46.1055 +mbytes_total: 217.996 +resident_ratio: 0.211497 ruby_cycles_executed: [ 87900 ] @@ -127,11 +127,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12024 +page_reclaims: 12179 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 88 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index f849b0d8f..3e1c7a0df 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:41 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:22 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 253fc28f1..0b4d202c9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000088 # Nu sim_ticks 87899 # Number of ticks simulated final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 46491 # Simulator instruction rate (inst/s) -host_op_rate 46479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1584970 # Simulator tick rate (ticks/s) -host_mem_usage 222824 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 49141 # Simulator instruction rate (inst/s) +host_op_rate 49125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1675041 # Simulator tick rate (ticks/s) +host_mem_usage 223232 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 151947121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 117635013 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 23413236 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 175360357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 117635013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34312108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 151947121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 117635013 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 117635013 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 23413236 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 23413236 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 117635013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57725344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 175360357 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 6835e2100..f062dbc78 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:31 +Real time: Jun/04/2012 13:42:34 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.24 -Virtual_time_in_minutes: 0.004 -Virtual_time_in_hours: 6.66667e-05 -Virtual_time_in_days: 2.77778e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 78448 Ruby_start_time: 0 Ruby_cycles: 78448 -mbytes_resident: 44.707 -mbytes_total: 217.324 -resident_ratio: 0.205716 +mbytes_resident: 45.7539 +mbytes_total: 217.664 +resident_ratio: 0.210204 ruby_cycles_executed: [ 78449 ] @@ -126,11 +126,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11920 -page_faults: 3 +page_reclaims: 12072 +page_faults: 20 swaps: 0 -block_inputs: 824 -block_outputs: 88 +block_inputs: 2944 +block_outputs: 96 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 7b52a0c21..423daf7c7 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index f21155c2f..002b923d5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000078 # Nu sim_ticks 78448 # Number of ticks simulated final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 48255 # Simulator instruction rate (inst/s) -host_op_rate 48240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1468118 # Simulator tick rate (ticks/s) -host_mem_usage 222544 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 9618 # Simulator instruction rate (inst/s) +host_op_rate 9618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292754 # Simulator tick rate (ticks/s) +host_mem_usage 222892 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 170252906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 131807057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 26233938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 196486845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 131807057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38445849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 170252906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 131807057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 131807057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 26233938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26233938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 131807057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64679788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 196486845 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats index cc4333b9c..0115257b7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:37:51 +Real time: Jun/04/2012 14:06:25 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.4 -Virtual_time_in_minutes: 0.00666667 -Virtual_time_in_hours: 0.000111111 -Virtual_time_in_days: 4.62963e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 Ruby_current_time: 123378 Ruby_start_time: 0 Ruby_cycles: 123378 -mbytes_resident: 45.0547 -mbytes_total: 217.531 -resident_ratio: 0.207118 +mbytes_resident: 46.1406 +mbytes_total: 217.871 +resident_ratio: 0.211779 ruby_cycles_executed: [ 123379 ] @@ -122,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12045 +page_reclaims: 12216 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 6ae96cee0..ef2e2d974 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:51 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:06:24 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 6c31e7bc8..d4f9035ad 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000123 # Nu sim_ticks 123378 # Number of ticks simulated final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23789 # Simulator instruction rate (inst/s) -host_op_rate 23782 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1138300 # Simulator tick rate (ticks/s) -host_mem_usage 222756 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 56001 # Simulator instruction rate (inst/s) +host_op_rate 55979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2679090 # Simulator tick rate (ticks/s) +host_mem_usage 223104 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2058 # Number of bytes written to this memory -system.physmem.num_reads 3000 # Number of read requests responded to by this memory -system.physmem.num_writes 294 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 108252687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 83807486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 16680445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 124933132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory +system.physmem.bytes_read::total 13356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory +system.physmem.bytes_written::total 2058 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 83807486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24445201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 108252687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 83807486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 83807486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 16680445 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16680445 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 83807486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 41125646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 124933132 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 1cfaa4239..3d54d7382 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index 194a972c4..803a08b4e 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:39:41 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 2a4818376..fab613981 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000017 # Nu sim_ticks 16769000 # Number of ticks simulated final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149101 # Simulator instruction rate (inst/s) -host_op_rate 148981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 968734693 # Simulator tick rate (ticks/s) -host_mem_usage 212944 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 308591 # Simulator instruction rate (inst/s) +host_op_rate 307918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1999557615 # Simulator tick rate (ticks/s) +host_mem_usage 213304 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15680 # Number of bytes read from this memory -system.physmem.bytes_inst_read 10432 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 245 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 935058739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 935058739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory +system.physmem.bytes_read::total 15680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory +system.physmem.num_reads::total 245 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 622100304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 312958435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 935058739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 622100304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 622100304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 622100304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 312958435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 935058739 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -109,11 +116,17 @@ system.cpu.icache.demand_accesses::total 2586 # nu system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,11 +148,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 8639000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use @@ -183,13 +202,21 @@ system.cpu.dcache.demand_accesses::total 709 # nu system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,13 +242,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4346000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use @@ -269,18 +304,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 82 system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -313,18 +356,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 34353ab5e..d0f59b4b6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -551,9 +551,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -584,9 +583,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index a7713ed58..9fb63a7a7 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:23:41 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 7aa4a6157..ea50665b2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000010 # Nu sim_ticks 10303500 # Number of ticks simulated final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20985 # Simulator instruction rate (inst/s) -host_op_rate 26178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46991642 # Simulator tick rate (ticks/s) -host_mem_usage 229632 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 43907 # Simulator instruction rate (inst/s) +host_op_rate 54769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98312554 # Simulator tick rate (ticks/s) +host_mem_usage 230064 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25664 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 401 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory +system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 401 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -410,11 +417,17 @@ system.cpu.icache.demand_accesses::total 2031 # nu system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,11 +455,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 9833500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use @@ -502,15 +521,25 @@ system.cpu.dcache.demand_accesses::total 2879 # nu system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,13 +575,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4693500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use @@ -609,18 +646,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 149 system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -659,18 +704,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 816c7ba86..693c71c0c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -525,9 +524,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index fa47f77da..fc15b65e3 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:23:30 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 82d7d38dc..85d0d7401 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000010 # Nu sim_ticks 10303500 # Number of ticks simulated final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29431 # Simulator instruction rate (inst/s) -host_op_rate 36712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65901409 # Simulator tick rate (ticks/s) -host_mem_usage 229344 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 49511 # Simulator instruction rate (inst/s) +host_op_rate 61757 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110854808 # Simulator tick rate (ticks/s) +host_mem_usage 229756 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25664 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 401 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory +system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 401 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -365,11 +372,17 @@ system.cpu.icache.demand_accesses::total 2031 # nu system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -397,11 +410,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 9833500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use @@ -457,15 +476,25 @@ system.cpu.dcache.demand_accesses::total 2879 # nu system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,13 +530,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4693500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use @@ -564,18 +601,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 149 system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -614,18 +659,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 151e2cd8c..f9ef190bc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -166,9 +166,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 435d1afac..a8cf8ab9b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:24:03 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 1b101d03e..a4d8f3fa5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 415244 # Simulator instruction rate (inst/s) -host_op_rate 516464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 258032084 # Simulator tick rate (ticks/s) -host_mem_usage 219364 # Number of bytes of host memory used +host_inst_rate 760705 # Simulator instruction rate (inst/s) +host_op_rate 946184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 472746039 # Simulator tick rate (ticks/s) +host_mem_usage 219832 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3648 # Number of bytes written to this memory -system.physmem.num_reads 5771 # Number of read requests responded to by this memory -system.physmem.num_writes 924 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory +system.physmem.bytes_read::total 22944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory +system.physmem.bytes_written::total 3648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory +system.physmem.num_writes::total 924 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index da6096ffc..10416c8b5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -112,9 +112,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 73791bcc0..f818842dc 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:23:52 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index da264e87e..44b5714ac 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 249779 # Simulator instruction rate (inst/s) -host_op_rate 311187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155712783 # Simulator tick rate (ticks/s) -host_mem_usage 219320 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 577592 # Simulator instruction rate (inst/s) +host_op_rate 718947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 359450620 # Simulator tick rate (ticks/s) +host_mem_usage 219740 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3648 # Number of bytes written to this memory -system.physmem.num_reads 5771 # Number of read requests responded to by this memory -system.physmem.num_writes 924 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory +system.physmem.bytes_read::total 22944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory +system.physmem.bytes_written::total 3648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory +system.physmem.num_writes::total 924 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 91f39c039..89402c0d8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -194,9 +193,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index f409a27fc..a6d6adcc2 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:24:13 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 55e20828c..0449db647 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000026 # Nu sim_ticks 26361000 # Number of ticks simulated final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148609 # Simulator instruction rate (inst/s) -host_op_rate 184448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 855039933 # Simulator tick rate (ticks/s) -host_mem_usage 228200 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 366471 # Simulator instruction rate (inst/s) +host_op_rate 454532 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2105652624 # Simulator tick rate (ticks/s) +host_mem_usage 228652 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4574 # Number of instructions simulated sim_ops 5682 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 22400 # Number of bytes read from this memory -system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 350 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 849740146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 546261523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 849740146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory +system.physmem.bytes_read::total 22400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 350 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 546261523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 303478624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 849740146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546261523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546261523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546261523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 303478624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 849740146 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -119,11 +126,17 @@ system.cpu.icache.demand_accesses::total 4614 # nu system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052232 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052232 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53211.618257 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53211.618257 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -145,11 +158,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12101000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052232 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052232 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use @@ -201,13 +220,21 @@ system.cpu.dcache.demand_accesses::total 2060 # nu system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085440 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.068447 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.068447 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51234.042553 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51234.042553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -233,13 +260,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 6801000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085440 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.068447 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.068447 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use @@ -296,18 +331,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 141 system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,18 +383,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index 6db06c5ff..ee123d638 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 8cbac12cb..40197f717 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:16 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 2d3519846..705e8dbde 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000020 # Nu sim_ticks 19775000 # Number of ticks simulated final_tick 19775000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83973 # Simulator instruction rate (inst/s) -host_op_rate 83956 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 284866754 # Simulator tick rate (ticks/s) -host_mem_usage 214812 # Number of bytes of host memory used +host_inst_rate 79967 # Simulator instruction rate (inst/s) +host_op_rate 79947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 271245925 # Simulator tick rate (ticks/s) +host_mem_usage 215348 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 29120 # Number of bytes read from this memory -system.physmem.bytes_inst_read 20288 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 455 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1472566372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1025941846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1472566372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 29120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20288 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 455 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1025941846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 446624526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1472566372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1025941846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1025941846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1025941846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 446624526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1472566372 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -141,11 +148,17 @@ system.cpu.icache.demand_accesses::total 754 # nu system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.454907 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.454907 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.454907 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.454907 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.454907 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.454907 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55768.221574 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55768.221574 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55768.221574 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,11 +186,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 16951500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16951500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 16951500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53139.498433 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53139.498433 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53139.498433 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.746602 # Cycle average of tags in use @@ -221,13 +240,21 @@ system.cpu.dcache.demand_accesses::total 2089 # nu system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076460 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076460 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.175135 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.120153 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.120153 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56994.382022 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55003.086420 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55709.163347 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55709.163347 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -261,13 +288,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7448000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7448000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54051.724138 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53833.333333 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53971.014493 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53971.014493 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 205.517886 # Cycle average of tags in use @@ -321,18 +356,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995074 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995624 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52400.990099 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52588.235294 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52421.978022 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52421.978022 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,18 +408,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587500 system.cpu.l2cache.overall_mshr_miss_latency::total 18305000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40215.346535 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40352.941176 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40230.769231 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40230.769231 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 5535b7c1b..a70bd3d3a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 6efd85bce..c92fa97a1 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:27 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 0f84e872e..69e82fc15 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000013 # Nu sim_ticks 12671500 # Number of ticks simulated final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56172 # Simulator instruction rate (inst/s) -host_op_rate 56163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137660070 # Simulator tick rate (ticks/s) -host_mem_usage 215596 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 63611 # Simulator instruction rate (inst/s) +host_op_rate 63597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155871053 # Simulator tick rate (ticks/s) +host_mem_usage 216124 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 483 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2439490195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1722290179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2439490195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::total 30912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1722290179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 717200016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2439490195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1722290179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1722290179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1722290179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 717200016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2439490195 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -340,11 +347,17 @@ system.cpu.icache.demand_accesses::total 2039 # nu system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.219225 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.219225 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.219225 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35591.722595 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35591.722595 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -372,11 +385,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12065000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168710 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.168710 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.168710 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use @@ -420,13 +439,21 @@ system.cpu.dcache.demand_accesses::total 2944 # nu system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065874 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.160326 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.160326 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34364.406780 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34364.406780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -460,13 +487,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5113000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045072 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048234 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048234 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use @@ -520,18 +555,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 142 system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993103 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.993827 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.993827 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34372.670807 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34372.670807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,18 +607,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993103 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993827 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993827 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini index b0d54d9f2..bb362afce 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout index 289fd9d0d..43669dc21 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:38 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 91924afa4..fa97a6f47 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2913500 # Number of ticks simulated final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 826404 # Simulator instruction rate (inst/s) -host_op_rate 824787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 411656542 # Simulator tick rate (ticks/s) -host_mem_usage 205596 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 1277439 # Simulator instruction rate (inst/s) +host_op_rate 1267147 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 631162418 # Simulator tick rate (ticks/s) +host_mem_usage 206236 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 27687 # Number of bytes read from this memory -system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3658 # Number of bytes written to this memory -system.physmem.num_reads 6992 # Number of read requests responded to by this memory -system.physmem.num_writes 925 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9503003261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 8001372919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1255534580 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10758537841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 23312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4375 # Number of bytes read from this memory +system.physmem.bytes_read::total 27687 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 3658 # Number of bytes written to this memory +system.physmem.bytes_written::total 3658 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5828 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6992 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 925 # Number of write requests responded to by this memory +system.physmem.num_writes::total 925 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8001372919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1501630342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9503003261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8001372919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8001372919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1255534580 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1255534580 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8001372919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2757164922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10758537841 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index 4fad25b5f..9ce456b52 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:59 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index b950c6483..1e3413864 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000293 # Nu sim_ticks 292960 # Number of ticks simulated final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 60937 # Simulator instruction rate (inst/s) -host_op_rate 60929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3062846 # Simulator tick rate (ticks/s) -host_mem_usage 226192 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 55490 # Simulator instruction rate (inst/s) +host_op_rate 55480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2788890 # Simulator tick rate (ticks/s) +host_mem_usage 226736 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 27687 # Number of bytes read from this memory -system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory -system.physmem.bytes_written 3658 # Number of bytes written to this memory -system.physmem.num_reads 6992 # Number of read requests responded to by this memory -system.physmem.num_writes 925 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 94507783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 79574003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 12486346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 106994129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 23312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4375 # Number of bytes read from this memory +system.physmem.bytes_read::total 27687 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 3658 # Number of bytes written to this memory +system.physmem.bytes_written::total 3658 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5828 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6992 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 925 # Number of write requests responded to by this memory +system.physmem.num_writes::total 925 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 79574003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14933779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 94507783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 79574003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 79574003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 12486346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12486346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 79574003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 27420126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106994129 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index c6b1fd816..f7cc4efef 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index 0276ca4b7..ac53df969 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:07:01 -gem5 started May 8 2012 15:36:45 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:58:11 +gem5 started Jun 4 2012 14:43:48 +gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 6c79a4c95..8f49928a9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000032 # Nu sim_ticks 32088000 # Number of ticks simulated final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 273601 # Simulator instruction rate (inst/s) -host_op_rate 273420 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1504754975 # Simulator tick rate (ticks/s) -host_mem_usage 214572 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 540307 # Simulator instruction rate (inst/s) +host_op_rate 539410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2965678153 # Simulator tick rate (ticks/s) +host_mem_usage 215020 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28096 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 439 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 28096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 439 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 600349040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 275243082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 875592122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 600349040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 600349040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 600349040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 275243082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 875592122 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -95,11 +102,17 @@ system.cpu.icache.demand_accesses::total 5829 # nu system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.051981 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.051981 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.051981 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -121,11 +134,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 15975000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.051981 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.051981 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.051981 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use @@ -169,13 +188,21 @@ system.cpu.dcache.demand_accesses::total 2089 # nu system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.074742 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.066060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.066060 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -201,13 +228,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7314000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use @@ -261,18 +296,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,18 +348,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index b22bc0367..928f0469f 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -475,9 +475,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -508,9 +507,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 7aac87cd9..b797dcfe3 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:03:54 -gem5 started May 8 2012 15:36:49 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:59:33 +gem5 started Jun 4 2012 14:44:10 +gem5 executing on zizzer command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 129f4d9d2..975867801 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000011 # Nu sim_ticks 11243500 # Number of ticks simulated final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73653 # Simulator instruction rate (inst/s) -host_op_rate 73641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 142731766 # Simulator tick rate (ticks/s) -host_mem_usage 211540 # Number of bytes of host memory used +host_inst_rate 72271 # Simulator instruction rate (inst/s) +host_op_rate 72256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140039967 # Simulator tick rate (ticks/s) +host_mem_usage 211876 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28736 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 449 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory +system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -339,11 +346,17 @@ system.cpu.icache.demand_accesses::total 1899 # nu system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,11 +384,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12417500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use @@ -419,13 +438,21 @@ system.cpu.dcache.demand_accesses::total 2615 # nu system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,13 +486,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3570000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use @@ -519,18 +554,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 99 system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,18 +606,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index 0a48b581e..aaab5c18b 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -95,9 +95,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index 4ba999389..b409adbd2 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:03:54 -gem5 started May 8 2012 15:36:50 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:59:33 +gem5 started Jun 4 2012 14:44:21 +gem5 executing on zizzer command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 87b1b3e66..c355893c5 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2900000 # Number of ticks simulated final_tick 2900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 413372 # Simulator instruction rate (inst/s) -host_op_rate 412979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 206267825 # Simulator tick rate (ticks/s) -host_mem_usage 201744 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 1223636 # Simulator instruction rate (inst/s) +host_op_rate 1219143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 607261041 # Simulator tick rate (ticks/s) +host_mem_usage 202160 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 5801 # Number of instructions simulated sim_ops 5801 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 26925 # Number of bytes read from this memory -system.physmem.bytes_inst_read 23204 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4209 # Number of bytes written to this memory -system.physmem.num_reads 6763 # Number of read requests responded to by this memory -system.physmem.num_writes 1046 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9284482759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 8001379310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1451379310 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10735862069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 23204 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3721 # Number of bytes read from this memory +system.physmem.bytes_read::total 26925 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23204 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23204 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 4209 # Number of bytes written to this memory +system.physmem.bytes_written::total 4209 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5801 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 962 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6763 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 1046 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8001379310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1283103448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9284482759 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8001379310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8001379310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1451379310 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1451379310 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8001379310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2734482759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10735862069 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 61b03b911..d62e06b17 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 19ecb4795..76c88733e 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:31 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 5aea2d352..b45b5b881 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000018 # Nu sim_ticks 18196500 # Number of ticks simulated final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72963 # Simulator instruction rate (inst/s) -host_op_rate 72948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 248531385 # Simulator tick rate (ticks/s) -host_mem_usage 221204 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 58781 # Simulator instruction rate (inst/s) +host_op_rate 58769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 200221364 # Simulator tick rate (ticks/s) +host_mem_usage 221628 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 27072 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 423 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1487758635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1016459209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1487758635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory +system.physmem.bytes_read::total 27072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18496 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1016459209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 471299426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1487758635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1016459209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1016459209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1016459209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 471299426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1487758635 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 36394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -123,11 +130,17 @@ system.cpu.icache.demand_accesses::total 1174 # nu system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.295571 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.295571 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.295571 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55063.400576 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55063.400576 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55063.400576 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -155,11 +168,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 15468000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247871 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247871 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247871 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53154.639175 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.864730 # Cycle average of tags in use @@ -203,13 +222,21 @@ system.cpu.dcache.demand_accesses::total 1389 # nu system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082402 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.417533 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.244780 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.244780 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55788.135593 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55010.676157 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55145.588235 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55145.588235 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -243,13 +270,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7193500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7193500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7193500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097192 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53074.074074 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53425.925926 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53285.185185 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53285.185185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 162.299655 # Cycle average of tags in use @@ -306,18 +341,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 135 system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.991304 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.992958 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52390.350877 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52228.395062 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52359.338061 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52359.338061 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,18 +393,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5399000 system.cpu.l2cache.overall_mshr_miss_latency::total 17002500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40195.906433 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40191.358025 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index 3550cbb34..9462bf460 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 467d94a16..a096c2705 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:41 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index a0bb29684..c78599e75 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000003 # Nu sim_ticks 2701000 # Number of ticks simulated final_tick 2701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 660534 # Simulator instruction rate (inst/s) -host_op_rate 659359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 332979355 # Simulator tick rate (ticks/s) -host_mem_usage 211860 # Number of bytes of host memory used +host_inst_rate 947128 # Simulator instruction rate (inst/s) +host_op_rate 944143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 476131381 # Simulator tick rate (ticks/s) +host_mem_usage 212364 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 26135 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5065 # Number of bytes written to this memory -system.physmem.num_reads 6099 # Number of read requests responded to by this memory -system.physmem.num_writes 673 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 9676045909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7971862273 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1875231396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 11551277305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4603 # Number of bytes read from this memory +system.physmem.bytes_read::total 26135 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21532 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21532 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 5065 # Number of bytes written to this memory +system.physmem.bytes_written::total 5065 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 716 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6099 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 673 # Number of write requests responded to by this memory +system.physmem.num_writes::total 673 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7971862273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1704183636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9676045909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7971862273 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7971862273 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1875231396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1875231396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7971862273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3579415031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11551277305 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 5403 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index 5940396eb..095eef676 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:55 +Real time: Jun/04/2012 14:44:51 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.28 -Virtual_time_in_minutes: 0.00466667 -Virtual_time_in_hours: 7.77778e-05 -Virtual_time_in_days: 3.24074e-06 +Virtual_time_in_seconds: 0.31 +Virtual_time_in_minutes: 0.00516667 +Virtual_time_in_hours: 8.61111e-05 +Virtual_time_in_days: 3.58796e-06 Ruby_current_time: 253364 Ruby_start_time: 0 Ruby_cycles: 253364 -mbytes_resident: 48.3438 -mbytes_total: 226.668 -resident_ratio: 0.21328 +mbytes_resident: 49.3359 +mbytes_total: 227.086 +resident_ratio: 0.217257 ruby_cycles_executed: [ 253365 ] @@ -122,7 +122,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12864 +page_reclaims: 13015 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index dd8a0a7b3..e4a7b2f0d 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:51 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 362724c03..2f30e2be2 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000253 # Nu sim_ticks 253364 # Number of ticks simulated final_tick 253364 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 60301 # Simulator instruction rate (inst/s) -host_op_rate 60291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2860139 # Simulator tick rate (ticks/s) -host_mem_usage 232112 # Number of bytes of host memory used +host_inst_rate 57491 # Simulator instruction rate (inst/s) +host_op_rate 57480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2726732 # Simulator tick rate (ticks/s) +host_mem_usage 232540 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 26135 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5065 # Number of bytes written to this memory -system.physmem.num_reads 6099 # Number of read requests responded to by this memory -system.physmem.num_writes 673 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 103151987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 84984449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 19991001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 123142988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4603 # Number of bytes read from this memory +system.physmem.bytes_read::total 26135 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21532 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21532 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 5065 # Number of bytes written to this memory +system.physmem.bytes_written::total 5065 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 716 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6099 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 673 # Number of write requests responded to by this memory +system.physmem.num_writes::total 673 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84984449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 18167538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103151987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84984449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84984449 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 19991001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 19991001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84984449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38158539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 123142988 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 253364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 958c9bb97..232d3350e 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index 702411d18..e4af58bc7 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:42 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index d2987c02e..3580b75db 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000028 # Nu sim_ticks 28206000 # Number of ticks simulated final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240215 # Simulator instruction rate (inst/s) -host_op_rate 240049 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1267195715 # Simulator tick rate (ticks/s) -host_mem_usage 220748 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 427855 # Simulator instruction rate (inst/s) +host_op_rate 427237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2253599179 # Simulator tick rate (ticks/s) +host_mem_usage 221156 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 24896 # Number of bytes read from this memory -system.physmem.bytes_inst_read 16320 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 389 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 882649082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 578600298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 882649082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory +system.physmem.bytes_read::total 24896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 389 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 578600298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 304048784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 882649082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 578600298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 578600298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 578600298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 304048784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 882649082 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 56412 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 5384 # nu system.cpu.icache.overall_accesses::cpu.inst 5384 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5384 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.047734 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.047734 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.047734 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047734 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.047734 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55673.151751 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55673.151751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 13537000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047734 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.047734 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.047734 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use @@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total 1389 # nu system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075419 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.097192 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097192 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097192 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097192 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55688.888889 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55688.888889 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -183,13 +210,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7113000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097192 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use @@ -246,18 +281,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 135 system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,18 +333,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index ebb140a84..19d634444 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:03:58 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 5a009d0f1..b16a10afa 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000012 # Nu sim_ticks 12198000 # Number of ticks simulated final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27776 # Simulator instruction rate (inst/s) -host_op_rate 50299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62542635 # Simulator tick rate (ticks/s) -host_mem_usage 245428 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 39950 # Simulator instruction rate (inst/s) +host_op_rate 72345 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89952499 # Simulator tick rate (ticks/s) +host_mem_usage 224288 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28864 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 451 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2366289556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1584522053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2366289556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory +system.physmem.bytes_read::total 28864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 24397 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -321,11 +328,17 @@ system.cpu.icache.demand_accesses::total 1951 # nu system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,11 +366,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 10687000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155818 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.155818 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.155818 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use @@ -401,13 +420,21 @@ system.cpu.dcache.demand_accesses::total 2556 # nu system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070900 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074726 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074726 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36376.963351 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36376.963351 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -439,13 +466,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5263500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.058294 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.058294 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use @@ -499,18 +534,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 149 system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994695 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995585 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995585 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34250 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,18 +586,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994695 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995585 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 0daaf6112..85d4b3244 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:09 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 2c5d9e840..971607574 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000006 # Nu sim_ticks 5651000 # Number of ticks simulated final_tick 5651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 8235 # Simulator instruction rate (inst/s) -host_op_rate 14913 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8590426 # Simulator tick rate (ticks/s) -host_mem_usage 234908 # Number of bytes of host memory used -host_seconds 0.66 # Real time elapsed on the host +host_inst_rate 420667 # Simulator instruction rate (inst/s) +host_op_rate 760787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 437668419 # Simulator tick rate (ticks/s) +host_mem_usage 214072 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62348 # Number of bytes read from this memory -system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7110 # Number of bytes written to this memory -system.physmem.num_reads 7966 # Number of read requests responded to by this memory -system.physmem.num_writes 934 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11033091488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 9782339409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1258184392 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12291275880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 55280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7068 # Number of bytes read from this memory +system.physmem.bytes_read::total 62348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory +system.physmem.bytes_written::total 7110 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1056 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7966 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory +system.physmem.num_writes::total 934 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9782339409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1250752079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11033091488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9782339409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9782339409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1258184392 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1258184392 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9782339409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2508936471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12291275880 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 11303 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index a0ea73428..400138927 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jun/03/2012 13:31:00 +Real time: Jun/04/2012 15:04:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.36 +Virtual_time_in_minutes: 0.006 +Virtual_time_in_hours: 0.0001 +Virtual_time_in_days: 4.16667e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 52.5547 -mbytes_total: 249.254 -resident_ratio: 0.210848 +mbytes_resident: 52.9648 +mbytes_total: 228.941 +resident_ratio: 0.232473 ruby_cycles_executed: [ 276485 ] @@ -125,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11223 +page_reclaims: 14034 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index bef47caec..781f2a777 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:30 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 436ded977..37cc5b98f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000276 # Nu sim_ticks 276484 # Number of ticks simulated final_tick 276484 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 34222 # Simulator instruction rate (inst/s) -host_op_rate 61969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1746397 # Simulator tick rate (ticks/s) -host_mem_usage 255240 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 48659 # Simulator instruction rate (inst/s) +host_op_rate 88106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2482786 # Simulator tick rate (ticks/s) +host_mem_usage 234440 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62348 # Number of bytes read from this memory -system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7110 # Number of bytes written to this memory -system.physmem.num_reads 7966 # Number of read requests responded to by this memory -system.physmem.num_writes 934 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 225503103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199939237 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 25715774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 251218877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 55280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7068 # Number of bytes read from this memory +system.physmem.bytes_read::total 62348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory +system.physmem.bytes_written::total 7110 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1056 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7966 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory +system.physmem.num_writes::total 934 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 199939237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 25563866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 225503103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199939237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199939237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 25715774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25715774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199939237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 51279640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 251218877 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 276484 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 91d5c9297..62a044b81 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:19 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 2325f81a1..1e89d36d4 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000029 # Nu sim_ticks 28768000 # Number of ticks simulated final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39729 # Simulator instruction rate (inst/s) -host_op_rate 71940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 210944443 # Simulator tick rate (ticks/s) -host_mem_usage 244104 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 318234 # Simulator instruction rate (inst/s) +host_op_rate 575684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1686451163 # Simulator tick rate (ticks/s) +host_mem_usage 223048 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 23104 # Number of bytes read from this memory -system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 361 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 803114572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 505005562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 803114572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory +system.physmem.bytes_read::total 23104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 361 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 505005562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 298109010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 803114572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 505005562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505005562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 505005562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 298109010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 803114572 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 57536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 6911 # nu system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.032991 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.032991 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.032991 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55815.789474 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12042000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032991 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.032991 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.032991 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use @@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total 1990 # nu system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052083 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084582 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067337 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067337 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -183,13 +210,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7102000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052083 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052083 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084582 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067337 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067337 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use @@ -243,18 +278,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 134 system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -287,18 +330,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 60ac42ca2..01d2e4278 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -526,9 +525,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index c897f1e4e..0e67a0bd3 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:40:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:39:51 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 244839beb..972719e56 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000014 # Nu sim_ticks 13973500 # Number of ticks simulated final_tick 13973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43715 # Simulator instruction rate (inst/s) -host_op_rate 43711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47815570 # Simulator tick rate (ticks/s) -host_mem_usage 215652 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 68487 # Simulator instruction rate (inst/s) +host_op_rate 68480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74908448 # Simulator tick rate (ticks/s) +host_mem_usage 215960 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated sim_ops 12773 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62784 # Number of bytes read from this memory -system.physmem.bytes_inst_read 40192 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 981 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 4493076180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2876301571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 4493076180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 40192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22592 # Number of bytes read from this memory +system.physmem.bytes_read::total 62784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40192 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 353 # Number of read requests responded to by this memory +system.physmem.num_reads::total 981 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2876301571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1616774609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4493076180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2876301571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2876301571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2876301571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1616774609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4493076180 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -383,7 +390,7 @@ system.cpu.iew.wb_rate::1 0.345356 # in system.cpu.iew.wb_rate::total 0.694969 # insts written-back per cycle system.cpu.iew.wb_fanout::0 0.764981 # average fanout of values written-back system.cpu.iew.wb_fanout::1 0.765796 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 1.530777 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.765387 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ @@ -500,11 +507,17 @@ system.cpu.icache.demand_accesses::total 5262 # nu system.cpu.icache.overall_accesses::cpu.inst 5262 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5262 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169707 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.169707 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.169707 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.169707 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.169707 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.169707 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35538.633819 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35538.633819 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35538.633819 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35538.633819 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,11 +545,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 22442500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22442500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 22442500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119916 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.119916 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.119916 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.561014 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35566.561014 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements @@ -582,13 +601,21 @@ system.cpu.dcache.demand_accesses::total 5717 # nu system.cpu.dcache.overall_accesses::cpu.data 5717 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 5717 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078004 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078004 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.410405 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.178590 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.178590 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.178590 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.178590 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36080.385852 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36080.385852 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31737.323944 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31737.323944 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33060.235064 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33060.235064 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -622,13 +649,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 12899000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12899000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 12899000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051919 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051919 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061746 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061746 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36751.207729 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36751.207729 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36243.150685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36243.150685 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements @@ -684,18 +719,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 353 system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995246 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.996420 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995246 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.996951 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995246 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.996951 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34452.229299 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34859.903382 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34553.293413 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34681.506849 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34681.506849 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34572.375127 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34572.375127 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -728,18 +771,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11181000 system.cpu.l2cache.overall_mshr_miss_latency::total 30840500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996420 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996951 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996951 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31304.936306 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31739.130435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31412.574850 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.191781 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.191781 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index 8b9b39b0d..b15f5671c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -176,9 +176,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -209,9 +208,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index b2566a0a7..30eeb514f 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:44:53 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 5325eaa70..73324a4d5 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000025 # Nu sim_ticks 25007500 # Number of ticks simulated final_tick 25007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55900 # Simulator instruction rate (inst/s) -host_op_rate 55897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92110077 # Simulator tick rate (ticks/s) -host_mem_usage 220976 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 72389 # Simulator instruction rate (inst/s) +host_op_rate 72383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119272701 # Simulator tick rate (ticks/s) +host_mem_usage 221376 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 27904 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19072 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 436 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1115825252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 762651205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1115825252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 27904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 436 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 762651205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 353174048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1115825252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 762651205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 762651205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 762651205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 353174048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1115825252 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 50016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -123,11 +130,17 @@ system.cpu.icache.demand_accesses::total 2970 # nu system.cpu.icache.overall_accesses::cpu.inst 2970 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2970 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123906 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123906 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.123906 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123906 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.123906 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123906 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54900.815217 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54900.815217 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54900.815217 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -155,11 +168,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 15872000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.101347 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.101347 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52730.897010 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 97.041769 # Cycle average of tags in use @@ -207,13 +226,21 @@ system.cpu.dcache.demand_accesses::total 3668 # nu system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026056 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.208044 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097601 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097601 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56577.586207 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56577.586207 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54656.666667 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54656.666667 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54967.877095 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54967.877095 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -247,13 +274,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7382000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7382000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7382000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53528.301887 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53528.301887 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53470.588235 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 196.205624 # Cycle average of tags in use @@ -307,18 +342,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994350 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995444 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52386.792453 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.625000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52264.705882 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52064.073227 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52064.073227 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,18 +394,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 system.cpu.l2cache.overall_mshr_miss_latency::total 17464500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39910.511364 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40188.235294 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 64273b3fe..e306accf8 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -474,9 +474,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -507,9 +506,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 076570d2f..f0f4b69ef 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:02 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 693d12ddb..a887522dd 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000020 # Nu sim_ticks 19744500 # Number of ticks simulated final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52427 # Simulator instruction rate (inst/s) -host_op_rate 52424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71633039 # Simulator tick rate (ticks/s) -host_mem_usage 221536 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 74885 # Simulator instruction rate (inst/s) +host_op_rate 74878 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 102311932 # Simulator tick rate (ticks/s) +host_mem_usage 222004 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated sim_ops 14449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30976 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 484 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1568841956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1095596242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1568841956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory +system.physmem.bytes_read::total 30976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory +system.physmem.num_reads::total 484 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1095596242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 473245714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1568841956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1095596242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1095596242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1095596242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 473245714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1568841956 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 39490 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -318,11 +325,17 @@ system.cpu.icache.demand_accesses::total 5506 # nu system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.088267 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.088267 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.088267 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34414.609053 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34414.609053 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,11 +363,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 11937500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061751 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.061751 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.061751 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use @@ -402,13 +421,21 @@ system.cpu.dcache.demand_accesses::total 4603 # nu system.cpu.dcache.overall_accesses::cpu.data 4603 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037330 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.114273 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.114273 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.114273 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35524.714829 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35524.714829 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,13 +469,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5223000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019930 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031718 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031718 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use @@ -502,18 +537,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 146 system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994118 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995037 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994118 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995885 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,18 +589,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 63fce3718..9dd70f314 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -94,9 +94,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr index e45cd058f..7edd901b2 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ +warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index c5ff1dac8..0a6c1bd0d 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:36:55 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:04 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index b4eb79291..a62ce7951 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,23 +4,37 @@ sim_seconds 0.000008 # Nu sim_ticks 7618500 # Number of ticks simulated final_tick 7618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147764 # Simulator instruction rate (inst/s) -host_op_rate 147721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74142280 # Simulator tick rate (ticks/s) -host_mem_usage 211580 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 949089 # Simulator instruction rate (inst/s) +host_op_rate 948034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 475431989 # Simulator tick rate (ticks/s) +host_mem_usage 212076 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 72223 # Number of bytes read from this memory -system.physmem.bytes_inst_read 60880 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9042 # Number of bytes written to this memory -system.physmem.num_reads 17446 # Number of read requests responded to by this memory -system.physmem.num_writes 1442 # Number of write requests responded to by this memory -system.physmem.num_other 6 # Number of other requests responded to by this memory -system.physmem.bw_read 9479950121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 7991074358 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1186847805 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 10666797926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 60880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11343 # Number of bytes read from this memory +system.physmem.bytes_read::total 72223 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory +system.physmem.bytes_written::total 9042 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2226 # Number of read requests responded to by this memory +system.physmem.num_reads::total 17446 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory +system.physmem.num_other::total 6 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7991074358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1488875763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9479950121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7991074358 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7991074358 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186847805 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1186847805 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7991074358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2675723568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10666797926 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 15238 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index ad6d2cdd3..cfbf65944 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -176,9 +175,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index 9346f2ccc..423d84a63 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:42:54 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:13 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index dfba79da8..f6532c6ee 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000042 # Nu sim_ticks 41800000 # Number of ticks simulated final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130693 # Simulator instruction rate (inst/s) -host_op_rate 130661 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 359830859 # Simulator tick rate (ticks/s) -host_mem_usage 220580 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 488993 # Simulator instruction rate (inst/s) +host_op_rate 488707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1345414902 # Simulator tick rate (ticks/s) +host_mem_usage 221064 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 416 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 636937799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 425645933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 636937799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory +system.physmem.bytes_read::total 26624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory +system.physmem.num_reads::total 416 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 425645933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 211291866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 636937799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 425645933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 425645933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 425645933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 211291866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 636937799 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 83600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 15221 # nu system.cpu.icache.overall_accesses::cpu.inst 15221 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 15221 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018396 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.018396 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.018396 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.018396 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.018396 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55700 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55700 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55700 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 14756000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018396 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.018396 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.018396 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use @@ -155,13 +174,21 @@ system.cpu.dcache.demand_accesses::total 3668 # nu system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023810 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.037623 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037623 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037623 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,13 +214,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7314000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use @@ -247,18 +282,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 138 system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993994 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -291,18 +334,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 5684cea4e..08b3f6997 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1768,9 +1768,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -1791,9 +1790,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 9445b3529..51784eba5 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:42:58 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:14 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 243852286..1590e3eee 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,22 +4,59 @@ sim_seconds 0.000111 # Nu sim_ticks 111402500 # Number of ticks simulated final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79928 # Simulator instruction rate (inst/s) -host_op_rate 79928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8175729 # Simulator tick rate (ticks/s) -host_mem_usage 236248 # Number of bytes of host memory used -host_seconds 13.63 # Real time elapsed on the host +host_inst_rate 133234 # Simulator instruction rate (inst/s) +host_op_rate 133234 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13628365 # Simulator tick rate (ticks/s) +host_mem_usage 236536 # Number of bytes of host memory used +host_seconds 8.17 # Real time elapsed on the host sim_insts 1089093 # Number of instructions simulated sim_ops 1089093 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 43072 # Number of bytes read from this memory -system.physmem.bytes_inst_read 29312 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 673 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 386634052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 263117973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 386634052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::total 43072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::total 673 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 208541101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97089383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 8042907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7468414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 45959471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11489868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 574493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7468414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 386634052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 208541101 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 8042907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 45959471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 574493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 263117973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 208541101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97089383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 8042907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7468414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 45959471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11489868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 574493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7468414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 386634052 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 222806 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -319,11 +356,17 @@ system.cpu0.icache.demand_accesses::total 6218 # n system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.122065 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.122065 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.122065 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38418.313570 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38418.313570 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38418.313570 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -351,11 +394,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 21891000 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.095529 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.095529 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.095529 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36853.535354 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 8 # number of replacements system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use @@ -407,15 +456,25 @@ system.cpu0.dcache.demand_accesses::total 164751 # n system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005927 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006722 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006319 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006319 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28234.343434 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44619.021978 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19025 # average SwapReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36828.036503 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36828.036503 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -455,15 +514,25 @@ system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002179 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002167 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002173 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002173 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27222.527473 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35511.363636 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16025 # average SwapReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 187393 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -765,11 +834,17 @@ system.cpu1.icache.demand_accesses::total 19809 # n system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.025493 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.025493 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.025493 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14852.475248 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14852.475248 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14852.475248 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -797,11 +872,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 5474500 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021960 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.021960 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.021960 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.057471 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use @@ -853,15 +934,25 @@ system.cpu1.dcache.demand_accesses::total 93422 # n system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009191 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003689 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006733 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006733 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20285.263158 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19269.480519 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 20770 # average SwapReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20036.565978 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20036.565978 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -901,15 +992,25 @@ system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003019 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002837 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002837 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13153.846154 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13977.064220 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17770 # average SwapReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 187102 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -1211,11 +1312,17 @@ system.cpu2.icache.demand_accesses::total 21870 # n system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.023411 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.023411 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.023411 # miss rate for overall accesses system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 21760.742188 # average ReadReq miss latency system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 21760.742188 # average overall miss latency system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 21760.742188 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1243,11 +1350,17 @@ system.cpu2.icache.demand_mshr_miss_latency::total 8467000 system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.020119 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.020119 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.020119 # mshr miss rate for overall accesses system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19243.181818 # average ReadReq mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use @@ -1299,15 +1412,25 @@ system.cpu2.dcache.demand_accesses::total 81444 # n system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009490 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004137 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.815789 # miss rate for SwapReq accesses system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007171 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007171 # miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 23413.242009 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20116.438356 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 19048.387097 # average SwapReq miss latency system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 22589.041096 # average overall miss latency system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 22589.041096 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1347,15 +1470,25 @@ system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003705 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002862 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.815789 # mshr miss rate for SwapReq accesses system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003340 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003340 # mshr miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14502.923977 # average ReadReq mshr miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15014.851485 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 16048.387097 # average SwapReq mshr miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 186832 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -1657,11 +1790,17 @@ system.cpu3.icache.demand_accesses::total 24454 # n system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.020569 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.020569 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.020569 # miss rate for overall accesses system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13604.373757 # average ReadReq miss latency system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13604.373757 # average overall miss latency system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13604.373757 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1689,11 +1828,17 @@ system.cpu3.icache.demand_mshr_miss_latency::total 4912000 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017666 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.017666 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.017666 # mshr miss rate for overall accesses system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11370.370370 # average ReadReq mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use @@ -1745,15 +1890,25 @@ system.cpu3.dcache.demand_accesses::total 74691 # n system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009688 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004755 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007618 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007618 # miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 20514.285714 # average ReadReq miss latency system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20184.563758 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 21017.543860 # average SwapReq miss latency system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 20427.943761 # average overall miss latency system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 20427.943761 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1793,15 +1948,25 @@ system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003760 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003319 # mshr miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003575 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003575 # mshr miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13196.319018 # average ReadReq mshr miss latency system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15586.538462 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 18017.543860 # average SwapReq mshr miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 441.136869 # Cycle average of tags in use @@ -1979,14 +2144,17 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # mi system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.271379 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.963855 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses @@ -1995,6 +2163,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.193182 # mi system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.315692 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses @@ -2003,6 +2172,7 @@ system.l2c.overall_miss_rate::cpu2.inst 0.193182 # mi system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.315692 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency @@ -2011,13 +2181,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 51985.428051 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1968.750000 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52480.916031 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency @@ -2026,6 +2199,7 @@ system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52080.882353 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency @@ -2034,6 +2208,7 @@ system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52080.882353 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2136,14 +2311,17 @@ system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.267919 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.963855 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses @@ -2152,6 +2330,7 @@ system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.312442 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses @@ -2160,6 +2339,7 @@ system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.312442 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency @@ -2168,14 +2348,17 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39979.704797 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.893130 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency @@ -2184,6 +2367,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency @@ -2192,6 +2376,7 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index a47e5e15d..f048ede7e 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -460,9 +460,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -483,9 +482,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index ab456df4c..7edc0f615 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:05 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:23 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index e871b4c6b..a670e1cab 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,22 +4,59 @@ sim_seconds 0.000088 # Nu sim_ticks 87713500 # Number of ticks simulated final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 523852 # Simulator instruction rate (inst/s) -host_op_rate 523839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67834135 # Simulator tick rate (ticks/s) -host_mem_usage 1149444 # Number of bytes of host memory used -host_seconds 1.29 # Real time elapsed on the host +host_inst_rate 1597903 # Simulator instruction rate (inst/s) +host_op_rate 1597833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206906108 # Simulator tick rate (ticks/s) +host_mem_usage 1149840 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host sim_insts 677340 # Number of instructions simulated sim_ops 677340 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 35776 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 559 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 407873360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 253917584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 407873360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::total 35776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::total 559 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 205760801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 120391958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45238190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 14592965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1459296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 9485427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1459296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 9485427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 407873360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205760801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45238190 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1459296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1459296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 253917584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205760801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 120391958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45238190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 14592965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1459296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 9485427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1459296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 9485427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 407873360 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 175428 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -71,8 +108,11 @@ system.cpu0.icache.demand_accesses::total 175401 # n system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002662 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002662 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002662 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -122,10 +162,15 @@ system.cpu0.dcache.demand_accesses::total 82337 # n system.cpu0.dcache.overall_accesses::cpu0.data 82337 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 82337 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002766 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.002766 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -187,8 +232,11 @@ system.cpu1.icache.demand_accesses::total 167430 # n system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -238,10 +286,15 @@ system.cpu1.dcache.demand_accesses::total 53313 # n system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004330 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005290 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005290 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,8 +356,11 @@ system.cpu2.icache.demand_accesses::total 167366 # n system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -354,10 +410,15 @@ system.cpu2.dcache.demand_accesses::total 58461 # n system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003825 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004636 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004636 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,8 +480,11 @@ system.cpu3.icache.demand_accesses::total 167301 # n system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,10 +534,15 @@ system.cpu3.dcache.demand_accesses::total 55820 # n system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003835 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004676 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004676 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -625,14 +694,17 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # mi system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.256519 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.977528 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses @@ -641,6 +713,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.005587 # mi system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.313165 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses @@ -649,6 +722,7 @@ system.l2c.overall_miss_rate::cpu2.inst 0.005587 # mi system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.313165 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 7658e05d6..cf4b383de 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -444,9 +444,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -467,9 +466,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index bd4b2c9b4..3d54c9924 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:42 -gem5 started May 8 2012 15:43:05 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:01:47 +gem5 started Jun 4 2012 14:45:33 +gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 70ef2d753..36b8c656f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,22 +4,59 @@ sim_seconds 0.000262 # Nu sim_ticks 262298000 # Number of ticks simulated final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 323904 # Simulator instruction rate (inst/s) -host_op_rate 323899 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 128274037 # Simulator tick rate (ticks/s) -host_mem_usage 231956 # Number of bytes of host memory used -host_seconds 2.05 # Real time elapsed on the host +host_inst_rate 1070900 # Simulator instruction rate (inst/s) +host_op_rate 1070867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 424091073 # Simulator tick rate (ticks/s) +host_mem_usage 232420 # Number of bytes of host memory used +host_seconds 0.62 # Real time elapsed on the host sim_insts 662307 # Number of instructions simulated sim_ops 662307 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 36608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 572 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 139566447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 86375039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 139566447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 36608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 572 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 69539226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40259552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14395840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5367940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2195976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3903957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 243997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3659959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139566447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69539226 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14395840 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2195976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 243997 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86375039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69539226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40259552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14395840 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5367940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2195976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3903957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 243997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3659959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139566447 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 524596 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +114,17 @@ system.cpu0.icache.demand_accesses::total 158416 # n system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002948 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002948 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002948 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 39665.952891 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 39665.952891 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 39665.952891 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +146,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total 17123000 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002948 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002948 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002948 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36665.952891 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use @@ -159,15 +208,25 @@ system.cpu0.dcache.demand_accesses::total 73844 # n system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003312 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007342 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29314.814815 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39207.650273 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 14884.615385 # average SwapReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34562.318841 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34562.318841 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,15 +258,25 @@ system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007342 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26314.814815 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36207.650273 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11884.615385 # average SwapReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 524596 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -265,11 +334,17 @@ system.cpu1.icache.demand_accesses::total 172358 # n system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21640.710383 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21640.710383 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21640.710383 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -291,11 +366,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total 6822000 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18639.344262 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use @@ -347,15 +428,25 @@ system.cpu1.dcache.demand_accesses::total 47806 # n system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004570 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005836 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005836 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20513.812155 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19275.510204 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20078.853047 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20078.853047 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,15 +478,25 @@ system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004570 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005836 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005836 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17513.812155 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16275.510204 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 524596 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -453,11 +554,17 @@ system.cpu2.icache.demand_accesses::total 165532 # n system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002211 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002211 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002211 # miss rate for overall accesses system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15433.060109 # average overall miss latency system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15433.060109 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,11 +586,17 @@ system.cpu2.icache.demand_mshr_miss_latency::total 4550500 system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002211 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002211 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002211 # mshr miss rate for overall accesses system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use @@ -535,15 +648,25 @@ system.cpu2.dcache.demand_accesses::total 57869 # n system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003728 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004579 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004579 # miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16198.717949 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 19119.266055 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17400 # average overall miss latency system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17400 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,15 +698,25 @@ system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003728 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004579 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004579 # mshr miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13198.717949 # average ReadReq mshr miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16119.266055 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 524596 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -641,11 +774,17 @@ system.cpu3.icache.demand_accesses::total 166163 # n system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 15072.207084 # average ReadReq miss latency system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 15072.207084 # average overall miss latency system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 15072.207084 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -667,11 +806,17 @@ system.cpu3.icache.demand_mshr_miss_latency::total 4430500 system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12072.207084 # average ReadReq mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use @@ -723,15 +868,25 @@ system.cpu3.dcache.demand_accesses::total 57168 # n system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.006988 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004635 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004635 # miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16363.057325 # average ReadReq miss latency system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19259.259259 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17543.396226 # average overall miss latency system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17543.396226 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -763,15 +918,25 @@ system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006988 # mshr miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004635 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004635 # mshr miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13363.057325 # average ReadReq mshr miss latency system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16259.259259 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3037.037037 # average SwapReq mshr miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 353.886259 # Cycle average of tags in use @@ -949,14 +1114,17 @@ system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # mi system.l2c.ReadReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.268496 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.972973 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses @@ -965,6 +1133,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.032787 # mi system.l2c.demand_miss_rate::cpu2.data 0.592593 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.592593 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.325633 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses @@ -973,6 +1142,7 @@ system.l2c.overall_miss_rate::cpu2.inst 0.032787 # mi system.l2c.overall_miss_rate::cpu2.data 0.592593 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.592593 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.325633 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency @@ -981,13 +1151,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 51844.444444 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2166.666667 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52007.042254 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency @@ -996,6 +1169,7 @@ system.l2c.demand_avg_miss_latency::cpu2.inst 51250 system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51883.445946 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency @@ -1004,6 +1178,7 @@ system.l2c.overall_avg_miss_latency::cpu2.inst 51250 system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51883.445946 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1112,14 +1287,17 @@ system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.256563 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.972973 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses @@ -1128,6 +1306,7 @@ system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.314631 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses @@ -1136,6 +1315,7 @@ system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.314631 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency @@ -1144,14 +1324,17 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.976744 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.042254 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency @@ -1160,6 +1343,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency @@ -1168,6 +1352,7 @@ system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index b44d5a4c2..1cbda9483 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:38:27 +Real time: Jun/04/2012 14:41:50 Profiler Stats -------------- -Elapsed_time_in_seconds: 113 -Elapsed_time_in_minutes: 1.88333 -Elapsed_time_in_hours: 0.0313889 -Elapsed_time_in_days: 0.00130787 +Elapsed_time_in_seconds: 88 +Elapsed_time_in_minutes: 1.46667 +Elapsed_time_in_hours: 0.0244444 +Elapsed_time_in_days: 0.00101852 -Virtual_time_in_seconds: 112.14 -Virtual_time_in_minutes: 1.869 -Virtual_time_in_hours: 0.03115 -Virtual_time_in_days: 0.00129792 +Virtual_time_in_seconds: 87.84 +Virtual_time_in_minutes: 1.464 +Virtual_time_in_hours: 0.0244 +Virtual_time_in_days: 0.00101667 Ruby_current_time: 22495354 Ruby_start_time: 0 Ruby_cycles: 22495354 -mbytes_resident: 60.2695 -mbytes_total: 361.398 -resident_ratio: 0.166768 +mbytes_resident: 61.2852 +mbytes_total: 361.766 +resident_ratio: 0.169406 ruby_cycles_executed: [ 22495355 22495355 22495355 22495355 22495355 22495355 22495355 22495355 ] @@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 3280807 average: 0.508064 | Resource Usage -------------- page_size: 4096 -user_time: 112 +user_time: 87 system_time: 0 -page_reclaims: 15932 +page_reclaims: 16135 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 232 +block_outputs: 216 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index 26548e28d..4c179bc95 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 14:40:22 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index 1ae2ff15c..c7afc7b3a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.022495 # Nu sim_ticks 22495354 # Number of ticks simulated final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 200233 # Simulator tick rate (ticks/s) -host_mem_usage 370076 # Number of bytes of host memory used -host_seconds 112.35 # Real time elapsed on the host -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 256726 # Simulator tick rate (ticks/s) +host_mem_usage 370452 # Number of bytes of host memory used +host_seconds 87.62 # Real time elapsed on the host system.cpu0.num_reads 99326 # number of read accesses completed system.cpu0.num_writes 53132 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index af42ad0ff..e3b9d4def 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -14,7 +14,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing -memories=system.funcmem system.physmem +memories=system.physmem system.funcmem num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats index cb3fdaf16..c5ae1c27c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:42:43 +Real time: Jun/04/2012 14:45:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 365 -Elapsed_time_in_minutes: 6.08333 -Elapsed_time_in_hours: 0.101389 -Elapsed_time_in_days: 0.00422454 +Elapsed_time_in_seconds: 244 +Elapsed_time_in_minutes: 4.06667 +Elapsed_time_in_hours: 0.0677778 +Elapsed_time_in_days: 0.00282407 -Virtual_time_in_seconds: 361.58 -Virtual_time_in_minutes: 6.02633 -Virtual_time_in_hours: 0.100439 -Virtual_time_in_days: 0.00418495 +Virtual_time_in_seconds: 244.12 +Virtual_time_in_minutes: 4.06867 +Virtual_time_in_hours: 0.0678111 +Virtual_time_in_days: 0.00282546 Ruby_current_time: 19400856 Ruby_start_time: 0 Ruby_cycles: 19400856 -mbytes_resident: 60.2344 -mbytes_total: 361.566 -resident_ratio: 0.166593 +mbytes_resident: 61.3008 +mbytes_total: 361.941 +resident_ratio: 0.169367 ruby_cycles_executed: [ 19400857 19400857 19400857 19400857 19400857 19400857 19400857 19400857 ] @@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 361 +user_time: 244 system_time: 0 -page_reclaims: 15956 +page_reclaims: 16161 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 448 +block_outputs: 216 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 403e6654c..ca77e3fc7 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:26 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 9aec04ac2..fcc191198 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.019401 # Nu sim_ticks 19400856 # Number of ticks simulated final_tick 19400856 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 53186 # Simulator tick rate (ticks/s) -host_mem_usage 370248 # Number of bytes of host memory used -host_seconds 364.77 # Real time elapsed on the host -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 79524 # Simulator tick rate (ticks/s) +host_mem_usage 370632 # Number of bytes of host memory used +host_seconds 243.96 # Real time elapsed on the host system.cpu0.num_reads 98844 # number of read accesses completed system.cpu0.num_writes 53478 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats index ab5cb8e9e..fe9a9f183 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:39:26 +Real time: Jun/04/2012 14:44:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 164 -Elapsed_time_in_minutes: 2.73333 -Elapsed_time_in_hours: 0.0455556 -Elapsed_time_in_days: 0.00189815 +Elapsed_time_in_seconds: 117 +Elapsed_time_in_minutes: 1.95 +Elapsed_time_in_hours: 0.0325 +Elapsed_time_in_days: 0.00135417 -Virtual_time_in_seconds: 163.7 -Virtual_time_in_minutes: 2.72833 -Virtual_time_in_hours: 0.0454722 -Virtual_time_in_days: 0.00189468 +Virtual_time_in_seconds: 117.17 +Virtual_time_in_minutes: 1.95283 +Virtual_time_in_hours: 0.0325472 +Virtual_time_in_days: 0.00135613 Ruby_current_time: 19665440 Ruby_start_time: 0 Ruby_cycles: 19665440 -mbytes_resident: 60.0117 -mbytes_total: 361.082 -resident_ratio: 0.1662 +mbytes_resident: 61.0625 +mbytes_total: 361.484 +resident_ratio: 0.168922 ruby_cycles_executed: [ 19665441 19665441 19665441 19665441 19665441 19665441 19665441 19665441 ] @@ -125,13 +125,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 163 +user_time: 117 system_time: 0 -page_reclaims: 15846 +page_reclaims: 16038 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 288 +block_outputs: 232 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index 7601ab137..4dc86aa94 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:42 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:33 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index d352be3a5..284e6ab5c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.019665 # Nu sim_ticks 19665440 # Number of ticks simulated final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 119847 # Simulator tick rate (ticks/s) -host_mem_usage 369752 # Number of bytes of host memory used -host_seconds 164.09 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 168119 # Simulator tick rate (ticks/s) +host_mem_usage 370164 # Number of bytes of host memory used +host_seconds 116.97 # Real time elapsed on the host system.cpu0.num_reads 99534 # number of read accesses completed system.cpu0.num_writes 53920 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 08a16b146..f9a059734 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:38:42 +Real time: Jun/04/2012 13:44:25 Profiler Stats -------------- -Elapsed_time_in_seconds: 131 -Elapsed_time_in_minutes: 2.18333 -Elapsed_time_in_hours: 0.0363889 -Elapsed_time_in_days: 0.0015162 +Elapsed_time_in_seconds: 111 +Elapsed_time_in_minutes: 1.85 +Elapsed_time_in_hours: 0.0308333 +Elapsed_time_in_days: 0.00128472 -Virtual_time_in_seconds: 129.82 -Virtual_time_in_minutes: 2.16367 -Virtual_time_in_hours: 0.0360611 -Virtual_time_in_days: 0.00150255 +Virtual_time_in_seconds: 111.55 +Virtual_time_in_minutes: 1.85917 +Virtual_time_in_hours: 0.0309861 +Virtual_time_in_days: 0.00129109 Ruby_current_time: 19129199 Ruby_start_time: 0 Ruby_cycles: 19129199 -mbytes_resident: 59.6641 -mbytes_total: 360.938 -resident_ratio: 0.165303 +mbytes_resident: 60.7188 +mbytes_total: 361.293 +resident_ratio: 0.16806 ruby_cycles_executed: [ 19129200 19129200 19129200 19129200 19129200 19129200 19129200 19129200 ] @@ -124,13 +124,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 129 +user_time: 111 system_time: 0 -page_reclaims: 15794 +page_reclaims: 15994 page_faults: 0 swaps: 0 -block_inputs: 16 -block_outputs: 256 +block_inputs: 0 +block_outputs: 224 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 9fc5d7446..bc60d72d3 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index cad2377ee..7c588684e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.019129 # Nu sim_ticks 19129199 # Number of ticks simulated final_tick 19129199 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 146249 # Simulator tick rate (ticks/s) -host_mem_usage 369604 # Number of bytes of host memory used -host_seconds 130.80 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 171697 # Simulator tick rate (ticks/s) +host_mem_usage 369968 # Number of bytes of host memory used +host_seconds 111.41 # Real time elapsed on the host system.cpu0.num_reads 100000 # number of read accesses completed system.cpu0.num_writes 53893 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index 379029232..ceb7b2a64 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:42:37 +Real time: Jun/04/2012 14:22:53 Profiler Stats -------------- -Elapsed_time_in_seconds: 69 -Elapsed_time_in_minutes: 1.15 -Elapsed_time_in_hours: 0.0191667 -Elapsed_time_in_days: 0.000798611 +Elapsed_time_in_seconds: 41 +Elapsed_time_in_minutes: 0.683333 +Elapsed_time_in_hours: 0.0113889 +Elapsed_time_in_days: 0.000474537 -Virtual_time_in_seconds: 68.73 -Virtual_time_in_minutes: 1.1455 -Virtual_time_in_hours: 0.0190917 -Virtual_time_in_days: 0.000795486 +Virtual_time_in_seconds: 41.24 +Virtual_time_in_minutes: 0.687333 +Virtual_time_in_hours: 0.0114556 +Virtual_time_in_days: 0.000477315 Ruby_current_time: 28725020 Ruby_start_time: 0 Ruby_cycles: 28725020 -mbytes_resident: 59.4102 -mbytes_total: 360.535 -resident_ratio: 0.164783 +mbytes_resident: 60.7461 +mbytes_total: 361.262 +resident_ratio: 0.16815 ruby_cycles_executed: [ 28725021 28725021 28725021 28725021 28725021 28725021 28725021 28725021 ] @@ -118,13 +118,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367 Resource Usage -------------- page_size: 4096 -user_time: 68 +user_time: 41 system_time: 0 -page_reclaims: 15745 -page_faults: 0 +page_reclaims: 15955 +page_faults: 2 swaps: 0 -block_inputs: 0 -block_outputs: 256 +block_inputs: 128 +block_outputs: 184 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout index 4cb3155a6..19534930d 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:28 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:22:12 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 12fdf4aa3..fbf03980e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.028725 # Nu sim_ticks 28725020 # Number of ticks simulated final_tick 28725020 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 417169 # Simulator tick rate (ticks/s) -host_mem_usage 369192 # Number of bytes of host memory used -host_seconds 68.86 # Real time elapsed on the host -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 699351 # Simulator tick rate (ticks/s) +host_mem_usage 369936 # Number of bytes of host memory used +host_seconds 41.07 # Real time elapsed on the host system.cpu0.num_reads 100000 # number of read accesses completed system.cpu0.num_writes 53147 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini index dfa7c1d18..db9f08590 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini @@ -417,9 +417,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=2 header_cycles=1 use_default_range=false @@ -440,9 +439,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=2 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index cd078a3a4..4cc5a9b4f 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:08 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:15:53 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 58bdafd11..9aa493322 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -4,24 +4,76 @@ sim_seconds 0.000263 # Nu sim_ticks 263488655 # Number of ticks simulated final_tick 263488655 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1217695 # Simulator tick rate (ticks/s) -host_mem_usage 343548 # Number of bytes of host memory used -host_seconds 216.38 # Real time elapsed on the host -system.physmem.bytes_read 4057580 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2644316 # Number of bytes written to this memory -system.physmem.num_reads 141878 # Number of read requests responded to by this memory -system.physmem.num_writes 83744 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15399448602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write 10035786930 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 25435235532 # Total bandwidth to/from this memory (bytes/s) -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 1558675 # Simulator tick rate (ticks/s) +host_mem_usage 343952 # Number of bytes of host memory used +host_seconds 169.05 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 504730 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 513456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 503221 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 509883 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 511138 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 501110 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 514161 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 499881 # Number of bytes read from this memory +system.physmem.bytes_read::total 4057580 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 2601216 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5426 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5325 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5406 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5362 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5419 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5298 # Number of bytes written to this memory +system.physmem.bytes_written::total 2644316 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 17740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 17646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 17743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 17727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 17848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 17774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 17658 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 17742 # Number of read requests responded to by this memory +system.physmem.num_reads::total 141878 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 40644 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5325 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5406 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5472 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5362 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5419 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5298 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83744 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 1915566346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 1948683521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 1909839344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 1935123165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 1939886178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 1901827614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 1951359158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 1897163276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15399448602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9872212525 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 20463879 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 20592917 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 20209599 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 20517012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 20767498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 20350022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 20566350 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 20107128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10035786930 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9872212525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 1936030225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 1969276438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 1930048943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 1955640177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 1960653676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 1922177636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 1971925509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 1917270404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 25435235532 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 76856 # number of replacements system.l2c.tagsinuse 657.714518 # Cycle average of tags in use system.l2c.total_refs 139150 # Total number of references to valid blocks. @@ -239,6 +291,7 @@ system.l2c.ReadReq_miss_rate::cpu4 0.333248 # mi system.l2c.ReadReq_miss_rate::cpu5 0.329978 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu6 0.326978 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu7 0.323177 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.329797 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0 0.782485 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1 0.792266 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2 0.783810 # miss rate for UpgradeReq accesses @@ -247,6 +300,7 @@ system.l2c.UpgradeReq_miss_rate::cpu4 0.786706 # mi system.l2c.UpgradeReq_miss_rate::cpu5 0.778363 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu6 0.796469 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu7 0.793778 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.786224 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0 0.661926 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1 0.673235 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2 0.653281 # miss rate for ReadExReq accesses @@ -255,6 +309,7 @@ system.l2c.ReadExReq_miss_rate::cpu4 0.664491 # mi system.l2c.ReadExReq_miss_rate::cpu5 0.652798 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu6 0.668049 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu7 0.659537 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.662584 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0 0.445972 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1 0.454617 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2 0.441105 # miss rate for demand accesses @@ -263,6 +318,7 @@ system.l2c.demand_miss_rate::cpu4 0.449498 # mi system.l2c.demand_miss_rate::cpu5 0.443762 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu6 0.448253 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu7 0.443015 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.446844 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0 0.445972 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1 0.454617 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2 0.441105 # miss rate for overall accesses @@ -271,6 +327,7 @@ system.l2c.overall_miss_rate::cpu4 0.449498 # mi system.l2c.overall_miss_rate::cpu5 0.443762 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu6 0.448253 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu7 0.443015 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.446844 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0 49621.728646 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1 49611.864250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2 49597.501643 # average ReadReq miss latency @@ -279,6 +336,7 @@ system.l2c.ReadReq_avg_miss_latency::cpu4 49599.928365 # a system.l2c.ReadReq_avg_miss_latency::cpu5 49643.596206 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu6 49631.254810 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu7 49598.091273 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 49615.022334 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0 19851.816910 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1 21112.256571 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2 20319.092146 # average UpgradeReq miss latency @@ -287,6 +345,7 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu4 19801.786885 system.l2c.UpgradeReq_avg_miss_latency::cpu5 20703.490160 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu6 19895.977833 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu7 20570.862832 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 20284.674323 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0 49777.383282 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1 49793.150482 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2 49738.978778 # average ReadExReq miss latency @@ -295,6 +354,7 @@ system.l2c.ReadExReq_avg_miss_latency::cpu4 49860.337739 # system.l2c.ReadExReq_avg_miss_latency::cpu5 49799.127293 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu6 49869.189138 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu7 49835.864788 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 49817.112873 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0 49702.290320 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1 49707.635619 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2 49670.188364 # average overall miss latency @@ -303,6 +363,7 @@ system.l2c.demand_avg_miss_latency::cpu4 49735.031412 # av system.l2c.demand_avg_miss_latency::cpu5 49724.239243 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu6 49757.341526 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu7 49724.208008 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 49720.418420 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0 49702.290320 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1 49707.635619 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2 49670.188364 # average overall miss latency @@ -311,6 +372,7 @@ system.l2c.overall_avg_miss_latency::cpu4 49735.031412 # a system.l2c.overall_avg_miss_latency::cpu5 49724.239243 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu6 49757.341526 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu7 49724.208008 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 49720.418420 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked @@ -491,6 +553,7 @@ system.l2c.ReadReq_mshr_miss_rate::cpu4 0.325355 # ms system.l2c.ReadReq_mshr_miss_rate::cpu5 0.322622 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu6 0.319987 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu7 0.315803 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.322103 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.779153 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.788299 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.781386 # mshr miss rate for UpgradeReq accesses @@ -499,6 +562,7 @@ system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.783730 # system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.775969 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.794017 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.790768 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.783235 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.653800 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.664889 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.644556 # mshr miss rate for ReadExReq accesses @@ -507,6 +571,7 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.657963 # m system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.644263 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.661368 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.652291 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.655102 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for demand accesses @@ -515,6 +580,7 @@ system.l2c.demand_mshr_miss_rate::cpu4 0.442084 # ms system.l2c.demand_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.439225 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for overall accesses @@ -523,6 +589,7 @@ system.l2c.overall_mshr_miss_rate::cpu4 0.442084 # ms system.l2c.overall_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.439225 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40002.870565 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40002.812241 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40002.878951 # average ReadReq mshr miss latency @@ -531,6 +598,7 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 39994.796252 system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.304600 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 39986.772989 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39994.349857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39998.692981 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40002.238852 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39976.872327 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40002.032258 # average UpgradeReq mshr miss latency @@ -539,6 +607,7 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40002.012025 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40002.360888 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40002.153799 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40002.212563 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39998.991821 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40002.446171 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39995.372559 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39994.920452 # average ReadExReq mshr miss latency @@ -547,6 +616,7 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40002.443543 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40002.523827 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40002.451411 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 40002.352804 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000.638344 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency @@ -555,6 +625,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu4 39998.790654 system.l2c.demand_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency @@ -563,6 +634,7 @@ system.l2c.overall_avg_mshr_miss_latency::cpu4 39998.790654 system.l2c.overall_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -571,6 +643,7 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -579,6 +652,7 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency @@ -587,6 +661,7 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.num_reads 99815 # number of read accesses completed system.cpu0.num_writes 53929 # number of write accesses completed @@ -633,13 +708,21 @@ system.cpu0.l1c.demand_accesses::total 69070 # nu system.cpu0.l1c.overall_accesses::cpu0 69070 # number of overall (read+write) accesses system.cpu0.l1c.overall_accesses::total 69070 # number of overall (read+write) accesses system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.831953 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.831953 # miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956350 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956350 # miss rate for WriteReq accesses system.cpu0.l1c.demand_miss_rate::cpu0 0.875648 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.875648 # miss rate for demand accesses system.cpu0.l1c.overall_miss_rate::cpu0 0.875648 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.875648 # miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 34863.258698 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 34863.258698 # average ReadReq miss latency system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 43164.731144 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 43164.731144 # average WriteReq miss latency system.cpu0.l1c.demand_avg_miss_latency::cpu0 38047.907822 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 38047.907822 # average overall miss latency system.cpu0.l1c.overall_avg_miss_latency::cpu0 38047.907822 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 38047.907822 # average overall miss latency system.cpu0.l1c.blocked_cycles::no_mshrs 253845135 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.blocked::no_mshrs 69110 # number of cycles access was blocked @@ -673,16 +756,27 @@ system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 569723237 system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1464301869 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1464301869 # number of overall MSHR uncacheable cycles system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.831953 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.831953 # mshr miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956350 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956350 # mshr miss rate for WriteReq accesses system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.875648 # mshr miss rate for demand accesses system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.875648 # mshr miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 33859.391373 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 33859.391373 # average ReadReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 42160.816007 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 42160.816007 # average WriteReq mshr miss latency system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.num_reads 98493 # number of read accesses completed system.cpu1.num_writes 53671 # number of write accesses completed @@ -729,13 +823,21 @@ system.cpu1.l1c.demand_accesses::total 68880 # nu system.cpu1.l1c.overall_accesses::cpu1 68880 # number of overall (read+write) accesses system.cpu1.l1c.overall_accesses::total 68880 # number of overall (read+write) accesses system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.833202 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.833202 # miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956206 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.956206 # miss rate for WriteReq accesses system.cpu1.l1c.demand_miss_rate::cpu1 0.876670 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.876670 # miss rate for demand accesses system.cpu1.l1c.overall_miss_rate::cpu1 0.876670 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.876670 # miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 35078.437375 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 35078.437375 # average ReadReq miss latency system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 43578.818690 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 43578.818690 # average WriteReq miss latency system.cpu1.l1c.demand_avg_miss_latency::cpu1 38354.853291 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 38354.853291 # average overall miss latency system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 38354.853291 # average overall miss latency system.cpu1.l1c.blocked_cycles::no_mshrs 253325402 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.blocked::no_mshrs 68822 # number of cycles access was blocked @@ -769,16 +871,27 @@ system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 578327433 system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1455446592 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1455446592 # number of overall MSHR uncacheable cycles system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.833202 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.833202 # mshr miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956206 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956206 # mshr miss rate for WriteReq accesses system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.876670 # mshr miss rate for demand accesses system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.876670 # mshr miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 34074.598410 # average ReadReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 42575.032825 # average WriteReq mshr miss latency system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.num_reads 99149 # number of read accesses completed system.cpu2.num_writes 53185 # number of write accesses completed @@ -825,13 +938,21 @@ system.cpu2.l1c.demand_accesses::total 68674 # nu system.cpu2.l1c.overall_accesses::cpu2 68674 # number of overall (read+write) accesses system.cpu2.l1c.overall_accesses::total 68674 # number of overall (read+write) accesses system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.830590 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.830590 # miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955373 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955373 # miss rate for WriteReq accesses system.cpu2.l1c.demand_miss_rate::cpu2 0.874115 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.874115 # miss rate for demand accesses system.cpu2.l1c.overall_miss_rate::cpu2 0.874115 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.874115 # miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 35074.051314 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 35074.051314 # average ReadReq miss latency system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 43332.089535 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 43332.089535 # average WriteReq miss latency system.cpu2.l1c.demand_avg_miss_latency::cpu2 38222.283080 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 38222.283080 # average overall miss latency system.cpu2.l1c.overall_avg_miss_latency::cpu2 38222.283080 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 38222.283080 # average overall miss latency system.cpu2.l1c.blocked_cycles::no_mshrs 254303447 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.blocked::no_mshrs 68698 # number of cycles access was blocked @@ -865,16 +986,27 @@ system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 566349170 system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1466862226 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1466862226 # number of overall MSHR uncacheable cycles system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.830590 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.830590 # mshr miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955373 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955373 # mshr miss rate for WriteReq accesses system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.874115 # mshr miss rate for demand accesses system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.874115 # mshr miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 34070.157684 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 34070.157684 # average ReadReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 42328.351409 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 42328.351409 # average WriteReq mshr miss latency system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.num_reads 99588 # number of read accesses completed system.cpu3.num_writes 53645 # number of write accesses completed @@ -921,13 +1053,21 @@ system.cpu3.l1c.demand_accesses::total 69040 # nu system.cpu3.l1c.overall_accesses::cpu3 69040 # number of overall (read+write) accesses system.cpu3.l1c.overall_accesses::total 69040 # number of overall (read+write) accesses system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.831214 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.831214 # miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955632 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955632 # miss rate for WriteReq accesses system.cpu3.l1c.demand_miss_rate::cpu3 0.875000 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.875000 # miss rate for demand accesses system.cpu3.l1c.overall_miss_rate::cpu3 0.875000 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.875000 # miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 35278.022452 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 35278.022452 # average ReadReq miss latency system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 42875.562470 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 42875.562470 # average WriteReq miss latency system.cpu3.l1c.demand_avg_miss_latency::cpu3 38198.189340 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 38198.189340 # average overall miss latency system.cpu3.l1c.overall_avg_miss_latency::cpu3 38198.189340 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 38198.189340 # average overall miss latency system.cpu3.l1c.blocked_cycles::no_mshrs 254462667 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.blocked::no_mshrs 68939 # number of cycles access was blocked @@ -961,16 +1101,27 @@ system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 569772276 system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1459204213 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1459204213 # number of overall MSHR uncacheable cycles system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.831214 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.831214 # mshr miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955632 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955632 # mshr miss rate for WriteReq accesses system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.875000 # mshr miss rate for demand accesses system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.875000 # mshr miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34274.209970 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34274.209970 # average ReadReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 41871.690641 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 41871.690641 # average WriteReq mshr miss latency system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu4.num_reads 99725 # number of read accesses completed system.cpu4.num_writes 53533 # number of write accesses completed @@ -1017,13 +1168,21 @@ system.cpu4.l1c.demand_accesses::total 68997 # nu system.cpu4.l1c.overall_accesses::cpu4 68997 # number of overall (read+write) accesses system.cpu4.l1c.overall_accesses::total 68997 # number of overall (read+write) accesses system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.828961 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.828961 # miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953325 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953325 # miss rate for WriteReq accesses system.cpu4.l1c.demand_miss_rate::cpu4 0.872328 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.872328 # miss rate for demand accesses system.cpu4.l1c.overall_miss_rate::cpu4 0.872328 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.872328 # miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 34981.938149 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 34981.938149 # average ReadReq miss latency system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 43355.729302 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 43355.729302 # average WriteReq miss latency system.cpu4.l1c.demand_avg_miss_latency::cpu4 38173.099970 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 38173.099970 # average overall miss latency system.cpu4.l1c.overall_avg_miss_latency::cpu4 38173.099970 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 38173.099970 # average overall miss latency system.cpu4.l1c.blocked_cycles::no_mshrs 254136532 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.blocked::no_mshrs 68868 # number of cycles access was blocked @@ -1057,16 +1216,27 @@ system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 576408625 system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1474870536 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1474870536 # number of overall MSHR uncacheable cycles system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.828961 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.828961 # mshr miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953325 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953325 # mshr miss rate for WriteReq accesses system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.872328 # mshr miss rate for demand accesses system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.872328 # mshr miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 33978.070817 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 33978.070817 # average ReadReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 42351.902864 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 42351.902864 # average WriteReq mshr miss latency system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu5.num_reads 100000 # number of read accesses completed system.cpu5.num_writes 53710 # number of write accesses completed @@ -1113,13 +1283,21 @@ system.cpu5.l1c.demand_accesses::total 69080 # nu system.cpu5.l1c.overall_accesses::cpu5 69080 # number of overall (read+write) accesses system.cpu5.l1c.overall_accesses::total 69080 # number of overall (read+write) accesses system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.831067 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.831067 # miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953353 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953353 # miss rate for WriteReq accesses system.cpu5.l1c.demand_miss_rate::cpu5 0.873798 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.873798 # miss rate for demand accesses system.cpu5.l1c.overall_miss_rate::cpu5 0.873798 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.873798 # miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 34590.842352 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 34590.842352 # average ReadReq miss latency system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 43380.004563 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 43380.004563 # average WriteReq miss latency system.cpu5.l1c.demand_avg_miss_latency::cpu5 37941.708625 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 37941.708625 # average overall miss latency system.cpu5.l1c.overall_avg_miss_latency::cpu5 37941.708625 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 37941.708625 # average overall miss latency system.cpu5.l1c.blocked_cycles::no_mshrs 253381114 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.blocked::no_mshrs 68969 # number of cycles access was blocked @@ -1153,16 +1331,27 @@ system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567587171 system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1470443205 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1470443205 # number of overall MSHR uncacheable cycles system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.831067 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.831067 # mshr miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953353 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953353 # mshr miss rate for WriteReq accesses system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.873798 # mshr miss rate for demand accesses system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.873798 # mshr miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 33586.894160 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 33586.894160 # average ReadReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 42376.221397 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 42376.221397 # average WriteReq mshr miss latency system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu6.num_reads 99389 # number of read accesses completed system.cpu6.num_writes 53686 # number of write accesses completed @@ -1209,13 +1398,21 @@ system.cpu6.l1c.demand_accesses::total 68913 # nu system.cpu6.l1c.overall_accesses::cpu6 68913 # number of overall (read+write) accesses system.cpu6.l1c.overall_accesses::total 68913 # number of overall (read+write) accesses system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.831071 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.831071 # miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953877 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953877 # miss rate for WriteReq accesses system.cpu6.l1c.demand_miss_rate::cpu6 0.874305 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.874305 # miss rate for demand accesses system.cpu6.l1c.overall_miss_rate::cpu6 0.874305 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.874305 # miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 35026.520844 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 35026.520844 # average ReadReq miss latency system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 43893.173019 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 43893.173019 # average WriteReq miss latency system.cpu6.l1c.demand_avg_miss_latency::cpu6 38432.141740 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 38432.141740 # average overall miss latency system.cpu6.l1c.overall_avg_miss_latency::cpu6 38432.141740 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 38432.141740 # average overall miss latency system.cpu6.l1c.blocked_cycles::no_mshrs 253794713 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.blocked::no_mshrs 68612 # number of cycles access was blocked @@ -1249,16 +1446,27 @@ system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 574689009 system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1452670464 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1452670464 # number of overall MSHR uncacheable cycles system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.831071 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.831071 # mshr miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953877 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953877 # mshr miss rate for WriteReq accesses system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.874305 # mshr miss rate for demand accesses system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.874305 # mshr miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 34022.708723 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 34022.708723 # average ReadReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 42889.171809 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 42889.171809 # average WriteReq mshr miss latency system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu7.num_reads 99694 # number of read accesses completed system.cpu7.num_writes 53501 # number of write accesses completed @@ -1305,13 +1513,21 @@ system.cpu7.l1c.demand_accesses::total 68980 # nu system.cpu7.l1c.overall_accesses::cpu7 68980 # number of overall (read+write) accesses system.cpu7.l1c.overall_accesses::total 68980 # number of overall (read+write) accesses system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.830316 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.830316 # miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954152 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954152 # miss rate for WriteReq accesses system.cpu7.l1c.demand_miss_rate::cpu7 0.873818 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.873818 # miss rate for demand accesses system.cpu7.l1c.overall_miss_rate::cpu7 0.873818 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.873818 # miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 34642.102409 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 34642.102409 # average ReadReq miss latency system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 43516.263916 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 43516.263916 # average WriteReq miss latency system.cpu7.l1c.demand_avg_miss_latency::cpu7 38046.102147 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 38046.102147 # average overall miss latency system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 38046.102147 # average overall miss latency system.cpu7.l1c.blocked_cycles::no_mshrs 254008986 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.blocked::no_mshrs 69036 # number of cycles access was blocked @@ -1345,16 +1561,27 @@ system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 558194703 system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1460156339 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1460156339 # number of overall MSHR uncacheable cycles system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.830316 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.830316 # mshr miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954152 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954152 # mshr miss rate for WriteReq accesses system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.873818 # mshr miss rate for demand accesses system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.873818 # mshr miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 33638.262764 # average ReadReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 42512.349466 # average WriteReq mshr miss latency system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats index f9dd021f3..7b092c66b 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:35 +Real time: Jun/04/2012 14:40:53 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.3 -Virtual_time_in_minutes: 0.005 -Virtual_time_in_hours: 8.33333e-05 -Virtual_time_in_days: 3.47222e-06 +Virtual_time_in_seconds: 0.36 +Virtual_time_in_minutes: 0.006 +Virtual_time_in_hours: 0.0001 +Virtual_time_in_days: 4.16667e-06 Ruby_current_time: 349711 Ruby_start_time: 0 Ruby_cycles: 349711 -mbytes_resident: 42.2773 -mbytes_total: 215.703 -resident_ratio: 0.195998 +mbytes_resident: 43.2695 +mbytes_total: 216.074 +resident_ratio: 0.200253 ruby_cycles_executed: [ 349712 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11317 +page_reclaims: 11518 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 80 +block_outputs: 88 Network Stats ------------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout index 56e348b35..bfa4f7e73 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 14:40:53 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index 715dd6b55..f6f4e6847 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000350 # Nu sim_ticks 349711 # Number of ticks simulated final_tick 349711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2733901 # Simulator tick rate (ticks/s) -host_mem_usage 220884 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 2288501 # Simulator tick rate (ticks/s) +host_mem_usage 221264 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats index 706512ef6..ebeb573bc 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:38 +Real time: Jun/04/2012 14:42:01 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.56 -Virtual_time_in_minutes: 0.00933333 -Virtual_time_in_hours: 0.000155556 -Virtual_time_in_days: 6.48148e-06 +Virtual_time_in_seconds: 0.66 +Virtual_time_in_minutes: 0.011 +Virtual_time_in_hours: 0.000183333 +Virtual_time_in_days: 7.63889e-06 Ruby_current_time: 357561 Ruby_start_time: 0 Ruby_cycles: 357561 -mbytes_resident: 42.2305 -mbytes_total: 215.871 -resident_ratio: 0.195628 +mbytes_resident: 43.5312 +mbytes_total: 216.246 +resident_ratio: 0.201304 ruby_cycles_executed: [ 357562 ] @@ -119,11 +119,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11327 +page_reclaims: 11528 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 72 +block_outputs: 80 Network Stats ------------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout index 45991493b..473ebc3b9 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:42:00 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index a0c426ba8..22e36183d 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000358 # Nu sim_ticks 357561 # Number of ticks simulated final_tick 357561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 908445 # Simulator tick rate (ticks/s) -host_mem_usage 221056 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 776030 # Simulator tick rate (ticks/s) +host_mem_usage 221440 # Number of bytes of host memory used +host_seconds 0.46 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats index 3806bbb4c..c55e7feb6 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:42 +Real time: Jun/04/2012 14:43:05 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.28 -Virtual_time_in_minutes: 0.00466667 -Virtual_time_in_hours: 7.77778e-05 -Virtual_time_in_days: 3.24074e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 Ruby_current_time: 259241 Ruby_start_time: 0 Ruby_cycles: 259241 -mbytes_resident: 42.25 -mbytes_total: 215.77 -resident_ratio: 0.195811 +mbytes_resident: 43.2578 +mbytes_total: 216.168 +resident_ratio: 0.200112 ruby_cycles_executed: [ 259242 ] @@ -126,11 +126,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11326 +page_reclaims: 11509 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 80 +block_outputs: 88 Network Stats ------------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout index 2d7dcae80..a79f03bf6 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:42 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:43:05 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 29c84ee49..b667f4459 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000259 # Nu sim_ticks 259241 # Number of ticks simulated final_tick 259241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2436767 # Simulator tick rate (ticks/s) -host_mem_usage 220952 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 2053459 # Simulator tick rate (ticks/s) +host_mem_usage 221360 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats index 5a24f618a..8e58b5f4d 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:31 +Real time: Jun/04/2012 13:42:34 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 +Virtual_time_in_seconds: 0.32 +Virtual_time_in_minutes: 0.00533333 +Virtual_time_in_hours: 8.88889e-05 +Virtual_time_in_days: 3.7037e-06 Ruby_current_time: 205611 Ruby_start_time: 0 Ruby_cycles: 205611 -mbytes_resident: 42.1211 -mbytes_total: 215.602 -resident_ratio: 0.195365 +mbytes_resident: 43.1602 +mbytes_total: 215.941 +resident_ratio: 0.19987 ruby_cycles_executed: [ 205612 ] @@ -127,10 +127,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11276 +page_reclaims: 11479 page_faults: 0 swaps: 0 -block_inputs: 16 +block_inputs: 0 block_outputs: 80 Network Stats diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index 1f028aa91..4f76e711e 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 35d1a046f..863fa07d3 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000206 # Nu sim_ticks 205611 # Number of ticks simulated final_tick 205611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2474305 # Simulator tick rate (ticks/s) -host_mem_usage 220780 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 2093129 # Simulator tick rate (ticks/s) +host_mem_usage 221128 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats index 3b6b0e305..1f17ccfc3 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:36:56 +Real time: Jun/04/2012 13:52:42 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.29 -Virtual_time_in_minutes: 0.00483333 -Virtual_time_in_hours: 8.05556e-05 -Virtual_time_in_days: 3.35648e-06 +Virtual_time_in_seconds: 0.28 +Virtual_time_in_minutes: 0.00466667 +Virtual_time_in_hours: 7.77778e-05 +Virtual_time_in_days: 3.24074e-06 Ruby_current_time: 280571 Ruby_start_time: 0 Ruby_cycles: 280571 -mbytes_resident: 41.6914 -mbytes_total: 214.977 -resident_ratio: 0.193935 +mbytes_resident: 43.0117 +mbytes_total: 215.34 +resident_ratio: 0.199739 ruby_cycles_executed: [ 280572 ] @@ -121,11 +121,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11172 -page_faults: 0 +page_reclaims: 11376 +page_faults: 5 swaps: 0 -block_inputs: 0 -block_outputs: 72 +block_inputs: 432 +block_outputs: 80 Network Stats ------------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout index 4e724cd5b..d291e3597 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:36:56 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 13:52:42 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index c5e74a2ba..b210abac4 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,14 +4,8 @@ sim_seconds 0.000281 # Nu sim_ticks 280571 # Number of ticks simulated final_tick 280571 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2565590 # Simulator tick rate (ticks/s) -host_mem_usage 220140 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 3251259 # Simulator tick rate (ticks/s) +host_mem_usage 220512 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host ---------- End Simulation Statistics ---------- |