diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/quick | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/quick')
27 files changed, 11124 insertions, 11024 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 6b719babe..a5d2b415b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -197,7 +197,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -440,8 +440,8 @@ system.cpu0.num_fp_register_writes 150767 # nu system.cpu0.num_mem_refs 15124548 # number of memory refs system.cpu0.num_load_insts 9178366 # Number of load instructions system.cpu0.num_store_insts 5946182 # Number of store instructions -system.cpu0.num_idle_cycles 3683454681.836560 # Number of idle cycles -system.cpu0.num_busy_cycles 57196201.163440 # Number of busy cycles +system.cpu0.num_idle_cycles 3683454681.064560 # Number of idle cycles +system.cpu0.num_busy_cycles 57196201.935440 # Number of busy cycles system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 2435d9264..178493c15 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -187,7 +187,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -302,8 +302,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115688 # number of memory refs system.cpu.num_load_insts 9747503 # Number of load instructions system.cpu.num_store_insts 6368185 # Number of store instructions -system.cpu.num_idle_cycles 3598606250.520791 # Number of idle cycles -system.cpu.num_busy_cycles 60054827.479209 # Number of busy cycles +system.cpu.num_idle_cycles 3598606249.772791 # Number of idle cycles +system.cpu.num_busy_cycles 60054828.227209 # Number of busy cycles system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983586 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -608,5 +608,69 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2042707 # number of replacements +system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits +system.cpu.dcache.overall_hits::total 13655968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks +system.cpu.dcache.writebacks::total 833491 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 0e2cc710f..e93e66fed 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.950814 # Number of seconds simulated -sim_ticks 1950813955500 # Number of ticks simulated -final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.952724 # Number of seconds simulated +sim_ticks 1952724269500 # Number of ticks simulated +final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 720692 # Simulator instruction rate (inst/s) -host_op_rate 720692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23054537293 # Simulator tick rate (ticks/s) -host_mem_usage 378432 # Number of bytes of host memory used -host_seconds 84.62 # Real time elapsed on the host -sim_insts 60983017 # Number of instructions simulated -sim_ops 60983017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory +host_inst_rate 1678586 # Simulator instruction rate (inst/s) +host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53851852439 # Simulator tick rate (ticks/s) +host_mem_usage 333452 # Number of bytes of host memory used +host_seconds 36.26 # Real time elapsed on the host +sim_insts 60867235 # Number of instructions simulated +sim_ops 60867235 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory -system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory -system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory +system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory +system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448191 # Total number of read requests seen -system.physmem.writeReqs 120414 # Total number of write requests seen -system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28684224 # Total number of bytes read from memory -system.physmem.bytesWritten 7706496 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis +system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448125 # Total number of read requests seen +system.physmem.writeReqs 120294 # Total number of write requests seen +system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28680000 # Total number of bytes read from memory +system.physmem.bytesWritten 7698816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry -system.physmem.totGap 1950760240000 # Total gap between requests +system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry +system.physmem.totGap 1952670553500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448191 # Categorize read packet sizes +system.physmem.readPktSize::6 448125 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 120944 # categorize write packet sizes +system.physmem.writePktSize::6 121700 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,30 +116,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes +system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 409750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests -system.physmem.totBusLat 1792536000 # Total cycles spent in databus access -system.physmem.totBankLat 6288996000 # Total cycles spent in bank access -system.physmem.avgQLat 6509.40 # Average queueing delay per request -system.physmem.avgBankLat 14033.74 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24543.14 # Average memory access latency -system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.totQLat 4798545467 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13448530467 # Sum of mem lat for all requests +system.physmem.totBusLat 2240285000 # Total cycles spent in databus access +system.physmem.totBankLat 6409700000 # Total cycles spent in bank access +system.physmem.avgQLat 10709.68 # Average queueing delay per request +system.physmem.avgBankLat 14305.55 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30015.22 # Average memory access latency +system.physmem.avgRdBW 14.69 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.94 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.51 # Average write queue length over time -system.physmem.readRowHits 428061 # Number of row buffer hits during reads -system.physmem.writeRowHits 76773 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes -system.physmem.avgGap 3430782.78 # Average gap between requests -system.l2c.replacements 341335 # number of replacements -system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use -system.l2c.total_refs 2438054 # Total number of references to valid blocks. -system.l2c.sampled_refs 406311 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.000463 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55545.332470 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4807.217204 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4686.652945 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 164.376424 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 43.456861 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.847555 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 674205 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 658217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 328581 # 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number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 706675500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 17206531500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 33342000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 443248500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 18389797500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 687131 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 929848 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 329193 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 113782 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2059954 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 791470 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 791470 # 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average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -503,14 +503,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.562950 # Cycle average of tags in use +system.iocache.tagsinuse 0.569993 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.562950 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1746698431000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.569993 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035625 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035625 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -521,12 +521,12 @@ system.iocache.overall_misses::tsunami.ide 41728 # system.iocache.overall_misses::total 41728 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10634917806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10634917806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10656186804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10656186804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10656186804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10656186804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -545,17 +545,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255942.380776 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 255942.380776 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255372.574866 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255372.574866 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 284837 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -569,14 +569,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41728 system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -585,14 +585,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -610,22 +610,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7424685 # DTB read hits +system.cpu0.dtb.read_hits 7490982 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5011105 # DTB write hits +system.cpu0.dtb.write_hits 5068153 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12435790 # DTB hits +system.cpu0.dtb.data_hits 12559135 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3481701 # ITB hits +system.cpu0.itb.fetch_hits 3503456 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3485572 # ITB accesses +system.cpu0.itb.fetch_accesses 3507327 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,55 +638,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3900399041 # number of cpu cycles simulated +system.cpu0.numCycles 3904305293 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47350784 # Number of instructions committed -system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses -system.cpu0.num_func_calls 1188579 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43919786 # number of integer instructions -system.cpu0.num_fp_insts 206365 # number of float instructions -system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written -system.cpu0.num_mem_refs 12475691 # number of memory refs -system.cpu0.num_load_insts 7451626 # Number of load instructions -system.cpu0.num_store_insts 5024065 # Number of store instructions -system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles -system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles +system.cpu0.committedInsts 47706703 # Number of instructions committed +system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses +system.cpu0.num_func_calls 1201591 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44241786 # number of integer instructions +system.cpu0.num_fp_insts 211423 # number of float instructions +system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599388 # number of memory refs +system.cpu0.num_load_insts 7518173 # Number of load instructions +system.cpu0.num_store_insts 5081215 # Number of store instructions +system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles +system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles +system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -718,37 +718,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed -system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed +system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147588 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches +system.cpu0.kern.callpal::total 149953 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3025 # number of times the context was actually changed +system.cpu0.kern.swap_context 3075 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -780,51 +780,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 686544 # number of replacements -system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use -system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 46672235 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46672235 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46672235 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46672235 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46672235 # number of overall hits -system.cpu0.icache.overall_hits::total 46672235 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687149 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687149 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687149 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687149 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687149 # number of overall misses -system.cpu0.icache.overall_misses::total 687149 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9571696500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9571696500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9571696500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9571696500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9571696500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9571696500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359384 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47359384 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47359384 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47359384 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47359384 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47359384 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014509 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014509 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014509 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014509 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014509 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014509 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13929.579320 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13929.579320 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13929.579320 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13929.579320 # average overall miss latency +system.cpu0.icache.replacements 699703 # number of replacements +system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use +system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits +system.cpu0.icache.overall_hits::total 47014995 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses +system.cpu0.icache.overall_misses::total 700308 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9851397000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47715303 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,112 +833,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687149 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687149 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687149 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687149 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687149 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687149 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8197398500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8197398500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8197398500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8197398500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8197398500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8197398500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014509 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014509 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014509 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11929.579320 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700308 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 700308 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 700308 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 700308 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 700308 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 700308 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8450781000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8450781000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8450781000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8450781000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8450781000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8450781000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014677 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014677 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014677 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.234702 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1171731 # number of replacements -system.cpu0.dcache.tagsinuse 505.264467 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11253773 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1172148 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.600983 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.264467 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6351999 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6351999 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4607371 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4607371 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138396 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138396 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10959370 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10959370 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10959370 # number of overall hits -system.cpu0.dcache.overall_hits::total 10959370 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 933038 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 933038 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249274 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249274 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13435 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13435 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1182312 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1182312 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1182312 # number of overall misses -system.cpu0.dcache.overall_misses::total 1182312 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20824713000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 20824713000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7766651000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7766651000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144248500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 144248500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43490500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 43490500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 28591364000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28591364000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 28591364000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28591364000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285037 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7285037 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4856645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151831 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151831 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12141682 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12141682 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12141682 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12141682 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051326 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051326 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088487 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088487 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097376 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097376 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097376 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097376 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22319.254950 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22319.254950 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31157.084172 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31157.084172 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10736.769632 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10736.769632 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7588.640726 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7588.640726 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24182.588014 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24182.588014 # average overall miss latency +system.cpu0.dcache.replacements 1182211 # number of replacements +system.cpu0.dcache.tagsinuse 505.184188 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11367781 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1182629 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.612297 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.184188 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.986688 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.986688 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6409561 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6409561 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4659572 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4659572 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140562 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140562 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148239 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148239 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11069133 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11069133 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11069133 # number of overall hits +system.cpu0.dcache.overall_hits::total 11069133 # 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miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097183 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097183 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097183 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22477.794758 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22477.794758 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30341.805420 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30341.805420 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10928.895890 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10928.895890 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7610.926541 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7610.926541 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24140.225290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24140.225290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,62 +947,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672345 # number of writebacks -system.cpu0.dcache.writebacks::total 672345 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933038 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 933038 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249274 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249274 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182312 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1182312 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182312 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks +system.cpu0.dcache.writebacks::total 680601 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1014,22 +1014,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2500361 # DTB read hits +system.cpu1.dtb.read_hits 2417694 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1820984 # DTB write hits +system.cpu1.dtb.write_hits 1754404 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4321345 # DTB hits +system.cpu1.dtb.data_hits 4172098 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1990033 # ITB hits +system.cpu1.itb.fetch_hits 1961503 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991249 # ITB accesses +system.cpu1.itb.fetch_accesses 1962719 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1042,51 +1042,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3901627911 # number of cpu cycles simulated +system.cpu1.numCycles 3905448539 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13632233 # Number of instructions committed -system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses -system.cpu1.num_func_calls 426713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12571690 # number of integer instructions -system.cpu1.num_fp_insts 180459 # number of float instructions -system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written -system.cpu1.num_mem_refs 4345653 # number of memory refs -system.cpu1.num_load_insts 2515108 # Number of load instructions -system.cpu1.num_store_insts 1830545 # Number of store instructions -system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles +system.cpu1.committedInsts 13160532 # Number of instructions committed +system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses +system.cpu1.num_func_calls 411397 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12141335 # number of integer instructions +system.cpu1.num_fp_insts 171917 # number of float instructions +system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written +system.cpu1.num_mem_refs 4195541 # number of memory refs +system.cpu1.num_load_insts 2431931 # Number of load instructions +system.cpu1.num_store_insts 1763610 # Number of store instructions +system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -1102,81 +1102,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed -system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed -system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed +system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed +system.cpu1.kern.callpal::rdps 2168 3.04% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3763 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73828 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches +system.cpu1.kern.callpal::total 71284 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2048 # number of protection mode switches system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 915 +system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 889 system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 450 -system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 424 +system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2086 # number of times the context was actually changed -system.cpu1.icache.replacements 328646 # number of replacements -system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use -system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 13306402 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13306402 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13306402 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13306402 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13306402 # number of overall hits -system.cpu1.icache.overall_hits::total 13306402 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 329194 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 329194 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 329194 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 329194 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 329194 # number of overall misses -system.cpu1.icache.overall_misses::total 329194 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4346536000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4346536000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4346536000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4346536000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4346536000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4346536000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635596 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13635596 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13635596 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13635596 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13635596 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13635596 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024142 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024142 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024142 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024142 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024142 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024142 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13203.569931 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13203.569931 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13203.569931 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.147427 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329931 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17784732000 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1713538500 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1933225237500 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1984 # number of times the context was actually changed +system.cpu1.icache.replacements 314891 # number of replacements +system.cpu1.icache.tagsinuse 448.025093 # Cycle average of tags in use +system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 448.025093 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.875049 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12848456 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12848456 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12848456 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12848456 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12848456 # number of overall hits +system.cpu1.icache.overall_hits::total 12848456 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 315439 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 315439 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 315439 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 315439 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 315439 # number of overall misses +system.cpu1.icache.overall_misses::total 315439 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4168917000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4168917000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13163895 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13163895 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13163895 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13163895 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13163895 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13163895 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023962 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023962 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,112 +1185,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023962 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023962 # 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Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 165927 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.133384 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 486.567196 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.950327 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.950327 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2254351 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2254351 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1637565 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1637565 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47962 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47962 # 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miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155940 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044207 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044207 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044207 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044207 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12134.632708 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12134.632708 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17403.375365 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17403.375365 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.644961 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.644961 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7253.223311 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7253.223311 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13959.137473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13959.137473 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1299,62 +1299,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119125 # number of writebacks -system.cpu1.dcache.writebacks::total 119125 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123241 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123241 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64769 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 64769 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9346 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9346 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6142 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6142 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 188010 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 188010 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 188010 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 188010 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks +system.cpu1.dcache.writebacks::total 113605 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 117672 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62334 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5817 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5817 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 180006 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 180006 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 180006 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 180006 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1192562500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1192562500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 960154000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 960154000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63672000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63672000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30558000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30558000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2152716500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2152716500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2152716500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2152716500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 712390500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index e3ca77030..37fa2c1e1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.910582 # Number of seconds simulated -sim_ticks 1910582068000 # Number of ticks simulated -final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.910548 # Number of seconds simulated +sim_ticks 1910547559000 # Number of ticks simulated +final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 951839 # Simulator instruction rate (inst/s) -host_op_rate 951839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32401800424 # Simulator tick rate (ticks/s) -host_mem_usage 374212 # Number of bytes of host memory used -host_seconds 58.97 # Real time elapsed on the host -sim_insts 56125446 # Number of instructions simulated -sim_ops 56125446 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +host_inst_rate 1284259 # Simulator instruction rate (inst/s) +host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43720523895 # Simulator tick rate (ticks/s) +host_mem_usage 330356 # Number of bytes of host memory used +host_seconds 43.70 # Real time elapsed on the host +sim_insts 56120911 # Number of instructions simulated +sim_ops 56120911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory -system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442975 # Total number of read requests seen -system.physmem.writeReqs 115503 # Total number of write requests seen -system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28350400 # Total number of bytes read from memory -system.physmem.bytesWritten 7392192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q +system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443146 # Total number of read requests seen +system.physmem.writeReqs 115693 # Total number of write requests seen +system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28361344 # Total number of bytes read from memory +system.physmem.bytesWritten 7404352 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27656 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7244 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7584 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7257 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7126 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7126 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27733 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27564 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7067 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7113 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 404 # Number of times wr buffer was full causing retry -system.physmem.totGap 1910570168000 # Total gap between requests +system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry +system.physmem.totGap 1910535659000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 442975 # Categorize read packet sizes +system.physmem.readPktSize::6 443146 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 115907 # categorize write packet sizes +system.physmem.writePktSize::6 117758 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -109,27 +109,27 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 130 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 404639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 402456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -142,69 +142,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2804911869 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10779125869 # Sum of mem lat for all requests -system.physmem.totBusLat 1771696000 # Total cycles spent in databus access -system.physmem.totBankLat 6202518000 # Total cycles spent in bank access -system.physmem.avgQLat 6332.72 # Average queueing delay per request -system.physmem.avgBankLat 14003.57 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24336.29 # Average memory access latency +system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests +system.physmem.totBusLat 2215505000 # Total cycles spent in databus access +system.physmem.totBankLat 6296675000 # Total cycles spent in bank access +system.physmem.avgQLat 10647.84 # Average queueing delay per request +system.physmem.avgBankLat 14210.47 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29858.31 # Average memory access latency system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.48 # Average write queue length over time -system.physmem.readRowHits 423327 # Number of row buffer hits during reads -system.physmem.writeRowHits 74914 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.86 # Row buffer hit rate for writes -system.physmem.avgGap 3421030.31 # Average gap between requests +system.physmem.avgWrQLen 11.47 # Average write queue length over time +system.physmem.readRowHits 415807 # Number of row buffer hits during reads +system.physmem.writeRowHits 89941 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes +system.physmem.avgGap 3418758.64 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.342666 # Cycle average of tags in use +system.iocache.tagsinuse 1.342284 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745691885000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.342666 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083917 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083917 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083893 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083893 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9475235806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9475235806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9496163804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9496163804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9496163804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9496163804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10644331806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10644331806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10665259804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10665259804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10665259804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10665259804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228033.206729 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228033.206729 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 189601 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256168.940268 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23064 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27152 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.220647 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.497496 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7324399500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7324399500 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8494267359 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8494267359 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175983.550732 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 175983.550732 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9055970 # DTB read hits +system.cpu.dtb.read_hits 9055197 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6351685 # DTB write hits +system.cpu.dtb.write_hits 6350929 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15407655 # DTB hits +system.cpu.dtb.data_hits 15406126 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974178 # ITB hits +system.cpu.itb.fetch_hits 4974131 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979184 # ITB accesses +system.cpu.itb.fetch_accesses 4979137 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,51 +332,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3821164136 # number of cpu cycles simulated +system.cpu.numCycles 3821095118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56125446 # Number of instructions committed -system.cpu.committedOps 56125446 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51999916 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1482010 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6463546 # number of instructions that are conditional controls -system.cpu.num_int_insts 51999916 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read -system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15460271 # number of memory refs -system.cpu.num_load_insts 9092827 # Number of load instructions -system.cpu.num_store_insts 6367444 # Number of store instructions -system.cpu.num_idle_cycles 3587332264.998123 # Number of idle cycles -system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles -system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.938806 # Percentage of idle cycles +system.cpu.committedInsts 56120911 # Number of instructions committed +system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1481756 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls +system.cpu.num_int_insts 51995405 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read +system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15458726 # number of memory refs +system.cpu.num_load_insts 9092044 # Number of load instructions +system.cpu.num_store_insts 6366682 # Number of store instructions +system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles +system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles +system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.938773 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211969 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149111 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91164500 0.00% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736454000 0.04% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 53835630000 2.82% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1910581334000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -412,10 +412,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175936 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -424,21 +424,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192878 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323843 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192879 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches +system.cpu.kern.mode_switch::user 1744 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 +system.cpu.kern.mode_good::user 1744 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.324237 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392483 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45587423000 2.39% 2.39% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5075517000 0.27% 2.65% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392853 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45393996500 2.38% 2.38% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5132973000 0.27% 2.64% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1860019853500 97.36% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -470,51 +470,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927460 # number of replacements -system.cpu.icache.tagsinuse 509.121498 # Cycle average of tags in use -system.cpu.icache.total_refs 55209154 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 927971 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.494482 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 32120759000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.121498 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.994378 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.994378 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55209154 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55209154 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55209154 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55209154 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55209154 # number of overall hits -system.cpu.icache.overall_hits::total 55209154 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928131 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928131 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928131 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928131 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928131 # number of overall misses -system.cpu.icache.overall_misses::total 928131 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12666318500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12666318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12666318500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12666318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12666318500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12666318500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56137285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56137285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56137285 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56137285 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56137285 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56137285 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016533 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016533 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016533 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016533 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13647.123628 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13647.123628 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13647.123628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13647.123628 # average overall miss latency +system.cpu.icache.replacements 927816 # number of replacements +system.cpu.icache.tagsinuse 509.100001 # Cycle average of tags in use +system.cpu.icache.total_refs 55204264 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 928327 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.466399 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 32331359000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.100001 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.994336 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.994336 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55204264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55204264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55204264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55204264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55204264 # number of overall hits +system.cpu.icache.overall_hits::total 55204264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928486 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928486 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928486 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928486 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928486 # number of overall misses +system.cpu.icache.overall_misses::total 928486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12769098000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12769098000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12769098000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12769098000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12769098000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12769098000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56132750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56132750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56132750 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56132750 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56132750 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56132750 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016541 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016541 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016541 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016541 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016541 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016541 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13752.601547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13752.601547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13752.601547 # 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number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 73991 # number of writebacks -system.cpu.l2cache.writebacks::total 73991 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271922 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285212 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks +system.cpu.l2cache.writebacks::total 74181 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271961 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285252 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229367500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229367500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4162858124 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4162858124 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666952085 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12539726199 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13206678284 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666952085 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12539726199 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13206678284 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229366500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229366500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250431 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141604 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383643 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22802.025405 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 7805620 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7805620 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5846988 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5846988 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182985 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182985 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199218 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199218 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13652608 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13652608 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13652608 # number of overall hits +system.cpu.dcache.overall_hits::total 13652608 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1068716 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1068716 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304374 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304374 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17254 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17254 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373090 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373090 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373090 # number of overall misses +system.cpu.dcache.overall_misses::total 1373090 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22883646000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22883646000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8388017500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8388017500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229841000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229841000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31271663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31271663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31271663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31271663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8874336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8874336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15025698 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15025698 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15025698 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15025698 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120428 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120428 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049481 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049481 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21412.279782 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21412.279782 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27558.258918 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27558.258918 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13321.027008 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22774.664079 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,54 +799,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks -system.cpu.dcache.writebacks::total 834403 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373108 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373108 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20573355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20573355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7990072500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7990072500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193251000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193251000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28563427500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28563427500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks +system.cpu.dcache.writebacks::total 834499 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304374 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304374 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17254 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17254 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373090 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373090 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373090 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373090 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20746214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20746214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7779269500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7779269500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195333000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195333000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28525483500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28525483500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28525483500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28525483500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 5fe42fc21..839e0acab 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -215,7 +215,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index bc1e2b029..9811be55f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -198,7 +198,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index ebe1b98fa..13c85b6d1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.182882 # Number of seconds simulated -sim_ticks 1182882156500 # Number of ticks simulated -final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.183003 # Number of seconds simulated +sim_ticks 1183003114000 # Number of ticks simulated +final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 497131 # Simulator instruction rate (inst/s) -host_op_rate 633435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9569364300 # Simulator tick rate (ticks/s) -host_mem_usage 452888 # Number of bytes of host memory used -host_seconds 123.61 # Real time elapsed on the host -sim_insts 61450993 # Number of instructions simulated -sim_ops 78299715 # Number of ops (including micro ops) simulated +host_inst_rate 673901 # Simulator instruction rate (inst/s) +host_op_rate 858757 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12970235901 # Simulator tick rate (ticks/s) +host_mem_usage 408748 # Number of bytes of host memory used +host_seconds 91.21 # Real time elapsed on the host +sim_insts 61465824 # Number of instructions simulated +sim_ops 78326377 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory -system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory +system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory +system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654451 # Total number of read requests seen -system.physmem.writeReqs 821128 # Total number of write requests seen -system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425884864 # Total number of bytes read from memory -system.physmem.bytesWritten 52552192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654023 # Total number of read requests seen +system.physmem.writeReqs 820738 # Total number of write requests seen +system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425857472 # Total number of bytes read from memory +system.physmem.bytesWritten 52527232 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182877668000 # Total gap between requests +system.physmem.totGap 1182998675500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159562 # Categorize read packet sizes +system.physmem.readPktSize::6 159134 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,7 +125,7 @@ system.physmem.writePktSize::2 756836 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 64292 # categorize write packet sizes +system.physmem.writePktSize::6 63902 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,26 +134,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -170,60 +170,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 123719908904 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 159121708904 # Sum of mem lat for all requests -system.physmem.totBusLat 26617276000 # Total cycles spent in databus access -system.physmem.totBankLat 8784524000 # Total cycles spent in bank access -system.physmem.avgQLat 18592.42 # Average queueing delay per request -system.physmem.avgBankLat 1320.12 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23912.55 # Average memory access latency -system.physmem.avgRdBW 360.04 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.54 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.53 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 15.12 # Average write queue length over time -system.physmem.readRowHits 6628163 # Number of row buffer hits during reads -system.physmem.writeRowHits 789308 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.12 # Row buffer hit rate for writes -system.physmem.avgGap 158232.25 # Average gap between requests +system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests +system.physmem.totBusLat 33269555000 # Total cycles spent in databus access +system.physmem.totBankLat 9041986250 # Total cycles spent in bank access +system.physmem.avgQLat 22090.22 # Average queueing delay per request +system.physmem.avgBankLat 1358.90 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28449.12 # Average memory access latency +system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # 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mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770724 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573338 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.546627 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.558553 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106316 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106316 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40610.018244 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48571.194566 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42133.820428 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.341055 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.735761 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.114496 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.758319 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.444685 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.384690 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31951.092372 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34850.344312 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33521.565603 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -656,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070111 # DTB read hits -system.cpu0.dtb.read_misses 3764 # DTB read misses -system.cpu0.dtb.write_hits 5656042 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses +system.cpu0.dtb.read_hits 5883553 # DTB read hits +system.cpu0.dtb.read_misses 2148 # DTB read misses +system.cpu0.dtb.write_hits 4842455 # DTB write hits +system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073875 # DTB read accesses -system.cpu0.dtb.write_accesses 5656846 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 5885701 # DTB read accesses +system.cpu0.dtb.write_accesses 4842860 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12726153 # DTB hits -system.cpu0.dtb.misses 4568 # DTB misses -system.cpu0.dtb.accesses 12730721 # DTB accesses -system.cpu0.itb.inst_hits 29570310 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.dtb.hits 10726008 # DTB hits +system.cpu0.dtb.misses 2553 # DTB misses +system.cpu0.dtb.accesses 10728561 # DTB accesses +system.cpu0.itb.inst_hits 24779849 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -685,86 +685,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses -system.cpu0.itb.hits 29570310 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29572515 # DTB accesses -system.cpu0.numCycles 2365764313 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses +system.cpu0.itb.hits 24779849 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 24781199 # DTB accesses +system.cpu0.numCycles 2364565551 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28872367 # Number of instructions committed -system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33098187 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241715 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373222 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33098187 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13394441 # number of memory refs -system.cpu0.num_load_insts 7407672 # Number of load instructions -system.cpu0.num_store_insts 5986769 # Number of store instructions -system.cpu0.num_idle_cycles 2224997657.358119 # Number of idle cycles -system.cpu0.num_busy_cycles 140766655.641881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059502 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940498 # Percentage of idle cycles +system.cpu0.committedInsts 24381823 # Number of instructions committed +system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses +system.cpu0.num_func_calls 1070639 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28075203 # number of integer instructions +system.cpu0.num_fp_insts 4364 # number of float instructions +system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read +system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written +system.cpu0.num_mem_refs 11318426 # number of memory refs +system.cpu0.num_load_insts 6163151 # Number of load instructions +system.cpu0.num_store_insts 5155275 # Number of store instructions +system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles +system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed -system.cpu0.icache.replacements 425445 # number of replacements -system.cpu0.icache.tagsinuse 509.616014 # Cycle average of tags in use -system.cpu0.icache.total_refs 29144335 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 425957 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.420838 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995344 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29144335 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29144335 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29144335 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29144335 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29144335 # number of overall hits -system.cpu0.icache.overall_hits::total 29144335 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses -system.cpu0.icache.overall_misses::total 425958 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5792188000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5792188000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5792188000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5792188000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5792188000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5792188000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570293 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29570293 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29570293 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29570293 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29570293 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29570293 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.026096 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13598.026096 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13598.026096 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13598.026096 # average overall miss latency +system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed +system.cpu0.icache.replacements 354669 # number of replacements +system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use +system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits +system.cpu0.icache.overall_hits::total 24424650 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses +system.cpu0.icache.overall_misses::total 355182 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,120 +773,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425958 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425958 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425958 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425958 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330355 # number of replacements -system.cpu0.dcache.tagsinuse 453.331528 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12270860 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 330867 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.086987 # 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average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306206 # number of writebacks -system.cpu0.dcache.writebacks::total 306206 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227863 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227863 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141515 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141515 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9301 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9301 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369378 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369378 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369378 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369378 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2674386000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2674386000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3820765500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3820765500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69382000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69382000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29532500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks +system.cpu0.dcache.writebacks::total 257540 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6495151500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6495151500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6495151500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6495151500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,27 +964,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8310545 # DTB read hits -system.cpu1.dtb.read_misses 3643 # DTB read misses -system.cpu1.dtb.write_hits 5827351 # DTB write hits -system.cpu1.dtb.write_misses 1434 # DTB write misses +system.cpu1.dtb.read_hits 9504194 # DTB read hits +system.cpu1.dtb.read_misses 5263 # DTB read misses +system.cpu1.dtb.write_hits 6646220 # DTB write hits +system.cpu1.dtb.write_misses 1833 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8314188 # DTB read accesses -system.cpu1.dtb.write_accesses 5828785 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 9509457 # DTB read accesses +system.cpu1.dtb.write_accesses 6648053 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14137896 # DTB hits -system.cpu1.dtb.misses 5077 # DTB misses -system.cpu1.dtb.accesses 14142973 # DTB accesses -system.cpu1.itb.inst_hits 33189113 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.dtb.hits 16150414 # DTB hits +system.cpu1.dtb.misses 7096 # DTB misses +system.cpu1.dtb.accesses 16157510 # DTB accesses +system.cpu1.itb.inst_hits 37994467 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -993,86 +993,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses -system.cpu1.itb.hits 33189113 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33191284 # DTB accesses -system.cpu1.numCycles 2364318212 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses +system.cpu1.itb.hits 37994467 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 37997484 # DTB accesses +system.cpu1.numCycles 2366006228 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32578626 # Number of instructions committed -system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962009 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37313171 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14675641 # number of memory refs -system.cpu1.num_load_insts 8632449 # Number of load instructions -system.cpu1.num_store_insts 6043192 # Number of store instructions -system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles -system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles -system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles +system.cpu1.committedInsts 37084001 # Number of instructions committed +system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1133542 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls +system.cpu1.num_int_insts 42360540 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read +system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 16764021 # number of memory refs +system.cpu1.num_load_insts 9884261 # Number of load instructions +system.cpu1.num_store_insts 6879760 # Number of store instructions +system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles +system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles +system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed -system.cpu1.icache.replacements 469194 # number of replacements -system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use -system.cpu1.icache.total_refs 32719403 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.783096 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32719403 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32719403 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32719403 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32719403 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32719403 # number of overall hits -system.cpu1.icache.overall_hits::total 32719403 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469706 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469706 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469706 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469706 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469706 # number of overall misses -system.cpu1.icache.overall_misses::total 469706 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6343605000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6343605000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6343605000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6343605000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189109 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33189109 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33189109 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33189109 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33189109 # 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Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 83709904000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 473.088021 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.924000 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.924000 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8074934 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8074934 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5611325 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5611325 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100335 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 100335 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102214 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 102214 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 13686259 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 13686259 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 13686259 # number of overall hits +system.cpu1.dcache.overall_hits::total 13686259 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 207178 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 207178 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 165249 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 165249 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11790 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11790 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9834 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9834 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 372427 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 372427 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 372427 # number of overall misses +system.cpu1.dcache.overall_misses::total 372427 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2639135500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2639135500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4834942000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4834942000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 103120000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 103120000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50505000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50505000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7474077500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7474077500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7474077500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7474077500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8282112 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8282112 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5776574 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5776574 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112125 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 112125 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112048 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 112048 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14058686 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14058686 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14058686 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14058686 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.025015 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.025015 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.105151 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.105151 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087766 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087766 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026491 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026491 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026491 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026491 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12738.492987 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12738.492987 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29258.525014 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 29258.525014 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8746.395250 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8746.395250 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5135.753508 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5135.753508 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20068.570485 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20068.570485 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1203,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks -system.cpu1.dcache.writebacks::total 265102 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10026 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10026 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320439 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320439 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320439 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320439 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1808202000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1808202000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4227233500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4227233500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70109500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70109500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31633000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31633000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks +system.cpu1.dcache.writebacks::total 315665 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b72126c20..73585121b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603635 # Number of seconds simulated -sim_ticks 2603634694000 # Number of ticks simulated -final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603665 # Number of seconds simulated +sim_ticks 2603664815000 # Number of ticks simulated +final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 413538 # Simulator instruction rate (inst/s) -host_op_rate 526220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17886148072 # Simulator tick rate (ticks/s) -host_mem_usage 448796 # Number of bytes of host memory used -host_seconds 145.57 # Real time elapsed on the host -sim_insts 60197457 # Number of instructions simulated -sim_ops 76600355 # Number of ops (including micro ops) simulated +host_inst_rate 536000 # Simulator instruction rate (inst/s) +host_op_rate 682052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23183028791 # Simulator tick rate (ticks/s) +host_mem_usage 404656 # Number of bytes of host memory used +host_seconds 112.31 # Real time elapsed on the host +sim_insts 60197643 # Number of instructions simulated +sim_ops 76600583 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory -system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory +system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494095 # Total number of read requests seen -system.physmem.writeReqs 811481 # Total number of write requests seen -system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991622080 # Total number of bytes read from memory -system.physmem.bytesWritten 51934784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494089 # Total number of read requests seen +system.physmem.writeReqs 811479 # Total number of write requests seen +system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991621696 # Total number of bytes read from memory +system.physmem.bytesWritten 51934656 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603630334000 # Total gap between requests +system.physmem.totGap 2603660455000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.readPktSize::6 152013 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -108,7 +108,7 @@ system.physmem.writePktSize::2 754018 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57463 # categorize write packet sizes +system.physmem.writePktSize::6 57461 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -120,23 +120,23 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -153,14 +153,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see @@ -169,44 +169,44 @@ system.physmem.wrQLenPdf::12 35282 # Wh system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests -system.physmem.totBusLat 61975036000 # Total cycles spent in databus access -system.physmem.totBankLat 16863224000 # Total cycles spent in bank access -system.physmem.avgQLat 18619.82 # Average queueing delay per request -system.physmem.avgBankLat 1088.39 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23708.21 # Average memory access latency +system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests +system.physmem.totBusLat 77468765000 # Total cycles spent in databus access +system.physmem.totBankLat 17445216250 # Total cycles spent in bank access +system.physmem.avgQLat 22041.64 # Average queueing delay per request +system.physmem.avgBankLat 1125.95 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28167.59 # Average memory access latency system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.51 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 12.40 # Average write queue length over time -system.physmem.readRowHits 15451886 # Number of row buffer hits during reads -system.physmem.writeRowHits 785061 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes -system.physmem.avgGap 159677.30 # Average gap between requests +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 12.39 # Average write queue length over time +system.physmem.readRowHits 15418905 # Number of row buffer hits during reads +system.physmem.writeRowHits 794060 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes +system.physmem.avgGap 159679.22 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995645 # DTB read hits -system.cpu.dtb.read_misses 7331 # DTB read misses -system.cpu.dtb.write_hits 11230857 # DTB write hits +system.cpu.dtb.read_hits 14995667 # DTB read hits +system.cpu.dtb.read_misses 7332 # DTB read misses +system.cpu.dtb.write_hits 11230865 # DTB write hits system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002976 # DTB read accesses -system.cpu.dtb.write_accesses 11233060 # DTB write accesses +system.cpu.dtb.read_accesses 15002999 # DTB read accesses +system.cpu.dtb.write_accesses 11233068 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226502 # DTB hits -system.cpu.dtb.misses 9534 # DTB misses -system.cpu.dtb.accesses 26236036 # DTB accesses -system.cpu.itb.inst_hits 61491397 # ITB inst hits +system.cpu.dtb.hits 26226532 # DTB hits +system.cpu.dtb.misses 9535 # DTB misses +system.cpu.dtb.accesses 26236067 # DTB accesses +system.cpu.itb.inst_hits 61491584 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -263,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495868 # ITB inst accesses -system.cpu.itb.hits 61491397 # DTB hits +system.cpu.itb.inst_accesses 61496055 # ITB inst accesses +system.cpu.itb.hits 61491584 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495868 # DTB accesses -system.cpu.numCycles 5207269388 # number of cpu cycles simulated +system.cpu.itb.accesses 61496055 # DTB accesses +system.cpu.numCycles 5207329630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197457 # Number of instructions committed -system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses +system.cpu.committedInsts 60197643 # Number of instructions committed +system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139722 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868122 # number of integer instructions +system.cpu.num_func_calls 2139730 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls +system.cpu.num_int_insts 68868344 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written +system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read +system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393871 # number of memory refs -system.cpu.num_load_insts 15659652 # Number of load instructions -system.cpu.num_store_insts 11734219 # Number of store instructions -system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879373 # Percentage of idle cycles +system.cpu.num_mem_refs 27393912 # number of memory refs +system.cpu.num_load_insts 15659685 # Number of load instructions +system.cpu.num_store_insts 11734227 # Number of store instructions +system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879355 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855485 # number of replacements -system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use -system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635400 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635400 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635400 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635400 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635400 # number of overall hits -system.cpu.icache.overall_hits::total 60635400 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855997 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855997 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855997 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855997 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855997 # number of overall misses -system.cpu.icache.overall_misses::total 855997 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11539684000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11539684000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11539684000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses +system.cpu.icache.replacements 855486 # number of replacements +system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use +system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits +system.cpu.icache.overall_hits::total 60635586 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses +system.cpu.icache.overall_misses::total 855998 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491584 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491584 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13480.986499 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13480.986499 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13480.986499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13480.986499 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13515.573635 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13515.573635 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13515.573635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13515.573635 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,174 +344,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855997 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855997 # 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average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11515.573635 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11515.573635 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9173753597 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9173753597 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209122550 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175862199412 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176071321962 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -615,79 +615,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195134 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236278 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236278 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168170 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168170 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168170 # number of overall hits -system.cpu.dcache.overall_hits::total 23168170 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368781 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368781 # 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number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027188 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027188 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026034 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026034 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026034 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026034 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.130145 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.130145 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32117.582132 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,54 +696,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596029 # number of writebacks -system.cpu.dcache.writebacks::total 596029 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368781 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368781 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619291 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619291 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619291 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619291 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4464142000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4464142000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7544755500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7544755500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12008897500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12008897500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12008897500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12008897500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182078406500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182078406500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18714752000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18714752000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200793158500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200793158500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks +system.cpu.dcache.writebacks::total 596039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.130145 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.130145 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30117.582132 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30117.582132 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11575.425364 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11575.425364 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 21a80bd51..9d3d17a68 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -211,7 +211,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 175418c2b..4cde41f9a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.112041 # Nu sim_ticks 5112040970500 # Number of ticks simulated final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1071475 # Simulator instruction rate (inst/s) -host_op_rate 2193921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27413112180 # Simulator tick rate (ticks/s) -host_mem_usage 626876 # Number of bytes of host memory used -host_seconds 186.48 # Real time elapsed on the host +host_inst_rate 1816388 # Simulator instruction rate (inst/s) +host_op_rate 3719186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46471341970 # Simulator tick rate (ticks/s) +host_mem_usage 582576 # Number of bytes of host memory used +host_seconds 110.00 # Real time elapsed on the host sim_insts 199810242 # Number of instructions simulated -sim_ops 409125923 # Number of ops (including micro ops) simulated +sim_ops 409125913 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -195,7 +195,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -264,22 +264,22 @@ system.cpu.numCycles 10224081964 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 199810242 # Number of instructions committed -system.cpu.committedOps 409125923 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374289914 # Number of integer alu accesses +system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls -system.cpu.num_int_insts 374289914 # number of integer instructions +system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls +system.cpu.num_int_insts 374289904 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915450706 # number of times the integer registers were read -system.cpu.num_int_register_writes 480322745 # number of times the integer registers were written +system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read +system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 35624590 # number of memory refs system.cpu.num_load_insts 27216588 # Number of load instructions system.cpu.num_store_insts 8408002 # Number of store instructions -system.cpu.num_idle_cycles 9770609597.971960 # Number of idle cycles -system.cpu.num_busy_cycles 453472366.028039 # Number of busy cycles +system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles +system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -331,7 +331,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cy system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102019610500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy @@ -379,7 +379,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cy system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101206386000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy @@ -471,7 +471,7 @@ system.cpu.dcache.writebacks::writebacks 1534848 # nu system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 106558 # number of replacements -system.cpu.l2cache.tagsinuse 64822.149219 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. @@ -479,8 +479,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.994082 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.564951 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 5387a3a4f..da7af1088 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,98 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.191113 # Number of seconds simulated -sim_ticks 5191112864000 # Number of ticks simulated -final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.195162 # Number of seconds simulated +sim_ticks 5195162021000 # Number of ticks simulated +final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 663100 # Simulator instruction rate (inst/s) -host_op_rate 1278245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26841102406 # Simulator tick rate (ticks/s) -host_mem_usage 658020 # Number of bytes of host memory used -host_seconds 193.40 # Real time elapsed on the host -sim_insts 128244620 # Number of instructions simulated -sim_ops 247214608 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory +host_inst_rate 973985 # Simulator instruction rate (inst/s) +host_op_rate 1877578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39447094407 # Simulator tick rate (ticks/s) +host_mem_usage 612564 # Number of bytes of host memory used +host_seconds 131.70 # Real time elapsed on the host +sim_insts 128273348 # Number of instructions simulated +sim_ops 247275973 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9026368 # Number of bytes read from this memory -system.physmem.bytes_read::total 12705024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8129280 # Number of bytes written to this memory -system.physmem.bytes_written::total 8129280 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44568 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9012160 # Number of bytes read from this memory +system.physmem.bytes_read::total 12697600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8123136 # Number of bytes written to this memory +system.physmem.bytes_written::total 8123136 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44708 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141037 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 127020 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127020 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 549468 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140815 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198400 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126924 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126924 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 550765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1738812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2447457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1565999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1565999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1565999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 549468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1734722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2444120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1563596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1563596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1563596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 550765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1738812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4013456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198516 # Total number of read requests seen -system.physmem.writeReqs 127020 # Total number of write requests seen -system.physmem.cpureqs 331314 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 12705024 # Total number of bytes read from memory -system.physmem.bytesWritten 8129280 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12705024 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8129280 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1599 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12411 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 11776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12503 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12788 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 12663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12141 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12474 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12788 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7431 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7966 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7373 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 8083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7719 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 8332 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7712 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7893 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7991 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8281 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 158560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1734722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198400 # Total number of read requests seen +system.physmem.writeReqs 126924 # Total number of write requests seen +system.physmem.cpureqs 331611 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12697600 # Total number of bytes read from memory +system.physmem.bytesWritten 8123136 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 12479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12349 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12500 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12050 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12574 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8012 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 8089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7865 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8084 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 8243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8069 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7980 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 5191112800500 # Total gap between requests +system.physmem.numWrRetry 633 # Number of times wr buffer was full causing retry +system.physmem.totGap 5195161957500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198516 # Categorize read packet sizes +system.physmem.readPktSize::6 198400 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -101,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 127020 # categorize write packet sizes +system.physmem.writePktSize::6 127557 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -110,30 +114,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1599 # categorize neither packet sizes +system.physmem.neitherpktsize::6 1624 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 158090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 155111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -146,93 +150,93 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2876225269 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6438451269 # Sum of mem lat for all requests -system.physmem.totBusLat 793712000 # Total cycles spent in databus access -system.physmem.totBankLat 2768514000 # Total cycles spent in bank access -system.physmem.avgQLat 14495.06 # Average queueing delay per request -system.physmem.avgBankLat 13952.23 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32447.29 # Average memory access latency -system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.totQLat 4076582985 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7872522985 # Sum of mem lat for all requests +system.physmem.totBusLat 991710000 # Total cycles spent in databus access +system.physmem.totBankLat 2804230000 # Total cycles spent in bank access +system.physmem.avgQLat 20553.30 # Average queueing delay per request +system.physmem.avgBankLat 14138.36 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 39691.66 # Average memory access latency +system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.06 # Average write queue length over time -system.physmem.readRowHits 179831 # Number of row buffer hits during reads -system.physmem.writeRowHits 78085 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.47 # Row buffer hit rate for writes -system.physmem.avgGap 15946355.55 # Average gap between requests -system.iocache.replacements 47506 # number of replacements -system.iocache.tagsinuse 0.117830 # Cycle average of tags in use +system.physmem.avgWrQLen 12.66 # Average write queue length over time +system.physmem.readRowHits 175587 # Number of row buffer hits during reads +system.physmem.writeRowHits 94819 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes +system.physmem.avgGap 15969193.66 # Average gap between requests +system.iocache.replacements 47509 # number of replacements +system.iocache.tagsinuse 0.124742 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47522 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47525 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5044498925000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.117830 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007364 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007364 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 841 # number of ReadReq misses -system.iocache.ReadReq_misses::total 841 # number of ReadReq misses +system.iocache.warmup_cycle 5044527520000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.124742 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007796 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007796 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses +system.iocache.ReadReq_misses::total 844 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47561 # number of demand (read+write) misses -system.iocache.demand_misses::total 47561 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47561 # number of overall misses -system.iocache.overall_misses::total 47561 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 133668932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 133668932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9598301160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9598301160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9731970092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9731970092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9731970092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9731970092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 841 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 841 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses +system.iocache.demand_misses::total 47564 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses +system.iocache.overall_misses::total 47564 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10701739160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10701739160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10841219092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10841219092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10841219092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10841219092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47561 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47561 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47561 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47561 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -241,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158940.466112 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158940.466112 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 205443.089897 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 205443.089897 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 204620.804693 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 204620.804693 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 78425 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229061.197774 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229061.197774 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227929.086957 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227929.086957 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 173428 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10368 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16211 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.564140 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.698168 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 841 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 841 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47561 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47561 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47561 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47561 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89906992 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 89906992 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7166703132 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7166703132 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7256610124 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7256610124 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570991 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 95570991 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8270938224 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8270938224 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8366509215 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8366509215 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -283,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106904.865636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106904.865636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 153396.899229 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 153396.899229 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.771327 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.771327 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177032.068151 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177032.068151 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -304,75 +308,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10382225728 # number of cpu cycles simulated +system.cpu.numCycles 10390324042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128244620 # Number of instructions committed -system.cpu.committedOps 247214608 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231949869 # Number of integer alu accesses +system.cpu.committedInsts 128273348 # Number of instructions committed +system.cpu.committedOps 247275973 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232011682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls -system.cpu.num_int_insts 231949869 # number of integer instructions +system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls +system.cpu.num_int_insts 232011682 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566905534 # number of times the integer registers were read -system.cpu.num_int_register_writes 293156476 # number of times the integer registers were written +system.cpu.num_int_register_reads 567056120 # number of times the integer registers were read +system.cpu.num_int_register_writes 293242224 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22227095 # number of memory refs -system.cpu.num_load_insts 13866667 # Number of load instructions -system.cpu.num_store_insts 8360428 # Number of store instructions -system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942147 # Percentage of idle cycles +system.cpu.num_mem_refs 22232138 # number of memory refs +system.cpu.num_load_insts 13871783 # Number of load instructions +system.cpu.num_store_insts 8360355 # Number of store instructions +system.cpu.num_idle_cycles 9789668776.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600655265.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942191 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790930 # number of replacements -system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use -system.cpu.icache.total_refs 144455345 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.521707 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor +system.cpu.icache.replacements 791521 # number of replacements +system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use +system.cpu.icache.total_refs 144497694 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 792033 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.438982 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144455345 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144455345 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144455345 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144455345 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144455345 # number of overall hits -system.cpu.icache.overall_hits::total 144455345 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses -system.cpu.icache.overall_misses::total 791449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871281000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10871281000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10871281000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145246794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145246794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145246794 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145246794 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145246794 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145246794 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.921076 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13735.921076 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13735.921076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13735.921076 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 144497694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144497694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144497694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144497694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144497694 # number of overall hits +system.cpu.icache.overall_hits::total 144497694 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792040 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792040 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792040 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792040 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792040 # number of overall misses +system.cpu.icache.overall_misses::total 792040 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10957638500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10957638500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10957638500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10957638500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10957638500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10957638500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145289734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145289734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145289734 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145289734 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145289734 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145289734 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.703424 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13834.703424 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13834.703424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13834.703424 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,80 +385,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9288383000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9288383000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.921076 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.921076 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9373558500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9373558500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9373558500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9373558500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9373558500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # 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Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3675 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.094150 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5164936292000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.069768 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191861 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191861 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7696 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7696 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3425 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.077882 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5164118674000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077882 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192368 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.192368 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8004 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 8004 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7698 # 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number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 46136000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 46136000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 46136000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 46136000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8006 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 8006 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8006 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 8006 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4287 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4287 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4287 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4287 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4287 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4287 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42274000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42274000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42274000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 42274000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42274000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 42274000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12291 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12291 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.370419 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.370419 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.370358 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.370358 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10189.045936 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10189.045936 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10189.045936 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10189.045936 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12293 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12293 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12293 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12293 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.348792 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.348792 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.348735 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.348735 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.348735 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.348735 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9860.975041 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9860.975041 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9860.975041 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -463,78 +467,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 884 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 884 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4528 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4528 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4528 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4528 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4528 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4528 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37080000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37080000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37080000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37080000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37080000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37080000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.370419 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.370419 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8189.045936 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 641 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 641 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4287 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4287 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4287 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4287 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4287 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4287 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33700000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33700000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33700000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33700000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33700000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33700000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.348792 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.348792 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.348735 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.348735 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7860.975041 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 8012 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.053256 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13052 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 8025 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.626417 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5162707625000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053256 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315829 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315829 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13068 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13068 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13068 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13068 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13068 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13068 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9194 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9194 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9194 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9194 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9194 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9194 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 98984000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 98984000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 98984000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 98984000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 98984000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 98984000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22262 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22262 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22262 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22262 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22262 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22262 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.412991 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.412991 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.412991 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.412991 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.412991 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.412991 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10766.151838 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10766.151838 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10766.151838 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10766.151838 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7538 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.062515 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13179 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7552 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.745101 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062515 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13181 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13181 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13181 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13181 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13181 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13181 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8725 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8725 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8725 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8725 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8725 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8725 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92081500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92081500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92081500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 92081500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92081500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 92081500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398293 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398293 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398293 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398293 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398293 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398293 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.753582 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.753582 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.753582 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,90 +547,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3347 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3347 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9194 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9194 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9194 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9194 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9194 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9194 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 80596000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 80596000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 80596000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 80596000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 80596000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 80596000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.412991 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.412991 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.412991 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8766.151838 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2712 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2712 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8725 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8725 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8725 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8725 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8725 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8725 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74631500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74631500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74631500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74631500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398293 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398293 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398293 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.753582 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1620901 # number of replacements -system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use -system.cpu.dcache.total_refs 20018690 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621413 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.346447 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1618787 # number of replacements +system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use +system.cpu.dcache.total_refs 20025899 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1619299 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.367017 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8034928 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8034928 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20016508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20016508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20016508 # number of overall hits -system.cpu.dcache.overall_hits::total 20016508 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308145 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308145 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315486 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623631 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623631 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623631 # number of overall misses -system.cpu.dcache.overall_misses::total 1623631 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313636000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18313636000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702717500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8702717500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27016353500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27016353500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27016353500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27016353500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21640139 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21640139 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21640139 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21640139 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098433 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037781 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037781 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075029 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # 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number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035473 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20023737 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20023737 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20023737 # number of overall hits +system.cpu.dcache.overall_hits::total 20023737 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1306607 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1306607 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1621495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1621495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1621495 # number of overall misses +system.cpu.dcache.overall_misses::total 1621495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18344083000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18344083000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556368000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8556368000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26900451000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26900451000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26900451000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26900451000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13294871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13294871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8350361 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350361 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21645232 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21645232 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21645232 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21645232 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098279 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098279 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037710 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037710 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074912 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074912 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074912 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074912 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14039.480119 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14039.480119 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27172.734433 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27172.734433 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16589.906845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16589.906845 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,46 +639,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538028 # number of writebacks -system.cpu.dcache.writebacks::total 1538028 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308145 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1308145 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315486 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1623631 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1623631 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1623631 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1623631 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697346000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23769091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769091500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23769091500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469978500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469978500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96617154500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96617154500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098433 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098433 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037781 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037781 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.698810 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.698810 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1536049 # number of writebacks +system.cpu.dcache.writebacks::total 1536049 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306607 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1306607 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1621495 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1621495 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1621495 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1621495 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15730869000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15730869000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926592000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926592000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23657461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23657461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23657461000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23657461000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467832500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467832500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613781500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613781500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037710 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037710 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074912 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074912 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.480119 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.480119 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25172.734433 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25172.734433 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -682,127 +686,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 87015 # number of replacements -system.cpu.l2cache.tagsinuse 64709.520704 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3488531 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 151765 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.986400 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 86864 # number of replacements +system.cpu.l2cache.tagsinuse 64770.429000 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3484731 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.981653 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50328.696692 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140121 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3391.684309 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10988.999582 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86592298500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2307004500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2307004500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88899303000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88899303000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021749 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019607 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.805288 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141743 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154621 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56252 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281260 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 630045573 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1296264296 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1926647381 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14542846 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14542846 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190240726 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190240726 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281260 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 630045573 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5486505022 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6116888107 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56252 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281260 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 630045573 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5486505022 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6116888107 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305021500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896197000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896197000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063901 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48946.983608 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45667.229029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46691.888156 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36964.667037 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36964.667037 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 015bc1924..c8eb78d93 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.200409 # Number of seconds simulated -sim_ticks 200409284500 # Number of ticks simulated -final_tick 4321205328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 200409293000 # Number of ticks simulated +final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 13697441 # Simulator instruction rate (inst/s) -host_op_rate 13697433 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5245128514 # Simulator tick rate (ticks/s) -host_mem_usage 514692 # Number of bytes of host memory used -host_seconds 38.21 # Real time elapsed on the host -sim_insts 523360203 # Number of instructions simulated -sim_ops 523360203 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 80888044 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 27771396 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 50103096 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 158762536 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 80888044 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 80888044 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 16575224 # Number of bytes written to this memory +host_inst_rate 19440889 # Simulator instruction rate (inst/s) +host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7408936081 # Simulator tick rate (ticks/s) +host_mem_usage 472492 # Number of bytes of host memory used +host_seconds 27.05 # Real time elapsed on the host +sim_insts 525869186 # Number of instructions simulated +sim_ops 525869186 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 27826180 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 51169128 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 160043872 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 81048564 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 81048564 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 16606324 # Number of bytes written to this memory testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 16576126 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 20222011 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 3834989 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 2087611 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 26144611 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 2254078 # Number of write requests responded to by this memory +testsys.physmem.bytes_written::total 16607226 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 20262141 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 3842564 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 2132029 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 26236734 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 2258349 # Number of write requests responded to by this memory testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 2254109 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 403614255 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 138573400 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 250003866 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 792191521 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 403614255 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 403614255 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 82706867 # Write bandwidth from this memory (bytes/s) +testsys.physmem.num_writes::total 2258380 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 404415198 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 138846755 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 255323130 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 798585084 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 404415198 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 404415198 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 82862046 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 82711368 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 403614255 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 221280267 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 250008367 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 874902889 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_write::total 82866547 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 404415198 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 221708801 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 255327631 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 881451630 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.readReqs 0 # Total number of read requests seen testsys.physmem.writeReqs 0 # Total number of write requests seen testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -189,7 +189,7 @@ testsys.physmem.avgRdBW 0.00 # Av testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s testsys.physmem.busUtil 0.00 # Data bus utilization in percentage testsys.physmem.avgRdQLen 0.00 # Average read queue length over time testsys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -214,22 +214,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 3909164 # DTB read hits +testsys.cpu.dtb.read_hits 3916928 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.read_acv 80 # DTB read access violations testsys.cpu.dtb.read_accesses 225414 # DTB read accesses -testsys.cpu.dtb.write_hits 2312434 # DTB write hits +testsys.cpu.dtb.write_hits 2316846 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.dtb.write_acv 81 # DTB write access violations testsys.cpu.dtb.write_accesses 109988 # DTB write accesses -testsys.cpu.dtb.data_hits 6221598 # DTB hits +testsys.cpu.dtb.data_hits 6233774 # DTB hits testsys.cpu.dtb.data_misses 3815 # DTB misses testsys.cpu.dtb.data_acv 161 # DTB access violations testsys.cpu.dtb.data_accesses 335402 # DTB accesses -testsys.cpu.itb.fetch_hits 4045775 # ITB hits +testsys.cpu.itb.fetch_hits 4052272 # ITB hits testsys.cpu.itb.fetch_misses 1497 # ITB misses testsys.cpu.itb.fetch_acv 69 # ITB acv -testsys.cpu.itb.fetch_accesses 4047272 # ITB accesses +testsys.cpu.itb.fetch_accesses 4053769 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -242,51 +242,51 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 400807419 # number of cpu cycles simulated +testsys.cpu.numCycles 400815936 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 20218035 # Number of instructions committed -testsys.cpu.committedOps 20218035 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 18800192 # Number of integer alu accesses -testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses -testsys.cpu.num_func_calls 1218514 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 1439639 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 18800192 # number of integer instructions -testsys.cpu.num_fp_insts 17380 # number of float instructions -testsys.cpu.num_int_register_reads 24739164 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 14664877 # number of times the integer registers were written -testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read -testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written -testsys.cpu.num_mem_refs 6250795 # number of memory refs -testsys.cpu.num_load_insts 3936233 # Number of load instructions -testsys.cpu.num_store_insts 2314562 # Number of store instructions -testsys.cpu.num_idle_cycles 380584404.581032 # Number of idle cycles -testsys.cpu.num_busy_cycles 20223014.418968 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.050456 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.949544 # Percentage of idle cycles +testsys.cpu.committedInsts 20258165 # Number of instructions committed +testsys.cpu.committedOps 20258165 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 18837392 # Number of integer alu accesses +testsys.cpu.num_fp_alu_accesses 17313 # Number of float alu accesses +testsys.cpu.num_func_calls 1221260 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 1442190 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 18837392 # number of integer instructions +testsys.cpu.num_fp_insts 17313 # number of float instructions +testsys.cpu.num_int_register_reads 24787608 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 14694255 # number of times the integer registers were written +testsys.cpu.num_fp_register_reads 11133 # number of times the floating registers were read +testsys.cpu.num_fp_register_writes 10789 # number of times the floating registers were written +testsys.cpu.num_mem_refs 6263009 # number of memory refs +testsys.cpu.num_load_insts 3944038 # Number of load instructions +testsys.cpu.num_store_insts 2318971 # Number of store instructions +testsys.cpu.num_idle_cycles 380552362.972989 # Number of idle cycles +testsys.cpu.num_busy_cycles 20263573.027011 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.050556 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.949444 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 19525 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 153371 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 62656 42.67% 42.67% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 19578 13.33% 56.01% # number of times we switched to this ipl +testsys.cpu.kern.inst.quiesce 19598 # number of quiesce instructions executed +testsys.cpu.kern.inst.hwrei 153677 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 62790 42.68% 42.68% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 19620 13.34% 56.01% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 64383 43.85% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 146822 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 62650 43.18% 43.18% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 19578 13.49% 56.67% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_count::31 64514 43.85% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 147129 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 62784 43.18% 43.18% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 19620 13.49% 56.67% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 62661 43.19% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 145094 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 194361437500 96.98% 96.98% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 1585244500 0.79% 97.78% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_good::31 62791 43.19% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 145400 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 194352160500 96.98% 96.98% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 1588908500 0.79% 97.77% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 4448431000 2.22% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 200403928000 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 4458302500 2.22% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 200408186500 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.973254 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.988231 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::31 0.973293 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.988248 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed @@ -309,30 +309,30 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.kern.syscall::total 83 # number of syscalls executed -testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed +testsys.cpu.kern.callpal::swpctx 437 0.34% 0.34% # number of callpals executed testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed -testsys.cpu.kern.callpal::swpipl 106626 83.26% 83.62% # number of callpals executed +testsys.cpu.kern.callpal::swpipl 106841 83.26% 83.62% # number of callpals executed testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed -testsys.cpu.kern.callpal::rdusp 3 0.00% 83.91% # number of callpals executed -testsys.cpu.kern.callpal::rti 20424 15.95% 99.86% # number of callpals executed +testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed +testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 128057 # number of callpals executed -testsys.cpu.kern.mode_switch::kernel 1279 # number of protection mode switches -testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 19584 # number of protection mode switches +testsys.cpu.kern.callpal::total 128317 # number of callpals executed +testsys.cpu.kern.mode_switch::kernel 1281 # number of protection mode switches +testsys.cpu.kern.mode_switch::user 703 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 19627 # number of protection mode switches testsys.cpu.kern.mode_good::kernel 707 -testsys.cpu.kern.mode_good::user 702 -testsys.cpu.kern.mode_good::idle 5 -testsys.cpu.kern.mode_switch_good::kernel 0.552776 # fraction of useful protection mode switches +testsys.cpu.kern.mode_good::user 703 +testsys.cpu.kern.mode_good::idle 4 +testsys.cpu.kern.mode_switch_good::kernel 0.551913 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::total 0.065569 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks::kernel 993857000 59.77% 59.77% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::user 533068000 32.06% 91.82% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::idle 135946500 8.18% 100.00% # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 438 # number of times the context was actually changed +testsys.cpu.kern.mode_switch_good::idle 0.000204 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks::kernel 1002766500 60.53% 60.53% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::user 533073000 32.18% 92.70% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::idle 120928500 7.30% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 437 # number of times the context was actually changed testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted testsys.tsunami.ethernet.rxBytes 798 # Bytes Received testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted @@ -343,9 +343,9 @@ testsys.tsunami.ethernet.txTcpChecksums 2 # Nu testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -testsys.tsunami.ethernet.descDMAReads 2087576 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 2131994 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 50101824 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 51167856 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) testsys.tsunami.ethernet.totPackets 13 # Total Packets @@ -370,9 +370,9 @@ testsys.tsunami.ethernet.totalRxDesc 5 # to testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 19525 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 2087576 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 2131994 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -380,37 +380,37 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 2087594 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 2132012 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read::cpu.inst 76121948 # Number of bytes read from this memory -drivesys.physmem.bytes_read::cpu.data 26255588 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 50103126 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 152480662 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read::cpu.inst 76121948 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_inst_read::total 76121948 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written::cpu.data 14603776 # Number of bytes written to this memory +drivesys.physmem.bytes_read::cpu.inst 76288612 # Number of bytes read from this memory +drivesys.physmem.bytes_read::cpu.data 26312880 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 51169134 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 153770626 # Number of bytes read from this memory +drivesys.physmem.bytes_inst_read::cpu.inst 76288612 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_inst_read::total 76288612 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_written::cpu.data 14635456 # Number of bytes written to this memory drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory -drivesys.physmem.bytes_written::total 14604840 # Number of bytes written to this memory -drivesys.physmem.num_reads::cpu.inst 19030487 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::cpu.data 3643074 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 2087613 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 24761174 # Number of read requests responded to by this memory -drivesys.physmem.num_writes::cpu.data 2022588 # Number of write requests responded to by this memory +drivesys.physmem.bytes_written::total 14636520 # Number of bytes written to this memory +drivesys.physmem.num_reads::cpu.inst 19072153 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::cpu.data 3651006 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 2132030 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 24855189 # Number of read requests responded to by this memory +drivesys.physmem.num_writes::cpu.data 2026958 # Number of write requests responded to by this memory drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory -drivesys.physmem.num_writes::total 2022625 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 379832442 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 131009839 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 250004016 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 760846297 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 379832442 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 379832442 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 72869758 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.num_writes::total 2026995 # Number of write requests responded to by this memory +drivesys.physmem.bw_read::cpu.inst 380664044 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 131295708 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 255323160 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 767282912 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 380664044 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 380664044 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 73027831 # Write bandwidth from this memory (bytes/s) drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 72875067 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 379832442 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 203879596 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 250009325 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 833721364 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_write::total 73033140 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 380664044 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 204323539 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 255328469 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 840316053 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.readReqs 0 # Total number of read requests seen drivesys.physmem.writeReqs 0 # Total number of write requests seen drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -560,7 +560,7 @@ drivesys.physmem.avgRdBW 0.00 # Av drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -585,22 +585,22 @@ drivesys.cpu.dtb.fetch_hits 0 # IT drivesys.cpu.dtb.fetch_misses 0 # ITB misses drivesys.cpu.dtb.fetch_acv 0 # ITB acv drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses -drivesys.cpu.dtb.read_hits 3721202 # DTB read hits +drivesys.cpu.dtb.read_hits 3729326 # DTB read hits drivesys.cpu.dtb.read_misses 487 # DTB read misses drivesys.cpu.dtb.read_acv 30 # DTB read access violations drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses -drivesys.cpu.dtb.write_hits 2081819 # DTB write hits +drivesys.cpu.dtb.write_hits 2086333 # DTB write hits drivesys.cpu.dtb.write_misses 82 # DTB write misses drivesys.cpu.dtb.write_acv 10 # DTB write access violations drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses -drivesys.cpu.dtb.data_hits 5803021 # DTB hits +drivesys.cpu.dtb.data_hits 5815659 # DTB hits drivesys.cpu.dtb.data_misses 569 # DTB misses drivesys.cpu.dtb.data_acv 40 # DTB access violations drivesys.cpu.dtb.data_accesses 401230 # DTB accesses -drivesys.cpu.itb.fetch_hits 4194101 # ITB hits +drivesys.cpu.itb.fetch_hits 4201097 # ITB hits drivesys.cpu.itb.fetch_misses 194 # ITB misses drivesys.cpu.itb.fetch_acv 22 # ITB acv -drivesys.cpu.itb.fetch_accesses 4194295 # ITB accesses +drivesys.cpu.itb.fetch_accesses 4201291 # ITB accesses drivesys.cpu.itb.read_hits 0 # DTB read hits drivesys.cpu.itb.read_misses 0 # DTB read misses drivesys.cpu.itb.read_acv 0 # DTB read access violations @@ -613,51 +613,51 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 801639056 # number of cpu cycles simulated +drivesys.cpu.numCycles 801619128 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.committedInsts 19029878 # Number of instructions committed -drivesys.cpu.committedOps 19029878 # Number of ops (including micro ops) committed -drivesys.cpu.num_int_alu_accesses 17721251 # Number of integer alu accesses +drivesys.cpu.committedInsts 19071544 # Number of instructions committed +drivesys.cpu.committedOps 19071544 # Number of ops (including micro ops) committed +drivesys.cpu.num_int_alu_accesses 17759891 # Number of integer alu accesses drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses -drivesys.cpu.num_func_calls 1263632 # number of times a function call or return occured -drivesys.cpu.num_conditional_control_insts 1263629 # number of instructions that are conditional controls -drivesys.cpu.num_int_insts 17721251 # number of integer instructions +drivesys.cpu.num_func_calls 1266408 # number of times a function call or return occured +drivesys.cpu.num_conditional_control_insts 1266328 # number of instructions that are conditional controls +drivesys.cpu.num_int_insts 17759891 # number of integer instructions drivesys.cpu.num_fp_insts 1412 # number of float instructions -drivesys.cpu.num_int_register_reads 23047059 # number of times the integer registers were read -drivesys.cpu.num_int_register_writes 13965767 # number of times the integer registers were written +drivesys.cpu.num_int_register_reads 23097438 # number of times the integer registers were read +drivesys.cpu.num_int_register_writes 13996340 # number of times the integer registers were written drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written -drivesys.cpu.num_mem_refs 5824433 # number of memory refs -drivesys.cpu.num_load_insts 3742101 # Number of load instructions -drivesys.cpu.num_store_insts 2082332 # Number of store instructions -drivesys.cpu.num_idle_cycles 782608307.467164 # Number of idle cycles -drivesys.cpu.num_busy_cycles 19030748.532836 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.023740 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.976260 # Percentage of idle cycles +drivesys.cpu.num_mem_refs 5837119 # number of memory refs +drivesys.cpu.num_load_insts 3750273 # Number of load instructions +drivesys.cpu.num_store_insts 2086846 # Number of store instructions +drivesys.cpu.num_idle_cycles 782547188.298833 # Number of idle cycles +drivesys.cpu.num_busy_cycles 19071939.701167 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.023792 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.976208 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.quiesce 19854 # number of quiesce instructions executed -drivesys.cpu.kern.inst.hwrei 143418 # number of hwrei instructions executed -drivesys.cpu.kern.ipl_count::0 60285 42.42% 42.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::21 19703 13.86% 56.28% # number of times we switched to this ipl +drivesys.cpu.kern.inst.quiesce 19898 # number of quiesce instructions executed +drivesys.cpu.kern.inst.hwrei 143758 # number of hwrei instructions executed +drivesys.cpu.kern.ipl_count::0 60430 42.42% 42.42% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::21 19752 13.86% 56.28% # number of times we switched to this ipl drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::31 61936 43.58% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::total 142129 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good::0 60285 42.91% 42.91% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::21 19703 14.03% 56.94% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_count::31 62082 43.58% 100.00% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::total 142469 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good::0 60430 42.91% 42.91% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::21 19752 14.03% 56.94% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::31 60286 42.91% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::total 140479 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 197404825250 98.50% 98.50% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 797938750 0.40% 98.90% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_good::31 60432 42.91% 100.00% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::total 140819 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks::0 197392680000 98.50% 98.50% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 799890500 0.40% 98.90% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::31 2202592500 1.10% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 200409764000 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::31 2207804000 1.10% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 200404782000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::31 0.973360 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::total 0.988391 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::31 0.973422 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::total 0.988419 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed @@ -673,26 +673,26 @@ drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # nu drivesys.cpu.kern.syscall::total 22 # number of syscalls executed drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed -drivesys.cpu.kern.callpal::swpipl 102208 83.31% 83.37% # number of callpals executed +drivesys.cpu.kern.callpal::swpipl 102452 83.31% 83.37% # number of callpals executed drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed -drivesys.cpu.kern.callpal::rti 20014 16.31% 99.97% # number of callpals executed +drivesys.cpu.kern.callpal::rti 20062 16.31% 99.97% # number of callpals executed drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed -drivesys.cpu.kern.callpal::total 122686 # number of callpals executed +drivesys.cpu.kern.callpal::total 122978 # number of callpals executed drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches -drivesys.cpu.kern.mode_switch::idle 19872 # number of protection mode switches +drivesys.cpu.kern.mode_switch::idle 19920 # number of protection mode switches drivesys.cpu.kern.mode_good::kernel 143 drivesys.cpu.kern.mode_good::user 139 drivesys.cpu.kern.mode_good::idle 4 drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::total 0.014141 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::total 0.014107 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::user 319665750 10.81% 13.45% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::idle 2560362000 86.55% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::user 319665750 10.79% 13.43% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::idle 2564974000 86.57% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received @@ -704,9 +704,9 @@ drivesys.tsunami.ethernet.txTcpChecksums 2 # Nu drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -drivesys.tsunami.ethernet.descDMAReads 2087584 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 2132001 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 50102016 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 51168024 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) drivesys.tsunami.ethernet.totPackets 13 # Total Packets @@ -731,9 +731,9 @@ drivesys.tsunami.ethernet.totalRxDesc 8 # to drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -drivesys.tsunami.ethernet.postedTxIdle 19702 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 19750 # number of TxIdle interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 2087584 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 2132001 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -741,49 +741,49 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 2087605 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 2132022 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- ---------- Begin Simulation Statistics ---------- sim_seconds 0.000407 # Number of seconds simulated -sim_ticks 406952000 # Number of ticks simulated -final_tick 4321612280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 407365500 # Number of ticks simulated +final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 7058170696 # Simulator instruction rate (inst/s) -host_op_rate 7056390513 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5484794115 # Simulator tick rate (ticks/s) -host_mem_usage 514692 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -sim_insts 523432506 # Number of instructions simulated -sim_ops 523432506 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 144604 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 296292 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 144604 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 144604 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 27688 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 36151 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 47299 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 355334290 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 728076038 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 355334290 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 355334290 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 355334290 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 796113547 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 12024534237 # Simulator instruction rate (inst/s) +host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9308365303 # Simulator tick rate (ticks/s) +host_mem_usage 472492 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +sim_insts 525940622 # Number of instructions simulated +sim_ops 525940622 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 48760 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 103992 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 293888 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 141136 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 141136 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 27028 # Number of bytes written to this memory +testsys.physmem.bytes_written::total 27028 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 35284 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 6744 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 4333 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 46361 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 3721 # Number of write requests responded to by this memory +testsys.physmem.num_writes::total 3721 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 346460365 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 119695949 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 255279350 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 721435664 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 346460365 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 346460365 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 66348279 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::total 66348279 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 346460365 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 186044228 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 255279350 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 787783943 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.readReqs 0 # Total number of read requests seen testsys.physmem.writeReqs 0 # Total number of write requests seen testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -933,7 +933,7 @@ testsys.physmem.avgRdBW 0.00 # Av testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s testsys.physmem.busUtil 0.00 # Data bus utilization in percentage testsys.physmem.avgRdQLen 0.00 # Average read queue length over time testsys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -958,22 +958,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 7069 # DTB read hits +testsys.cpu.dtb.read_hits 6900 # DTB read hits testsys.cpu.dtb.read_misses 0 # DTB read misses testsys.cpu.dtb.read_acv 0 # DTB read access violations testsys.cpu.dtb.read_accesses 0 # DTB read accesses -testsys.cpu.dtb.write_hits 3933 # DTB write hits +testsys.cpu.dtb.write_hits 3839 # DTB write hits testsys.cpu.dtb.write_misses 0 # DTB write misses testsys.cpu.dtb.write_acv 0 # DTB write access violations testsys.cpu.dtb.write_accesses 0 # DTB write accesses -testsys.cpu.dtb.data_hits 11002 # DTB hits +testsys.cpu.dtb.data_hits 10739 # DTB hits testsys.cpu.dtb.data_misses 0 # DTB misses testsys.cpu.dtb.data_acv 0 # DTB access violations testsys.cpu.dtb.data_accesses 0 # DTB accesses -testsys.cpu.itb.fetch_hits 5992 # ITB hits +testsys.cpu.itb.fetch_hits 5847 # ITB hits testsys.cpu.itb.fetch_misses 0 # ITB misses testsys.cpu.itb.fetch_acv 0 # ITB acv -testsys.cpu.itb.fetch_accesses 5992 # ITB accesses +testsys.cpu.itb.fetch_accesses 5847 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -986,58 +986,58 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 821760 # number of cpu cycles simulated +testsys.cpu.numCycles 799188 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 36151 # Number of instructions committed -testsys.cpu.committedOps 36151 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 33514 # Number of integer alu accesses +testsys.cpu.committedInsts 35284 # Number of instructions committed +testsys.cpu.committedOps 35284 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 32710 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -testsys.cpu.num_func_calls 2388 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 2348 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 33514 # number of integer instructions +testsys.cpu.num_func_calls 2330 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 2292 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 32710 # number of integer instructions testsys.cpu.num_fp_insts 0 # number of float instructions -testsys.cpu.num_int_register_reads 43768 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 26496 # number of times the integer registers were written +testsys.cpu.num_int_register_reads 42720 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 25860 # number of times the integer registers were written testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written -testsys.cpu.num_mem_refs 11043 # number of memory refs -testsys.cpu.num_load_insts 7109 # Number of load instructions -testsys.cpu.num_store_insts 3934 # Number of store instructions -testsys.cpu.num_idle_cycles 785260.061817 # Number of idle cycles -testsys.cpu.num_busy_cycles 36499.938183 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.044417 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.955583 # Percentage of idle cycles +testsys.cpu.num_mem_refs 10779 # number of memory refs +testsys.cpu.num_load_insts 6939 # Number of load instructions +testsys.cpu.num_store_insts 3840 # Number of store instructions +testsys.cpu.num_idle_cycles 764577.129267 # Number of idle cycles +testsys.cpu.num_busy_cycles 34610.870733 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.043308 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.956692 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 398338500 96.95% 96.95% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.74% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.75% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 9258500 2.25% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 410880000 # number of cycles we spent at this ipl +testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed +testsys.cpu.kern.inst.hwrei 288 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 120 41.81% 41.81% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 39 13.59% 55.40% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::22 1 0.35% 55.75% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::31 127 44.25% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 287 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 120 42.86% 42.86% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 39 13.93% 56.79% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::22 1 0.36% 57.14% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::31 120 42.86% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 280 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 387349500 96.94% 96.94% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 3159000 0.79% 97.73% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 9042500 2.26% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 399594000 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed -testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed -testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 254 # number of callpals executed +testsys.cpu.kern.ipl_used::31 0.944882 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.975610 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.callpal::swpipl 207 83.47% 83.47% # number of callpals executed +testsys.cpu.kern.callpal::rdps 1 0.40% 83.87% # number of callpals executed +testsys.cpu.kern.callpal::rti 40 16.13% 100.00% # number of callpals executed +testsys.cpu.kern.callpal::total 248 # number of callpals executed testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 40 # number of protection mode switches testsys.cpu.kern.mode_good::kernel 0 testsys.cpu.kern.mode_good::user 0 testsys.cpu.kern.mode_good::idle 0 @@ -1049,9 +1049,9 @@ testsys.cpu.kern.mode_ticks::kernel 0 # nu testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode testsys.cpu.kern.swap_context 0 # number of times the context was actually changed -testsys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 4333 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 103992 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1068,9 +1068,9 @@ testsys.tsunami.ethernet.totalRxDesc 0 # to testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 39 # number of TxIdle interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 4333 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -1078,34 +1078,34 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 4333 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 296296 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 104016 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 298576 # Number of bytes read from this memory drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 47300 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 4334 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 47395 # Number of read requests responded to by this memory drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 355344119 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 728085868 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 355344119 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 355344119 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 355344119 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 796123376 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.inst 354983424 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 122622068 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 255338265 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 732943757 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 354983424 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 354983424 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 67968446 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::total 67968446 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 354983424 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 190590514 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 255338265 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 800912203 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.readReqs 0 # Total number of read requests seen drivesys.physmem.writeReqs 0 # Total number of write requests seen drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -1255,7 +1255,7 @@ drivesys.physmem.avgRdBW 0.00 # Av drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -1308,7 +1308,7 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 1628160 # number of cpu cycles simulated +drivesys.cpu.numCycles 1624320 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed drivesys.cpu.committedInsts 36152 # Number of instructions committed @@ -1326,10 +1326,10 @@ drivesys.cpu.num_fp_register_writes 0 # nu drivesys.cpu.num_mem_refs 11043 # number of memory refs drivesys.cpu.num_load_insts 7109 # Number of load instructions drivesys.cpu.num_store_insts 3934 # Number of store instructions -drivesys.cpu.num_idle_cycles 1592000.182518 # Number of idle cycles -drivesys.cpu.num_busy_cycles 36159.817482 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.022209 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.977791 # Percentage of idle cycles +drivesys.cpu.num_idle_cycles 1588282.082886 # Number of idle cycles +drivesys.cpu.num_busy_cycles 36037.917114 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.022186 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.977814 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed @@ -1343,11 +1343,11 @@ drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # nu drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 400769000 98.46% 98.46% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::0 399809000 98.46% 98.46% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.85% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 407040000 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 406080000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1371,9 +1371,9 @@ drivesys.cpu.kern.mode_ticks::kernel 0 # nu drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed -drivesys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 4334 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 104016 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1392,7 +1392,7 @@ drivesys.tsunami.ethernet.coalescedTxOk 0 # av drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 4334 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -1400,7 +1400,7 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 4334 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index b21e4d084..9e62381ba 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18737000 # Number of ticks simulated -final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19476000 # Number of ticks simulated +final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42684 # Simulator instruction rate (inst/s) -host_op_rate 42679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 125129111 # Simulator tick rate (ticks/s) -host_mem_usage 269636 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 78389 # Simulator instruction rate (inst/s) +host_op_rate 78368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238789679 # Simulator tick rate (ticks/s) +host_mem_usage 223680 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1024710466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 573837861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1598548327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1024710466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1024710466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1024710466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 573837861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1598548327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 985828712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 552064079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1537892791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 985828712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 985828712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 985828712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 552064079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1537892791 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -37,21 +37,21 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 47 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18722500 # Total gap between requests +system.physmem.totGap 19461500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1862969 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11648969 # Sum of mem lat for all requests -system.physmem.totBusLat 1876000 # Total cycles spent in databus access -system.physmem.totBankLat 7910000 # Total cycles spent in bank access -system.physmem.avgQLat 3972.22 # Average queueing delay per request -system.physmem.avgBankLat 16865.67 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24837.89 # Average memory access latency -system.physmem.avgRdBW 1598.55 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2628216 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13374466 # Sum of mem lat for all requests +system.physmem.totBusLat 2345000 # Total cycles spent in databus access +system.physmem.totBankLat 8401250 # Total cycles spent in bank access +system.physmem.avgQLat 5603.87 # Average queueing delay per request +system.physmem.avgBankLat 17913.11 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28516.99 # Average memory access latency +system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1598.55 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.62 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 12.01 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.69 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 401 # Number of row buffer hits during reads +system.physmem.readRowHits 377 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 39920.04 # Average gap between requests +system.physmem.avgGap 41495.74 # Average gap between requests system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -202,14 +202,14 @@ system.cpu.dtb.read_hits 1183 # DT system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_hits 866 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.write_accesses 869 # DTB write accesses +system.cpu.dtb.data_hits 2049 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.dtb.data_accesses 2059 # DTB accesses system.cpu.itb.fetch_hits 915 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 37475 # number of cpu cycles simulated +system.cpu.numCycles 38953 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5201 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9769 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9768 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2948 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 2949 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2152 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken). @@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11520 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30101 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7374 # Number of cycles cpu stages are processed. -system.cpu.activity 19.677118 # Percentage of cycles cpu is active +system.cpu.timesIdled 503 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31578 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7375 # Number of cycles cpu stages are processed. +system.cpu.activity 18.933073 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -266,72 +266,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 5.864632 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.095931 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 5.864632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.170514 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.095931 # CPI: Total CPI of All Threads +system.cpu.ipc 0.164044 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.170514 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32551 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.164044 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34029 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.139426 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33582 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 12.640875 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35060 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 10.388259 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33313 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4162 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 11.106071 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36170 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.482322 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 32961 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4514 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 12.045364 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.utilization 9.994095 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34792 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 10.682104 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 37647 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1306 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.352758 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 34441 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4512 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 11.583190 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.133594 # Cycle average of tags in use -system.cpu.icache.total_refs 561 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 142.957443 # Cycle average of tags in use +system.cpu.icache.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.863787 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.133594 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069889 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069889 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 561 # number of overall hits -system.cpu.icache.overall_hits::total 561 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 354 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 354 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 354 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 354 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 354 # number of overall misses -system.cpu.icache.overall_misses::total 354 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17402500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17402500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17402500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17402500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17402500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17402500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 142.957443 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069803 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069803 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 560 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 560 # number of overall hits +system.cpu.icache.overall_hits::total 560 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 355 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 355 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 355 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses +system.cpu.icache.overall_misses::total 355 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18504000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18504000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18504000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18504000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18504000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18504000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386885 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.386885 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.386885 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.386885 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.386885 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.386885 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49159.604520 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49159.604520 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49159.604520 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49159.604520 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.387978 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.387978 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52123.943662 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52123.943662 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52123.943662 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52123.943662 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -340,48 +340,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14751500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14751500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15862500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15862500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48846.026490 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48846.026490 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52524.834437 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52524.834437 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 200.167240 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.973805 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.234891 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.932349 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 143.049582 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.924223 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006109 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -399,17 +399,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14433000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4976500 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -432,17 +432,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47950.166113 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52384.210526 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49013.888889 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49260.273973 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49260.273973 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49052.238806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49052.238806 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51641.196013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56257.894737 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52748.737374 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48746.575342 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48746.575342 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52125.799574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52125.799574 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,17 +462,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17114216 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177366 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993865 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666348 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666348 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843714 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18660213 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843714 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18660213 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -484,27 +484,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35375.415282 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43972.273684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40388.547980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36525.315068 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36525.315068 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 104.225653 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 104.225653 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025446 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025446 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 104.433203 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025496 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025496 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -521,14 +521,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5353500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5353500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14913500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14913500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20267000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20267000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20267000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20267000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5722500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5722500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15380500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15380500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21103000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21103000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21103000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21103000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -545,19 +545,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55190.721649 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55190.721649 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42610 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42610 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45340.044743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45340.044743 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58994.845361 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58994.845361 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43944.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43944.285714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47210.290828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47210.290828 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 178 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -577,14 +577,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3673500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3673500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8751500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8751500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8751500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8751500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3636000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3636000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9082000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9082000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -593,14 +593,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53452.631579 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53452.631579 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50321.917808 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50321.917808 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49808.219178 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49808.219178 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index a295cf48e..d7bf6a6b9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 15802500 # Number of ticks simulated -final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16030500 # Number of ticks simulated +final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36566 # Simulator instruction rate (inst/s) -host_op_rate 36562 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90663114 # Simulator tick rate (ticks/s) -host_mem_usage 270656 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 76258 # Simulator instruction rate (inst/s) +host_op_rate 76239 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191753794 # Simulator tick rate (ticks/s) +host_mem_usage 225728 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory -system.physmem.bytes_read::total 31168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1267647524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 704698624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1972346148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1267647524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1267647524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1267647524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 704698624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1972346148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 487 # Total number of read requests seen +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 31168 # Total number of bytes read from memory +system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 31104 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 47 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 45 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15655000 # Total gap between requests +system.physmem.totGap 15817000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 487 # Categorize read packet sizes +system.physmem.readPktSize::6 486 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3073487 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12819487 # Sum of mem lat for all requests -system.physmem.totBusLat 1948000 # Total cycles spent in databus access -system.physmem.totBankLat 7798000 # Total cycles spent in bank access -system.physmem.avgQLat 6311.06 # Average queueing delay per request -system.physmem.avgBankLat 16012.32 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26323.38 # Average memory access latency -system.physmem.avgRdBW 1972.35 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2909986 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests +system.physmem.totBusLat 2430000 # Total cycles spent in databus access +system.physmem.totBankLat 8305000 # Total cycles spent in bank access +system.physmem.avgQLat 5987.63 # Average queueing delay per request +system.physmem.avgBankLat 17088.48 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28076.10 # Average memory access latency +system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1972.35 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.33 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.81 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 416 # Number of row buffer hits during reads +system.physmem.readRowHits 396 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32145.79 # Average gap between requests -system.cpu.branchPred.lookups 2927 # Number of BP lookups -system.cpu.branchPred.condPredicted 1718 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 517 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2238 # Number of BTB lookups -system.cpu.branchPred.BTBHits 757 # Number of BTB hits +system.physmem.avgGap 32545.27 # Average gap between requests +system.cpu.branchPred.lookups 2896 # Number of BP lookups +system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups +system.cpu.branchPred.BTBHits 746 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.824844 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2068 # DTB read hits +system.cpu.dtb.read_hits 2071 # DTB read hits system.cpu.dtb.read_misses 50 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2118 # DTB read accesses -system.cpu.dtb.write_hits 1071 # DTB write hits -system.cpu.dtb.write_misses 29 # DTB write misses +system.cpu.dtb.read_accesses 2121 # DTB read accesses +system.cpu.dtb.write_hits 1069 # DTB write hits +system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1100 # DTB write accesses -system.cpu.dtb.data_hits 3139 # DTB hits -system.cpu.dtb.data_misses 79 # DTB misses +system.cpu.dtb.write_accesses 1099 # DTB write accesses +system.cpu.dtb.data_hits 3140 # DTB hits +system.cpu.dtb.data_misses 80 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3218 # DTB accesses -system.cpu.itb.fetch_hits 2370 # ITB hits -system.cpu.itb.fetch_misses 39 # ITB misses +system.cpu.dtb.data_accesses 3220 # DTB accesses +system.cpu.itb.fetch_hits 2349 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2409 # ITB accesses +system.cpu.itb.fetch_accesses 2387 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,236 +227,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 31606 # number of cpu cycles simulated +system.cpu.numCycles 32062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1177 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2985 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1897 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1074 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 762 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2370 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.161487 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.555904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1142 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.139086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.536110 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11431 79.29% 79.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 317 2.20% 81.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 233 1.62% 83.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 212 1.47% 84.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 264 1.83% 86.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 229 1.59% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 265 1.84% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 186 1.29% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1279 8.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11558 79.66% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 185 1.28% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.092609 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.529773 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1146 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2779 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 90 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1222 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 249 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2753 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15526 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15363 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1222 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9389 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 326 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2653 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 349 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14793 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9517 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2631 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14679 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 317 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11113 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18446 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18429 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 11023 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18314 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18297 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6543 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 811 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2756 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6453 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2761 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10819 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6341 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14416 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.750486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.391653 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 13018 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10806 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.744779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.389331 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9926 68.85% 68.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1619 11.23% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1135 7.87% 87.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 768 5.33% 93.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 481 3.34% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 285 1.98% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 151 1.05% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 37 0.26% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10032 69.14% 69.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1598 11.01% 80.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 759 5.23% 93.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 472 3.25% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14509 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 14 11.97% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 64 54.70% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 63 53.39% 66.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 33.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7317 67.63% 67.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2355 21.77% 89.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1142 10.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7299 67.55% 67.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10819 # Type of FU issued -system.cpu.iq.rate 0.342308 # Inst issue rate -system.cpu.iq.fu_busy_cnt 117 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010814 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36206 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19446 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9723 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10806 # Type of FU issued +system.cpu.iq.rate 0.337034 # Inst issue rate +system.cpu.iq.fu_busy_cnt 118 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9700 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10923 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10911 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1573 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1578 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 90 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 87 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1222 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 52 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13186 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 157 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2756 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1363 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1212 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 522 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10167 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10154 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 87 # number of nop insts executed -system.cpu.iew.exec_refs 3231 # number of memory reference insts executed -system.cpu.iew.exec_branches 1614 # Number of branches executed -system.cpu.iew.exec_stores 1102 # Number of stores executed -system.cpu.iew.exec_rate 0.321679 # Inst execution rate -system.cpu.iew.wb_sent 9882 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9733 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5145 # num instructions producing a value -system.cpu.iew.wb_consumers 6933 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3233 # number of memory reference insts executed +system.cpu.iew.exec_branches 1613 # Number of branches executed +system.cpu.iew.exec_stores 1101 # Number of stores executed +system.cpu.iew.exec_rate 0.316699 # Inst execution rate +system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9710 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5134 # num instructions producing a value +system.cpu.iew.wb_consumers 6919 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.307948 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742103 # average fanout of values written-back +system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6795 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 435 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13194 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.484235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.303292 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.480484 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.303494 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10420 78.98% 78.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1475 11.18% 90.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 517 3.92% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 247 1.87% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 154 1.17% 97.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 92 0.70% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 106 0.80% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10548 79.33% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 514 3.87% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 101 0.76% 98.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 146 1.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13297 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -467,70 +467,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 146 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25881 # The number of ROB reads -system.cpu.rob.rob_writes 27599 # The number of ROB writes -system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17190 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25928 # The number of ROB reads +system.cpu.rob.rob_writes 27481 # The number of ROB writes +system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 4.960138 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.960138 # CPI: Total CPI of All Threads -system.cpu.ipc 0.201607 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.201607 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12907 # number of integer regfile reads -system.cpu.int_regfile_writes 7365 # number of integer regfile writes +system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12888 # number of integer regfile reads +system.cpu.int_regfile_writes 7343 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.479269 # Cycle average of tags in use -system.cpu.icache.total_refs 1894 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.031847 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use +system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.479269 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078359 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078359 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1894 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1894 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1894 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1894 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1894 # number of overall hits -system.cpu.icache.overall_hits::total 1894 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 476 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 476 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 476 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 476 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 476 # number of overall misses -system.cpu.icache.overall_misses::total 476 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21386500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21386500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21386500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21386500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21386500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21386500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2370 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2370 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2370 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2370 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2370 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2370 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200844 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.200844 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.200844 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.200844 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.200844 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.200844 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44929.621849 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44929.621849 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44929.621849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44929.621849 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1869 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1869 # number of overall hits +system.cpu.icache.overall_hits::total 1869 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses +system.cpu.icache.overall_misses::total 480 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2349 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2349 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2349 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204342 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.204342 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -539,109 +539,109 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 162 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 162 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 162 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 162 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15404000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15404000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15404000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15404000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15404000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15404000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132489 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.132489 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.132489 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49057.324841 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49057.324841 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.834334 # Cycle average of tags in use -system.cpu.dcache.total_refs 2264 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.713176 # Cycle average of tags in use +system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.011494 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.834334 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026327 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026327 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1758 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2264 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2264 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2264 # number of overall hits -system.cpu.dcache.overall_hits::total 2264 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2262 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2262 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2262 # number of overall hits +system.cpu.dcache.overall_hits::total 2262 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -720,43 +720,43 @@ system.cpu.dcache.demand_misses::cpu.data 528 # n system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses system.cpu.dcache.overall_misses::total 528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9065500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9065500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15837484 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15837484 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24902984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24902984 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24902984 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24902984 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9127000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9127000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25020487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25020487 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25020487 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25020487 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1925 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2792 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2792 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2792 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2792 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087701 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087701 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2790 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2790 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2790 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2790 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087792 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087792 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.189112 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.189112 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.189112 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.189112 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53642.011834 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53642.011834 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44115.554318 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44115.554318 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47164.742424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47164.742424 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 801 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.189247 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.189247 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.189247 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.189247 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54005.917160 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54005.917160 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44271.551532 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44271.551532 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47387.285985 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47387.285985 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807692 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.478261 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,30 +776,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6319000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6319000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3813500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3813500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10132500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10132500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10132500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10132500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052413 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052413 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6189000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6189000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3763500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3763500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9952500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9952500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052468 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052468 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062321 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062321 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62564.356436 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62564.356436 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52239.726027 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52239.726027 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062366 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062366 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61277.227723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61277.227723 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 0c67bfe34..6b89534e6 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9059000 # Number of ticks simulated -final_tick 9059000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 9350000 # Number of ticks simulated +final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 18337 # Simulator instruction rate (inst/s) -host_op_rate 18335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69572663 # Simulator tick rate (ticks/s) -host_mem_usage 270376 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 146 # Simulator instruction rate (inst/s) +host_op_rate 146 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 570039 # Simulator tick rate (ticks/s) +host_mem_usage 224412 # Number of bytes of host memory used +host_seconds 16.40 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1321117121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 600507782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1921624903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1321117121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1321117121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1321117121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 600507782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1921624903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1280000000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 581818182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1861818182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1280000000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1280000000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1280000000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 581818182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1861818182 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 17408 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 21 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 8990500 # Total gap between requests +system.physmem.totGap 9280500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1180771 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6930771 # Sum of mem lat for all requests -system.physmem.totBusLat 1088000 # Total cycles spent in databus access -system.physmem.totBankLat 4662000 # Total cycles spent in bank access -system.physmem.avgQLat 4341.07 # Average queueing delay per request -system.physmem.avgBankLat 17139.71 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25480.78 # Average memory access latency -system.physmem.avgRdBW 1921.62 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 1329022 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7872772 # Sum of mem lat for all requests +system.physmem.totBusLat 1360000 # Total cycles spent in databus access +system.physmem.totBankLat 5183750 # Total cycles spent in bank access +system.physmem.avgQLat 4886.11 # Average queueing delay per request +system.physmem.avgBankLat 19057.90 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28944.01 # Average memory access latency +system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1921.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.77 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.55 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.84 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 228 # Number of row buffer hits during reads +system.physmem.readRowHits 207 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33053.31 # Average gap between requests -system.cpu.branchPred.lookups 1180 # Number of BP lookups -system.cpu.branchPred.condPredicted 594 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 261 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 806 # Number of BTB lookups -system.cpu.branchPred.BTBHits 235 # Number of BTB hits +system.physmem.avgGap 34119.49 # Average gap between requests +system.cpu.branchPred.lookups 1154 # Number of BP lookups +system.cpu.branchPred.condPredicted 581 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 791 # Number of BTB lookups +system.cpu.branchPred.BTBHits 226 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.156328 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 28.571429 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 39 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 717 # DTB read hits -system.cpu.dtb.read_misses 25 # DTB read misses +system.cpu.dtb.read_hits 708 # DTB read hits +system.cpu.dtb.read_misses 28 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 742 # DTB read accesses -system.cpu.dtb.write_hits 359 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses +system.cpu.dtb.read_accesses 736 # DTB read accesses +system.cpu.dtb.write_hits 357 # DTB write hits +system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 378 # DTB write accesses -system.cpu.dtb.data_hits 1076 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 377 # DTB write accesses +system.cpu.dtb.data_hits 1065 # DTB hits +system.cpu.dtb.data_misses 48 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1120 # DTB accesses -system.cpu.itb.fetch_hits 1063 # ITB hits +system.cpu.dtb.data_accesses 1113 # DTB accesses +system.cpu.itb.fetch_hits 1043 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1093 # ITB accesses +system.cpu.itb.fetch_accesses 1073 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,237 +227,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 18119 # number of cpu cycles simulated +system.cpu.numCycles 18701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4211 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7069 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1180 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 462 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1219 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 881 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 344 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1194 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 306 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 959 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1024 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1063 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 190 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.961769 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.375037 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.949044 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.362722 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6131 83.41% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57 0.78% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 120 1.63% 85.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.29% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 168 2.29% 89.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 73 0.99% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.91% 91.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.87% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 575 7.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6126 83.69% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 114 1.56% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 168 2.30% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 73 1.00% 90.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065125 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.390143 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5296 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 369 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1168 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 510 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 170 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5332 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1148 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 500 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6269 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 510 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5398 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 91 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1075 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5981 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5432 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1056 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 37 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5903 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4351 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6729 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6717 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 4293 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6642 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6630 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2583 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2525 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 979 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 463 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 133 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 964 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 466 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5055 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 5010 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4086 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2501 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1445 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4065 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.555918 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.264810 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.555328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.267026 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5719 77.81% 77.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 555 7.55% 85.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 404 5.50% 90.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.55% 94.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 214 2.91% 97.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 126 1.71% 99.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 50 0.68% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14 0.19% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5695 77.80% 77.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 561 7.66% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 261 3.57% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15 0.20% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7320 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21 45.65% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2910 71.22% 71.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 789 19.31% 90.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 386 9.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2890 71.09% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 787 19.36% 90.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 387 9.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4086 # Type of FU issued -system.cpu.iq.rate 0.225509 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010768 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15607 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7560 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3685 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4065 # Type of FU issued +system.cpu.iq.rate 0.217368 # Inst issue rate +system.cpu.iq.fu_busy_cnt 46 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15536 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4123 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4104 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 564 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 549 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 169 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 172 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 510 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 82 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 500 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 100 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5405 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 979 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 463 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 5355 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 129 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 964 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 466 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3887 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 743 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 199 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 159 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3852 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 737 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 213 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 344 # number of nop insts executed -system.cpu.iew.exec_refs 1121 # number of memory reference insts executed -system.cpu.iew.exec_branches 656 # Number of branches executed -system.cpu.iew.exec_stores 378 # Number of stores executed -system.cpu.iew.exec_rate 0.214526 # Inst execution rate -system.cpu.iew.wb_sent 3770 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3691 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1735 # num instructions producing a value -system.cpu.iew.wb_consumers 2218 # num instructions consuming a value +system.cpu.iew.exec_nop 339 # number of nop insts executed +system.cpu.iew.exec_refs 1114 # number of memory reference insts executed +system.cpu.iew.exec_branches 649 # Number of branches executed +system.cpu.iew.exec_stores 377 # Number of stores executed +system.cpu.iew.exec_rate 0.205978 # Inst execution rate +system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3664 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1730 # num instructions producing a value +system.cpu.iew.wb_consumers 2229 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.203709 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.782236 # average fanout of values written-back +system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.776133 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2808 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 183 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.234221 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6820 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.377713 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238824 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5975 87.35% 87.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 201 2.94% 90.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 309 4.52% 94.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 115 1.68% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 68 0.99% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 49 0.72% 98.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.48% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.34% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5956 87.33% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 310 4.55% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 116 1.70% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23 0.34% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6820 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,119 +468,119 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11910 # The number of ROB reads -system.cpu.rob.rob_writes 11291 # The number of ROB writes -system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10769 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11838 # The number of ROB reads +system.cpu.rob.rob_writes 11181 # The number of ROB writes +system.cpu.timesIdled 163 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11381 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 7.590700 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.590700 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131740 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4685 # number of integer regfile reads -system.cpu.int_regfile_writes 2864 # number of integer regfile writes +system.cpu.cpi 7.834520 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.834520 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127640 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127640 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4649 # number of integer regfile reads +system.cpu.int_regfile_writes 2842 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.986102 # Cycle average of tags in use -system.cpu.icache.total_refs 813 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 90.926534 # Cycle average of tags in use +system.cpu.icache.total_refs 794 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.347594 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.245989 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 92.986102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045403 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045403 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 813 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 813 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 813 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 813 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 813 # number of overall hits -system.cpu.icache.overall_hits::total 813 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses -system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11955999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11955999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11955999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11955999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11955999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11955999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1063 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1063 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1063 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235183 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.235183 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.235183 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.235183 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.235183 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.235183 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47823.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47823.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47823.996000 # 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average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.425217 # Cycle average of tags in use -system.cpu.dcache.total_refs 774 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use +system.cpu.dcache.total_refs 763 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.976471 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.425217 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011090 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011090 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 44.507812 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.010866 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.010866 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 550 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 550 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits -system.cpu.dcache.overall_hits::total 774 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 763 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 763 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 763 # number of overall hits +system.cpu.dcache.overall_hits::total 763 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 192 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 192 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 192 # number of overall misses -system.cpu.dcache.overall_misses::total 192 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5152500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5152500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4115500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9268000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9268000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9268000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9268000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 672 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses +system.cpu.dcache.overall_misses::total 193 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5526500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5526500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4429500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4429500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9956000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9956000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9956000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9956000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 662 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 662 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 966 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 966 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 966 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 966 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165179 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.165179 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 956 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 956 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 956 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 956 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169184 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169184 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.198758 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.198758 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.198758 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.198758 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46418.918919 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46418.918919 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50808.641975 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 50808.641975 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48270.833333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48270.833333 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.201883 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.201883 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.201883 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.201883 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49343.750000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49343.750000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54685.185185 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54685.185185 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51585.492228 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51585.492228 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 107 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 107 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 107 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 108 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 108 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 108 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -770,30 +770,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3326500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3326500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4676000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4676000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4676000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4676000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090774 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090774 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3648500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3648500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1433500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1433500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5082000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5082000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092145 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092145 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087992 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54532.786885 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54532.786885 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56229.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56229.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.088912 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.088912 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59811.475410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59811.475410 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index cbe7a8e01..80cf199ee 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13354000 # Number of ticks simulated -final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 13709000 # Number of ticks simulated +final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22763 # Simulator instruction rate (inst/s) -host_op_rate 28403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66199618 # Simulator tick rate (ticks/s) -host_mem_usage 285296 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 51480 # Simulator instruction rate (inst/s) +host_op_rate 64222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153638426 # Simulator tick rate (ticks/s) +host_mem_usage 239936 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 25216 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13296500 # Total gap between requests +system.physmem.totGap 13651500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2460894 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests -system.physmem.totBusLat 1576000 # Total cycles spent in databus access -system.physmem.totBankLat 6524000 # Total cycles spent in bank access -system.physmem.avgQLat 6245.92 # Average queueing delay per request -system.physmem.avgBankLat 16558.38 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2508144 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totBusLat 1970000 # Total cycles spent in databus access +system.physmem.totBankLat 7273750 # Total cycles spent in bank access +system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.37 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.86 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 319 # Number of row buffer hits during reads +system.physmem.readRowHits 294 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33747.46 # Average gap between requests +system.physmem.avgGap 34648.48 # Average gap between requests system.cpu.branchPred.lookups 2501 # Number of BP lookups system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect @@ -282,50 +282,50 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 26709 # number of cpu cycles simulated +system.cpu.numCycles 27419 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2444 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2445 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2245 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename @@ -347,28 +347,28 @@ system.cpu.memDep0.conflictingLoads 37 # Nu system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -404,50 +404,50 @@ system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336516 # Inst issue rate +system.cpu.iq.FU_type_0::total 8986 # Type of FU issued +system.cpu.iq.rate 0.327729 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -475,42 +475,42 @@ system.cpu.iew.predictedTakenIncorrect 109 # Nu system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1443 # Number of branches executed +system.cpu.iew.exec_refs 3302 # number of memory reference insts executed +system.cpu.iew.exec_branches 1444 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.320604 # Inst execution rate -system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8105 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.312302 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8106 # cumulative count of insts written-back system.cpu.iew.wb_producers 3904 # num instructions producing a value system.cpu.iew.wb_consumers 7842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle +system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -523,117 +523,117 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22955 # The number of ROB reads +system.cpu.rob.rob_reads 23072 # The number of ROB reads system.cpu.rob.rob_writes 23605 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39368 # number of integer regfile reads -system.cpu.int_regfile_writes 8018 # number of integer regfile writes +system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39366 # number of integer regfile reads +system.cpu.int_regfile_writes 8019 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2982 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use -system.cpu.icache.total_refs 1597 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use +system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits -system.cpu.icache.overall_hits::total 1597 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits +system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -654,17 +654,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -687,17 +687,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -723,17 +723,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -745,109 +745,109 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use -system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use +system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits -system.cpu.dcache.overall_hits::total 2373 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits +system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -856,30 +856,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index a9f3432ad..13489057c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13354000 # Number of ticks simulated -final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 13709000 # Number of ticks simulated +final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20035 # Simulator instruction rate (inst/s) -host_op_rate 24999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58267208 # Simulator tick rate (ticks/s) -host_mem_usage 285296 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 58002 # Simulator instruction rate (inst/s) +host_op_rate 72354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 173086159 # Simulator tick rate (ticks/s) +host_mem_usage 238920 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 25216 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13296500 # Total gap between requests +system.physmem.totGap 13651500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2460894 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests -system.physmem.totBusLat 1576000 # Total cycles spent in databus access -system.physmem.totBankLat 6524000 # Total cycles spent in bank access -system.physmem.avgQLat 6245.92 # Average queueing delay per request -system.physmem.avgBankLat 16558.38 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2508144 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totBusLat 1970000 # Total cycles spent in databus access +system.physmem.totBankLat 7273750 # Total cycles spent in bank access +system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.37 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.86 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 319 # Number of row buffer hits during reads +system.physmem.readRowHits 294 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33747.46 # Average gap between requests +system.physmem.avgGap 34648.48 # Average gap between requests system.cpu.branchPred.lookups 2501 # Number of BP lookups system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect @@ -237,50 +237,50 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 26709 # number of cpu cycles simulated +system.cpu.numCycles 27419 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2444 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2445 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2245 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename @@ -302,28 +302,28 @@ system.cpu.memDep0.conflictingLoads 37 # Nu system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -359,50 +359,50 @@ system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336516 # Inst issue rate +system.cpu.iq.FU_type_0::total 8986 # Type of FU issued +system.cpu.iq.rate 0.327729 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -430,42 +430,42 @@ system.cpu.iew.predictedTakenIncorrect 109 # Nu system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1443 # Number of branches executed +system.cpu.iew.exec_refs 3302 # number of memory reference insts executed +system.cpu.iew.exec_branches 1444 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.320604 # Inst execution rate -system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8105 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.312302 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8106 # cumulative count of insts written-back system.cpu.iew.wb_producers 3904 # num instructions producing a value system.cpu.iew.wb_consumers 7842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle +system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -478,117 +478,117 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22955 # The number of ROB reads +system.cpu.rob.rob_reads 23072 # The number of ROB reads system.cpu.rob.rob_writes 23605 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39368 # number of integer regfile reads -system.cpu.int_regfile_writes 8018 # number of integer regfile writes +system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39366 # number of integer regfile reads +system.cpu.int_regfile_writes 8019 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2982 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use -system.cpu.icache.total_refs 1597 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use +system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits -system.cpu.icache.overall_hits::total 1597 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits +system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -609,17 +609,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -642,17 +642,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -678,17 +678,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -700,109 +700,109 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use -system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use +system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits -system.cpu.dcache.overall_hits::total 2373 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits +system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -811,30 +811,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 7f0e6e36f..4baa76c40 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18578000 # Number of ticks simulated -final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19339000 # Number of ticks simulated +final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49489 # Simulator instruction rate (inst/s) -host_op_rate 49481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158085302 # Simulator tick rate (ticks/s) -host_mem_usage 270352 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 100636 # Simulator instruction rate (inst/s) +host_op_rate 100592 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 334460805 # Simulator tick rate (ticks/s) +host_mem_usage 224316 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1092044354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 475401012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1567445365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1092044354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1092044354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1092044354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 475401012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1567445365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1049071824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 456693728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1505765551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049071824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049071824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049071824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 456693728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1505765551 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29120 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 89 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 37 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18503000 # Total gap between requests +system.physmem.totGap 19292000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2354454 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12658454 # Sum of mem lat for all requests -system.physmem.totBusLat 1820000 # Total cycles spent in databus access -system.physmem.totBankLat 8484000 # Total cycles spent in bank access -system.physmem.avgQLat 5174.62 # Average queueing delay per request -system.physmem.avgBankLat 18646.15 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27820.78 # Average memory access latency -system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2650454 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13959204 # Sum of mem lat for all requests +system.physmem.totBusLat 2275000 # Total cycles spent in databus access +system.physmem.totBankLat 9033750 # Total cycles spent in bank access +system.physmem.avgQLat 5825.17 # Average queueing delay per request +system.physmem.avgBankLat 19854.40 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30679.57 # Average memory access latency +system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.68 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 11.76 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.72 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 357 # Number of row buffer hits during reads +system.physmem.readRowHits 334 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40665.93 # Average gap between requests +system.physmem.avgGap 42400.00 # Average gap between requests system.cpu.branchPred.lookups 1154 # Number of BP lookups system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect @@ -213,7 +213,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 37157 # number of cpu cycles simulated +system.cpu.numCycles 38679 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True). @@ -235,12 +235,12 @@ system.cpu.execution_unit.executions 3135 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9462 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9463 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5375 # Number of cycles cpu stages are processed. -system.cpu.activity 14.465646 # Percentage of cycles cpu is active +system.cpu.idleCycles 33303 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5376 # Number of cycles cpu stages are processed. +system.cpu.activity 13.899015 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -252,36 +252,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.390953 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.652735 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.390953 # CPI: Total CPI of All Threads -system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.652735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150314 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33508 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.150314 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 35030 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.820491 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34341 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.434060 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35863 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.578653 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34392 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.280436 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 35914 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.441397 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.148582 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 37453 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 34255 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.169679 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35777 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.810103 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 149.849185 # Cycle average of tags in use +system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use system.cpu.icache.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.849185 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073169 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073169 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -294,12 +294,12 @@ system.cpu.icache.demand_misses::cpu.inst 346 # n system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses system.cpu.icache.overall_misses::total 346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18063500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18063500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18063500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18063500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18063500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18063500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18937500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18937500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18937500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 774 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses @@ -312,12 +312,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.447028 system.cpu.icache.demand_miss_rate::total 0.447028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.447028 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.447028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52206.647399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52206.647399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52206.647399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52206.647399 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54732.658960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54732.658960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -338,36 +338,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16468000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16468000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.412145 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.412145 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.412145 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51623.824451 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51623.824451 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 207.484772 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 206.866516 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.598539 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.886233 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004626 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 151.045976 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.820540 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -385,17 +385,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16122500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5062000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21184500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16122500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7626500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23749000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16122500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7626500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23749000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16983500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5162000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22145500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2560500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2560500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16983500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7722500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24706000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16983500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7722500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24706000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -418,17 +418,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50859.621451 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58183.908046 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52436.881188 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52195.604396 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52195.604396 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53575.709779 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54815.594059 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50205.882353 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50205.882353 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54298.901099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54298.901099 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,17 +448,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12118017 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982594 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16100611 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12118017 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5912166 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18030183 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12118017 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5912166 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18030183 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055529 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090608 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17146137 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925076 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925076 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015684 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19071213 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055529 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015684 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19071213 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -470,27 +470,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38227.182965 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45776.942529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39852.997525 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41184.634069 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47018.482759 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.933168 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37746.588235 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37746.588235 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.859083 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.859083 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021938 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021938 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.917113 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021952 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021952 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits @@ -507,14 +507,14 @@ system.cpu.dcache.demand_misses::cpu.data 444 # n system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses system.cpu.dcache.overall_misses::total 444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5589500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14659500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14659500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20249000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20249000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20249000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20249000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5626500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5626500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14767500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14767500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20394000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20394000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20394000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20394000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -531,14 +531,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60102.150538 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60102.150538 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41764.957265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41764.957265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45605.855856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45605.855856 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42072.649573 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42072.649573 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45932.432432 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45932.432432 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -563,14 +563,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7774000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7774000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7774000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7774000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5255500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5255500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7870000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7870000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -579,14 +579,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59258.620690 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59258.620690 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60408.045977 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60408.045977 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51264.705882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51264.705882 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 8a152a960..7feba62df 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16532500 # Number of ticks simulated -final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17026500 # Number of ticks simulated +final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36398 # Simulator instruction rate (inst/s) -host_op_rate 36393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116675957 # Simulator tick rate (ticks/s) -host_mem_usage 271376 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 76348 # Simulator instruction rate (inst/s) +host_op_rate 76319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 251939378 # Simulator tick rate (ticks/s) +host_mem_usage 226380 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 30464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1296839558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 545833963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1842673522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1296839558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1296839558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1296839558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 545833963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1842673522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::total 30592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 478 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1262972425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 533756204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1796728629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1262972425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1262972425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1262972425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 533756204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1796728629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 478 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 476 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30464 # Total number of bytes read from memory +system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30592 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30464 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 93 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 38 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16453500 # Total gap between requests +system.physmem.totGap 16967000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476 # Categorize read packet sizes +system.physmem.readPktSize::6 478 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2530972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13086972 # Sum of mem lat for all requests -system.physmem.totBusLat 1904000 # Total cycles spent in databus access -system.physmem.totBankLat 8652000 # Total cycles spent in bank access -system.physmem.avgQLat 5317.17 # Average queueing delay per request -system.physmem.avgBankLat 18176.47 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27493.64 # Average memory access latency -system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2863474 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14617224 # Sum of mem lat for all requests +system.physmem.totBusLat 2390000 # Total cycles spent in databus access +system.physmem.totBankLat 9363750 # Total cycles spent in bank access +system.physmem.avgQLat 5990.53 # Average queueing delay per request +system.physmem.avgBankLat 19589.44 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30579.97 # Average memory access latency +system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.52 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.86 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 376 # Number of row buffer hits during reads +system.physmem.readRowHits 351 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34566.18 # Average gap between requests -system.cpu.branchPred.lookups 2120 # Number of BP lookups -system.cpu.branchPred.condPredicted 1453 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups -system.cpu.branchPred.BTBHits 517 # Number of BTB hits +system.physmem.avgGap 35495.82 # Average gap between requests +system.cpu.branchPred.lookups 2222 # Number of BP lookups +system.cpu.branchPred.condPredicted 1502 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1693 # Number of BTB lookups +system.cpu.branchPred.BTBHits 508 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.314355 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.005907 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -213,235 +213,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 33066 # number of cpu cycles simulated +system.cpu.numCycles 34054 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8642 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13389 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3272 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1401 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1949 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14126 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.947827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.258648 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10748 77.06% 77.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1351 9.69% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 103 0.74% 87.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 137 0.98% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 291 2.09% 90.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 93 0.67% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 169 1.21% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 155 1.11% 93.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 900 6.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10854 76.84% 76.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1348 9.54% 86.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105 0.74% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 135 0.96% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.16% 90.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.84% 91.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 156 1.10% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 1.13% 93.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 945 6.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064114 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.390008 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8777 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1236 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3037 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 851 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 137 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 166 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 851 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8957 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 360 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 113 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11654 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 97 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7041 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13857 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13853 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 14126 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065249 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.393170 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8860 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1239 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3094 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 889 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12497 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 889 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 804 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2958 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 93 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7237 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14212 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14208 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3643 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 265 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1198 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3839 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2483 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1201 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9172 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8209 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3542 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.588585 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.249847 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8325 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3645 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2172 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.589339 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.255776 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10394 74.52% 74.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1403 10.06% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 889 6.37% 90.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 554 3.97% 94.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 357 2.56% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 219 1.57% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.63% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10546 74.66% 74.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1398 9.90% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 898 6.36% 90.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 564 3.99% 94.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 360 2.55% 97.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.60% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14126 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.73% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 100 62.11% 65.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 55 34.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 100 62.89% 66.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4835 58.90% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2260 27.53% 86.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1105 13.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4947 59.42% 59.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2263 27.18% 86.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1106 13.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8209 # Type of FU issued -system.cpu.iq.rate 0.248261 # Inst issue rate -system.cpu.iq.fu_busy_cnt 161 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019613 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30577 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8325 # Type of FU issued +system.cpu.iq.rate 0.244465 # Inst issue rate +system.cpu.iq.fu_busy_cnt 159 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019099 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30977 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12971 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7469 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8368 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8482 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1313 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 273 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 276 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 851 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 242 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10697 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1198 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 889 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10864 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2483 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1201 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 330 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 433 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7849 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2119 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 360 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 389 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1512 # number of nop insts executed -system.cpu.iew.exec_refs 3196 # number of memory reference insts executed -system.cpu.iew.exec_branches 1341 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.237374 # Inst execution rate -system.cpu.iew.wb_sent 7488 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2925 # num instructions producing a value -system.cpu.iew.wb_consumers 4228 # num instructions consuming a value +system.cpu.iew.exec_nop 1547 # number of nop insts executed +system.cpu.iew.exec_refs 3203 # number of memory reference insts executed +system.cpu.iew.exec_branches 1355 # Number of branches executed +system.cpu.iew.exec_stores 1078 # Number of stores executed +system.cpu.iew.exec_rate 0.233042 # Inst execution rate +system.cpu.iew.wb_sent 7560 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7471 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2950 # num instructions producing a value +system.cpu.iew.wb_consumers 4259 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.223916 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691816 # average fanout of values written-back +system.cpu.iew.wb_rate 0.219387 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692651 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4876 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5043 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 377 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13096 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.443876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.229358 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13237 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.439148 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.223024 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10722 81.87% 81.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 944 7.21% 89.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 654 4.99% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 320 2.44% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 142 1.08% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 103 0.79% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.50% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.31% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10853 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.12% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 96 0.73% 98.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 63 0.48% 98.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.31% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13096 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13237 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -452,69 +453,69 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23666 # The number of ROB reads -system.cpu.rob.rob_writes 22238 # The number of ROB writes -system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19119 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23973 # The number of ROB reads +system.cpu.rob.rob_writes 22610 # The number of ROB writes +system.cpu.timesIdled 288 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 6.413111 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.413111 # CPI: Total CPI of All Threads -system.cpu.ipc 0.155931 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.155931 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10670 # number of integer regfile reads -system.cpu.int_regfile_writes 5185 # number of integer regfile writes +system.cpu.cpi 6.604732 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10756 # number of integer regfile reads +system.cpu.int_regfile_writes 5239 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 147 # number of misc regfile reads +system.cpu.misc_regfile_reads 150 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 163.159030 # Cycle average of tags in use -system.cpu.icache.total_refs 1502 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 162.249914 # Cycle average of tags in use +system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 163.159030 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079667 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079667 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits -system.cpu.icache.overall_hits::total 1502 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 162.249914 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079224 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079224 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits +system.cpu.icache.overall_hits::total 1566 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses system.cpu.icache.overall_misses::total 447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21475500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21475500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21475500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21475500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21475500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21475500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1949 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1949 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1949 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1949 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229348 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229348 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229348 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229348 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229348 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229348 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48043.624161 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48043.624161 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48043.624161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48043.624161 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22381500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22381500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22381500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22381500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22381500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22381500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.222057 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.222057 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.222057 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.222057 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.222057 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.222057 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50070.469799 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50070.469799 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50070.469799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50070.469799 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -523,109 +524,109 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 6 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16956000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16956000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16956000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16956000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16956000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16956000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173422 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.173422 # 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number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 479 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 481 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 481 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991150 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51941.964286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60394.366197 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54452.928870 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,156 +635,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.877976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52792.164835 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.807963 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39844.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39844.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.877976 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8297499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8297499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8297499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8297499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8722499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8722499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8722499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8722499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61594.444444 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61594.444444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 2fa72cd37..ccc0289be 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14065500 # Number of ticks simulated -final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000015 # Number of seconds simulated +sim_ticks 14724500 # Number of ticks simulated +final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44313 # Simulator instruction rate (inst/s) -host_op_rate 44306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107578636 # Simulator tick rate (ticks/s) -host_mem_usage 267272 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 87376 # Simulator instruction rate (inst/s) +host_op_rate 87343 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 221965921 # Simulator tick rate (ticks/s) +host_mem_usage 222644 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1569798443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 459564182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2029362625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1569798443 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1569798443 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1569798443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 459564182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2029362625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1499541580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 438996231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1938537811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1499541580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1499541580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1499541580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 438996231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1938537811 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 28544 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 56 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 19 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13958000 # Total gap between requests +system.physmem.totGap 14617000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,34 +164,34 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1923944 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11085944 # Sum of mem lat for all requests -system.physmem.totBusLat 1784000 # Total cycles spent in databus access -system.physmem.totBankLat 7378000 # Total cycles spent in bank access -system.physmem.avgQLat 4313.78 # Average queueing delay per request -system.physmem.avgBankLat 16542.60 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24856.38 # Average memory access latency -system.physmem.avgRdBW 2029.36 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2286195 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12779945 # Sum of mem lat for all requests +system.physmem.totBusLat 2230000 # Total cycles spent in databus access +system.physmem.totBankLat 8263750 # Total cycles spent in bank access +system.physmem.avgQLat 5126.00 # Average queueing delay per request +system.physmem.avgBankLat 18528.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28654.59 # Average memory access latency +system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2029.36 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.68 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.14 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.87 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 369 # Number of row buffer hits during reads +system.physmem.readRowHits 338 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 31295.96 # Average gap between requests -system.cpu.branchPred.lookups 2247 # Number of BP lookups -system.cpu.branchPred.condPredicted 1810 # Number of conditional branches predicted +system.physmem.avgGap 32773.54 # Average gap between requests +system.cpu.branchPred.lookups 2226 # Number of BP lookups +system.cpu.branchPred.condPredicted 1794 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1863 # Number of BTB lookups -system.cpu.branchPred.BTBHits 602 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1842 # Number of BTB lookups +system.cpu.branchPred.BTBHits 599 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.313473 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 32.519001 # BTB Hit Percentage system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -213,234 +213,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 28132 # number of cpu cycles simulated +system.cpu.numCycles 29450 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1136 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11663 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.133328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.550093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7445 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2246 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1279 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.132231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547600 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9396 80.56% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 175 1.50% 82.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.51% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.22% 84.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.95% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.13% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.20% 90.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 109 0.93% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1049 8.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9302 80.55% 80.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 174 1.51% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.14% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.94% 91.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11663 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079873 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.469856 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7468 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1305 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2099 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 156 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11753 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 11548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2083 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 697 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7658 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 585 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 451 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1983 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 277 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11310 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7696 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1969 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 261 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11203 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 233 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18197 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18142 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 218 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9614 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18041 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17986 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4616 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 553 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1993 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10211 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8959 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4243 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8907 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 171 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.768156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.499073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.771302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8296 71.13% 71.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1090 9.35% 80.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 795 6.82% 87.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 496 4.25% 91.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 4.00% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 308 2.64% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 133 1.14% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 43 0.37% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8209 71.09% 71.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1071 9.27% 80.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 791 6.85% 87.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 496 4.30% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 4.04% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 302 2.62% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11663 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11548 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.60% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 71 40.80% 45.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 95 54.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 69 40.35% 45.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 94 54.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5501 61.40% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1805 20.15% 81.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1651 18.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5470 61.41% 61.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1795 20.15% 81.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1640 18.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8959 # Type of FU issued -system.cpu.iq.rate 0.318463 # Inst issue rate -system.cpu.iq.fu_busy_cnt 174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29881 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14574 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8164 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8907 # Type of FU issued +system.cpu.iq.rate 0.302445 # Inst issue rate +system.cpu.iq.fu_busy_cnt 171 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8122 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9099 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9044 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1032 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 783 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 757 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 370 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10360 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 697 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 276 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10268 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1829 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1993 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 264 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 330 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8539 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1683 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 420 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8492 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 415 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3224 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed -system.cpu.iew.exec_stores 1541 # Number of stores executed -system.cpu.iew.exec_rate 0.303533 # Inst execution rate -system.cpu.iew.wb_sent 8307 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8191 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4222 # num instructions producing a value -system.cpu.iew.wb_consumers 6683 # num instructions consuming a value +system.cpu.iew.exec_refs 3204 # number of memory reference insts executed +system.cpu.iew.exec_branches 1349 # Number of branches executed +system.cpu.iew.exec_stores 1531 # Number of stores executed +system.cpu.iew.exec_rate 0.288353 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8149 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4198 # num instructions producing a value +system.cpu.iew.wb_consumers 6619 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.291163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631752 # average fanout of values written-back +system.cpu.iew.wb_rate 0.276706 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.528757 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.330367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.533776 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.333108 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8576 78.29% 78.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1000 9.13% 87.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 620 5.66% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 265 2.42% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 172 1.57% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 106 0.97% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 68 0.62% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.41% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8471 78.07% 78.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 9.21% 87.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 109 1.00% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.62% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 43 0.40% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10851 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -451,118 +451,118 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21218 # The number of ROB reads -system.cpu.rob.rob_writes 21442 # The number of ROB writes -system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16469 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21024 # The number of ROB reads +system.cpu.rob.rob_writes 21246 # The number of ROB writes +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17902 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 4.857044 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.857044 # CPI: Total CPI of All Threads -system.cpu.ipc 0.205887 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.205887 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13537 # number of integer regfile reads -system.cpu.int_regfile_writes 7068 # number of integer regfile writes +system.cpu.cpi 5.084599 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.084599 # CPI: Total CPI of All Threads +system.cpu.ipc 0.196672 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.196672 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13466 # number of integer regfile reads +system.cpu.int_regfile_writes 7036 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 168.326770 # Cycle average of tags in use -system.cpu.icache.total_refs 1375 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 167.837630 # Cycle average of tags in use +system.cpu.icache.total_refs 1361 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.917379 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.877493 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 168.326770 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.082191 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.082191 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1375 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1375 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1375 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1375 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1375 # number of overall hits -system.cpu.icache.overall_hits::total 1375 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses -system.cpu.icache.overall_misses::total 438 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20259000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20259000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20259000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20259000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20259000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20259000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241589 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.241589 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.241589 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.241589 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.241589 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.241589 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.424658 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46253.424658 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46253.424658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46253.424658 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 167.837630 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.081952 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.081952 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1361 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1361 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1361 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1361 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1361 # number of overall hits +system.cpu.icache.overall_hits::total 1361 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses +system.cpu.icache.overall_misses::total 441 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21881500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21881500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21881500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21881500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21881500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21881500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1802 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1802 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1802 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1802 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244728 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.244728 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.244728 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.244728 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.244728 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.244728 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49617.913832 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49617.913832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49617.913832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49617.913832 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 52.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 87 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 87 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 87 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16770000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16770000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16770000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16770000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16770000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16770000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47777.777778 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47777.777778 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17781500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17781500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17781500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17781500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17781500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17781500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.194784 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.194784 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.194784 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50659.544160 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50659.544160 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 198.645596 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 198.145802 # Cycle average of tags in use system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 167.286173 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.359424 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005105 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 166.786148 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.359654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006062 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -583,17 +583,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16358500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2981000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19339500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2766000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2766000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16358500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5747000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22105500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16358500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5747000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22105500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17370000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20540500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2908000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2908000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17370000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6078500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23448500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17370000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6078500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23448500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -616,17 +616,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47415.942029 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55203.703704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48469.924812 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58851.063830 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58851.063830 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49563.901345 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49563.901345 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50347.826087 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58712.962963 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51479.949875 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61872.340426 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61872.340426 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52575.112108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52575.112108 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,17 +646,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12035515 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2315048 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14350563 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2187044 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2187044 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12035515 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4502092 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16537607 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12035515 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4502092 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16537607 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13081037 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509304 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590341 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332794 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332794 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13081037 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842098 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17923135 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13081037 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842098 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17923135 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -668,91 +668,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34885.550725 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42871.259259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35966.323308 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46532.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46532.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37916.049275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.592593 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39073.536341 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.407702 # Cycle average of tags in use -system.cpu.dcache.total_refs 2190 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use +system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.470588 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.382353 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.407702 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015480 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015480 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2190 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2190 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2190 # number of overall hits -system.cpu.dcache.overall_hits::total 2190 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 435 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.324462 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015460 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015460 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 709 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 709 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2181 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2181 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2181 # number of overall hits +system.cpu.dcache.overall_hits::total 2181 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 337 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 337 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses +system.cpu.dcache.overall_misses::total 438 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5160500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5160500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14813997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14813997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19974497 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19974497 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19974497 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19974497 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1573 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1573 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2625 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2625 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2625 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2625 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065864 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065864 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165714 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165714 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165714 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50211.538462 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50211.538462 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42685.791541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42685.791541 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44485.050575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44485.050575 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 414 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2619 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2619 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2619 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2619 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064209 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.064209 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.322180 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.322180 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.167239 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.167239 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.167239 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.167239 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51094.059406 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51094.059406 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43958.448071 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43958.448071 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45603.874429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45603.874429 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 419 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.800000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -761,30 +761,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2815499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2815499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5861999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5861999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5861999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5861999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2957499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2957499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6193499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6193499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034965 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034965 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55390.909091 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55390.909091 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59904.234043 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59904.234043 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038946 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58836.363636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58836.363636 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62925.510638 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62925.510638 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 0a19f6727..a586f3039 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16286500 # Number of ticks simulated -final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16783500 # Number of ticks simulated +final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32843 # Simulator instruction rate (inst/s) -host_op_rate 32839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100387600 # Simulator tick rate (ticks/s) -host_mem_usage 278524 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 84096 # Simulator instruction rate (inst/s) +host_op_rate 84062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 264753473 # Simulator tick rate (ticks/s) +host_mem_usage 230292 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1135664507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 526571086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1662235594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1135664507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1135664507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1135664507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 526571086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1662235594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1102034736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 510978044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1613012780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1102034736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1102034736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1102034736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 510978044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1613012780 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27072 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 5 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 11 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 71 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16235000 # Total gap between requests +system.physmem.totGap 16708000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2302422 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11302422 # Sum of mem lat for all requests -system.physmem.totBusLat 1692000 # Total cycles spent in databus access -system.physmem.totBankLat 7308000 # Total cycles spent in bank access -system.physmem.avgQLat 5443.08 # Average queueing delay per request -system.physmem.avgBankLat 17276.60 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26719.67 # Average memory access latency -system.physmem.avgRdBW 1662.24 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2673172 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12996922 # Sum of mem lat for all requests +system.physmem.totBusLat 2115000 # Total cycles spent in databus access +system.physmem.totBankLat 8208750 # Total cycles spent in bank access +system.physmem.avgQLat 6319.56 # Average queueing delay per request +system.physmem.avgBankLat 19406.03 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30725.58 # Average memory access latency +system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1662.24 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.39 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.69 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 12.60 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.77 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 336 # Number of row buffer hits during reads +system.physmem.readRowHits 300 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads +system.physmem.readRowHitRate 70.92 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 38380.61 # Average gap between requests +system.physmem.avgGap 39498.82 # Average gap between requests system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -195,14 +195,14 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 32574 # number of cpu cycles simulated +system.cpu.numCycles 33568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9600 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File @@ -217,12 +217,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9655 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26327 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6247 # Number of cycles cpu stages are processed. -system.cpu.activity 19.177872 # Percentage of cycles cpu is active +system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. +system.cpu.activity 18.604028 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -234,36 +234,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.114886 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.301483 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.114886 # CPI: Total CPI of All Threads -system.cpu.ipc 0.163535 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.301483 # CPI: Total CPI of All Threads +system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.163535 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27935 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 28929 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 14.241420 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 13.819709 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 30371 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.814576 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 29541 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 9.523951 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.311107 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 31599 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 32593 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.993185 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29417 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.904552 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30411 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use +system.cpu.icache.tagsinuse 141.185042 # Cycle average of tags in use system.cpu.icache.total_refs 895 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.423519 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070031 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070031 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 141.185042 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits @@ -276,12 +276,12 @@ system.cpu.icache.demand_misses::cpu.inst 362 # n system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18347500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18347500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18347500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18347500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18347500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18347500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18996500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18996500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18996500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18996500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18996500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18996500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses @@ -294,12 +294,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50683.701657 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50683.701657 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50683.701657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50683.701657 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52476.519337 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52476.519337 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52476.519337 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52476.519337 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,36 +320,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15423000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15423000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 170.006396 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 167.397199 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.886606 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 27.119790 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 140.660988 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.736211 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -370,17 +370,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4069000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4069000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6941500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6941500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21817000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15104500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3320000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15104500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8030000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15104500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8030000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -403,17 +403,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50234.567901 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50234.567901 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51576.832151 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51576.832151 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52264.705882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62641.509434 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,17 +433,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11236437 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13444009 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066068 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066068 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11236437 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5273640 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16510077 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11236437 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5273640 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16510077 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527456 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665331 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192787 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719824 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719824 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527456 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385155 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17912611 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527456 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385155 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17912611 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -455,27 +455,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38880.404844 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.967836 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37852.691358 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37852.691358 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39887.391003 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50289.264151 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41499.377193 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.753086 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 84.137936 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020541 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020541 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -492,14 +492,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3818500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3818500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25630500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25630500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25630500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25630500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -516,19 +516,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62598.360656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62598.360656 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54072.784810 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54072.784810 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.406250 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -548,14 +548,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8180000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8180000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8180000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8180000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -564,14 +564,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 44632e460..b6a3a3279 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15014000 # Number of ticks simulated -final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15468000 # Number of ticks simulated +final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24822 # Simulator instruction rate (inst/s) -host_op_rate 44962 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69258779 # Simulator tick rate (ticks/s) -host_mem_usage 286624 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 31666 # Simulator instruction rate (inst/s) +host_op_rate 57357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91020367 # Simulator tick rate (ticks/s) +host_mem_usage 241544 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory @@ -19,39 +19,39 @@ system.physmem.bytes_inst_read::total 19392 # Nu system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1291594512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 622352471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1913946983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1291594512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1291594512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1291594512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 622352471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1913946983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 1253685027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 604085855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1857770882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1253685027 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1253685027 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1253685027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 604085855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1857770882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 450 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 28736 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 14993500 # Total gap between requests +system.physmem.totGap 15452000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450 # Categorize read packet sizes +system.physmem.readPktSize::6 451 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,266 +164,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1656450 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12024450 # Sum of mem lat for all requests -system.physmem.totBusLat 1800000 # Total cycles spent in databus access -system.physmem.totBankLat 8568000 # Total cycles spent in bank access -system.physmem.avgQLat 3681.00 # Average queueing delay per request -system.physmem.avgBankLat 19040.00 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26721.00 # Average memory access latency -system.physmem.avgRdBW 1913.95 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 1899951 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13161201 # Sum of mem lat for all requests +system.physmem.totBusLat 2255000 # Total cycles spent in databus access +system.physmem.totBankLat 9006250 # Total cycles spent in bank access +system.physmem.avgQLat 4212.75 # Average queueing delay per request +system.physmem.avgBankLat 19969.51 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29182.26 # Average memory access latency +system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1913.95 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.96 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.80 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.51 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 352 # Number of row buffer hits during reads +system.physmem.readRowHits 333 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33318.89 # Average gap between requests -system.cpu.branchPred.lookups 3018 # Number of BP lookups -system.cpu.branchPred.condPredicted 3018 # Number of conditional branches predicted +system.physmem.avgGap 34261.64 # Average gap between requests +system.cpu.branchPred.lookups 2995 # Number of BP lookups +system.cpu.branchPred.condPredicted 2995 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2500 # Number of BTB lookups -system.cpu.branchPred.BTBHits 796 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2485 # Number of BTB lookups +system.cpu.branchPred.BTBHits 793 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.840000 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.911469 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 30029 # number of cpu cycles simulated +system.cpu.numCycles 30937 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 8904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14405 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2995 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3911 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2416 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3684 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1881 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 18552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.371173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.873073 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 171 0.92% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 265 1.43% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 14740 79.45% 79.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.02% 80.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 154 0.83% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 193 1.04% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 163 0.88% 83.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 168 0.91% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 265 1.43% 85.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 0.86% 86.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2520 13.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3547 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24452 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3325 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22970 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 18552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.096810 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.465624 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9434 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3628 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3523 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1823 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24308 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1823 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9778 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3309 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 767 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22819 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25107 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55203 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 55187 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 54742 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54726 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14046 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13835 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 31 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1757 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2054 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2204 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1750 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20458 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20351 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17350 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9975 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13877 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17307 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9863 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.933649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.794423 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 18552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.932891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.792260 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1385 7.45% 78.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1043 5.61% 84.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13164 70.96% 70.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1399 7.54% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1053 5.68% 84.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 693 3.74% 87.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 728 3.92% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 621 3.35% 95.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 594 3.20% 98.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 258 1.39% 99.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 18583 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 18552 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 138 77.53% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 134 76.57% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20 11.43% 88.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 12.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13964 80.48% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1899 10.95% 91.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1483 8.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13916 80.41% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1905 11.01% 91.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1482 8.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17350 # Type of FU issued -system.cpu.iq.rate 0.577775 # Inst issue rate -system.cpu.iq.fu_busy_cnt 178 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010259 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53666 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16004 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17307 # Type of FU issued +system.cpu.iq.rate 0.559427 # Inst issue rate +system.cpu.iq.fu_busy_cnt 175 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010112 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53542 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15949 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17520 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17474 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 158 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 160 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 815 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1823 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20493 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 20386 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1757 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2204 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1750 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16426 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 607 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16378 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 929 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3141 # number of memory reference insts executed -system.cpu.iew.exec_branches 1630 # Number of branches executed -system.cpu.iew.exec_stores 1364 # Number of stores executed -system.cpu.iew.exec_rate 0.547005 # Inst execution rate -system.cpu.iew.wb_sent 16198 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16008 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10179 # num instructions producing a value -system.cpu.iew.wb_consumers 15729 # num instructions consuming a value +system.cpu.iew.exec_refs 3145 # number of memory reference insts executed +system.cpu.iew.exec_branches 1625 # Number of branches executed +system.cpu.iew.exec_stores 1365 # Number of stores executed +system.cpu.iew.exec_rate 0.529398 # Inst execution rate +system.cpu.iew.wb_sent 16147 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15953 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10136 # num instructions producing a value +system.cpu.iew.wb_consumers 15661 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.533085 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.647149 # average fanout of values written-back +system.cpu.iew.wb_rate 0.515661 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.647213 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10746 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10639 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.581747 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.458276 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 16729 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.582581 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.458500 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13224 78.94% 78.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1319 7.87% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 595 3.55% 90.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13195 78.88% 78.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1327 7.93% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 594 3.55% 90.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 704 4.21% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 141 0.84% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 118 0.71% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16729 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -436,71 +436,71 @@ system.cpu.commit.int_insts 9652 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 37024 # The number of ROB reads -system.cpu.rob.rob_writes 42843 # The number of ROB writes -system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 36893 # The number of ROB reads +system.cpu.rob.rob_writes 42622 # The number of ROB writes +system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads -system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28877 # number of integer regfile reads -system.cpu.int_regfile_writes 17233 # number of integer regfile writes +system.cpu.cpi 5.750372 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.750372 # CPI: Total CPI of All Threads +system.cpu.ipc 0.173902 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.173902 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28821 # number of integer regfile reads +system.cpu.int_regfile_writes 17168 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7157 # number of misc regfile reads +system.cpu.misc_regfile_reads 7143 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.838495 # Cycle average of tags in use -system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.824422 # Cycle average of tags in use +system.cpu.icache.total_refs 1475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.851974 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 144.838495 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1482 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1482 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits -system.cpu.icache.overall_hits::total 1482 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 144.824422 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070715 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070715 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1475 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1475 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1475 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1475 # number of overall hits +system.cpu.icache.overall_hits::total 1475 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses system.cpu.icache.overall_misses::total 399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19371000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19371000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19371000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19371000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19371000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19371000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1881 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1881 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1881 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1881 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1881 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1881 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212121 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.212121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212121 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.212121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212121 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.212121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48548.872180 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48548.872180 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48548.872180 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48548.872180 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20611500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20611500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20611500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20611500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20611500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20611500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1874 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1874 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1874 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1874 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.212914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.212914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.212914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.212914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.212914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51657.894737 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51657.894737 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51657.894737 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51657.894737 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 312 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.571429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -516,36 +516,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 304 system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15461500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15461500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161616 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.161616 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.161616 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16157000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16157000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16157000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16157000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162220 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.162220 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.162220 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53148.026316 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53148.026316 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # 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average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51001.111111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51001.111111 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52283.828383 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54062.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52625.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52506.578947 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52506.578947 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52605.321508 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52605.321508 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -616,59 +616,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # 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number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 127 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 127 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses -system.cpu.dcache.overall_misses::total 202 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6336500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10557000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10557000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10557000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10557000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 203 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 203 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 203 # number of overall misses +system.cpu.dcache.overall_misses::total 203 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6648000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6648000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4218500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4218500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10866500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10866500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2487 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2487 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2487 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2487 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081830 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081830 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50289.682540 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50289.682540 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52262.376238 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52262.376238 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.081624 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081624 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081624 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081624 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52346.456693 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52346.456693 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55506.578947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55506.578947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53529.556650 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53529.556650 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.600000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -731,38 +731,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 55 system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 72 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7804000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7804000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3962500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4066500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4066500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8029000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8029000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8029000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8029000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046392 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046392 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52612.676056 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52612.676056 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059509 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059509 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55034.722222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55034.722222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53506.578947 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53506.578947 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 18c747e94..329680740 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19857000 # Number of ticks simulated -final_tick 19857000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 24473000 # Number of ticks simulated +final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38427 # Simulator instruction rate (inst/s) -host_op_rate 38425 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59863252 # Simulator tick rate (ticks/s) -host_mem_usage 271256 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 4068 # Simulator instruction rate (inst/s) +host_op_rate 4068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7811345 # Simulator tick rate (ticks/s) +host_mem_usage 226312 # Number of bytes of host memory used +host_seconds 3.13 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory +system.physmem.bytes_read::total 62080 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 972 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2004733847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1128065670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3132799517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2004733847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2004733847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2004733847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1128065670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3132799517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 972 # Total number of read requests seen +system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory +system.physmem.num_reads::total 970 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1626608916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 910064152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2536673068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1626608916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1626608916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1626608916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 910064152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2536673068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 970 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 972 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 62208 # Total number of bytes read from memory +system.physmem.cpureqs 970 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 62080 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62208 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 62080 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 122 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 76 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 66 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 88 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 91 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19816500 # Total gap between requests +system.physmem.totGap 24326500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 972 # Categorize read packet sizes +system.physmem.readPktSize::6 970 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 11651972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 34145972 # Sum of mem lat for all requests -system.physmem.totBusLat 3888000 # Total cycles spent in databus access -system.physmem.totBankLat 18606000 # Total cycles spent in bank access -system.physmem.avgQLat 11987.63 # Average queueing delay per request -system.physmem.avgBankLat 19141.98 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35129.60 # Average memory access latency -system.physmem.avgRdBW 3132.80 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 22646466 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 53470216 # Sum of mem lat for all requests +system.physmem.totBusLat 4850000 # Total cycles spent in databus access +system.physmem.totBankLat 25973750 # Total cycles spent in bank access +system.physmem.avgQLat 23346.87 # Average queueing delay per request +system.physmem.avgBankLat 26777.06 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 55123.93 # Average memory access latency +system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3132.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 19.58 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.72 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 19.82 # Data bus utilization in percentage +system.physmem.avgRdQLen 2.18 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 733 # Number of row buffer hits during reads +system.physmem.readRowHits 450 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 46.39 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 20387.35 # Average gap between requests -system.cpu.branchPred.lookups 6348 # Number of BP lookups -system.cpu.branchPred.condPredicted 3569 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1446 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 874 # Number of BTB hits +system.physmem.avgGap 25078.87 # Average gap between requests +system.cpu.branchPred.lookups 6101 # Number of BP lookups +system.cpu.branchPred.condPredicted 3457 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4432 # Number of BTB lookups +system.cpu.branchPred.BTBHits 1023 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.293598 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 898 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 23.082130 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 800 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 163 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4359 # DTB read hits -system.cpu.dtb.read_misses 96 # DTB read misses +system.cpu.dtb.read_hits 4461 # DTB read hits +system.cpu.dtb.read_misses 100 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4455 # DTB read accesses -system.cpu.dtb.write_hits 2014 # DTB write hits -system.cpu.dtb.write_misses 72 # DTB write misses +system.cpu.dtb.read_accesses 4561 # DTB read accesses +system.cpu.dtb.write_hits 2022 # DTB write hits +system.cpu.dtb.write_misses 83 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2086 # DTB write accesses -system.cpu.dtb.data_hits 6373 # DTB hits -system.cpu.dtb.data_misses 168 # DTB misses +system.cpu.dtb.write_accesses 2105 # DTB write accesses +system.cpu.dtb.data_hits 6483 # DTB hits +system.cpu.dtb.data_misses 183 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6541 # DTB accesses -system.cpu.itb.fetch_hits 5250 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 6666 # DTB accesses +system.cpu.itb.fetch_hits 4836 # ITB hits +system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5307 # ITB accesses +system.cpu.itb.fetch_accesses 4885 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -228,350 +228,351 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 39715 # number of cpu cycles simulated +system.cpu.numCycles 48947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1539 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 35371 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6348 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1772 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5994 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1779 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5250 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 858 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 26295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.345161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.748208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1376 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 33899 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6101 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1823 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5733 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1590 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 519 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4836 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 811 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.207659 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.639587 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20301 77.20% 77.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 545 2.07% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 388 1.48% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 414 1.57% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 431 1.64% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 401 1.53% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 440 1.67% 87.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 561 2.13% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2814 10.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22337 79.58% 79.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 523 1.86% 81.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 359 1.28% 82.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 389 1.39% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 440 1.57% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 399 1.42% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 440 1.57% 88.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 368 1.31% 89.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2815 10.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 26295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.159839 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.890621 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37128 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7028 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5161 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 465 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2623 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 533 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 326 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 31237 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 663 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2623 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3807 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1133 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4855 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2198 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 28851 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2210 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21669 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 35547 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35513 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.124645 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.692565 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38855 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9028 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4956 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 477 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2426 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 492 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 289 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 30419 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 546 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2426 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 39473 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6021 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4731 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2122 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 28264 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2059 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21243 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 34749 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 34715 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12529 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 51 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6010 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2907 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12103 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5573 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2924 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1330 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2775 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1297 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 2736 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1292 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25429 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 70 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21088 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11668 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7282 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 26295 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.801978 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.371425 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 20875 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11589 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7157 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.743677 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.323333 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17201 65.42% 65.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3228 12.28% 77.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2604 9.90% 87.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1566 5.96% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 907 3.45% 97.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 493 1.87% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 226 0.86% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.21% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18893 67.31% 67.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3427 12.21% 79.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2538 9.04% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1546 5.51% 94.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 945 3.37% 97.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 459 1.64% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 189 0.67% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 59 0.21% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 26295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 117 60.31% 65.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66 34.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.64% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 98 59.39% 63.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 61 36.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6973 65.93% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2492 23.56% 89.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1106 10.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6970 65.71% 65.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2525 23.81% 89.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1107 10.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10576 # Type of FU issued +system.cpu.iq.FU_type_0::total 10607 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7011 66.70% 66.71% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.72% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2403 22.86% 89.60% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1093 10.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6762 65.86% 65.87% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.88% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2394 23.32% 89.22% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1107 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10512 # Type of FU issued +system.cpu.iq.FU_type_1::total 10268 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13984 66.31% 66.33% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 66.34% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 66.34% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4895 23.21% 89.57% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2199 10.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 13732 65.78% 65.80% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 65.81% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4919 23.56% 89.39% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2214 10.61% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21088 # Type of FU issued -system.cpu.iq.rate 0.530983 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 100 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 194 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004458 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004742 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.009200 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 68733 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 37173 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18381 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads +system.cpu.iq.FU_type::total 20875 # Type of FU issued +system.cpu.iq.rate 0.426482 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 82 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 165 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.003976 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.003928 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.007904 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 70014 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 36770 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18228 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 41 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21256 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 21015 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 21 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1724 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1741 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 465 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 355 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 427 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1592 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.squashedLoads 1553 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 432 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedStores 427 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 238 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 302 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2623 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 887 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25678 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5682 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2660 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 70 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 31 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 235 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1060 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1295 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 19629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2279 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2190 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4469 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1459 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2850 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25356 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 534 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5660 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 905 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1123 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 19630 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2348 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2224 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4572 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1245 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 110 # number of nop insts executed -system.cpu.iew.exec_nop::1 69 # number of nop insts executed +system.cpu.iew.exec_nop::0 98 # number of nop insts executed +system.cpu.iew.exec_nop::1 81 # number of nop insts executed system.cpu.iew.exec_nop::total 179 # number of nop insts executed -system.cpu.iew.exec_refs::0 3341 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3226 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6567 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1545 # Number of branches executed -system.cpu.iew.exec_branches::1 1563 # Number of branches executed -system.cpu.iew.exec_branches::total 3108 # Number of branches executed -system.cpu.iew.exec_stores::0 1062 # Number of stores executed -system.cpu.iew.exec_stores::1 1036 # Number of stores executed -system.cpu.iew.exec_stores::total 2098 # Number of stores executed -system.cpu.iew.exec_rate 0.494247 # Inst execution rate -system.cpu.iew.wb_sent::0 9363 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9308 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18671 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9223 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9178 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18401 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4724 # num instructions producing a value -system.cpu.iew.wb_producers::1 4736 # num instructions producing a value -system.cpu.iew.wb_producers::total 9460 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6156 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6184 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12340 # num instructions consuming a value +system.cpu.iew.exec_refs::0 3414 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3275 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6689 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1527 # Number of branches executed +system.cpu.iew.exec_branches::1 1521 # Number of branches executed +system.cpu.iew.exec_branches::total 3048 # Number of branches executed +system.cpu.iew.exec_stores::0 1066 # Number of stores executed +system.cpu.iew.exec_stores::1 1051 # Number of stores executed +system.cpu.iew.exec_stores::total 2117 # Number of stores executed +system.cpu.iew.exec_rate 0.401046 # Inst execution rate +system.cpu.iew.wb_sent::0 9349 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9181 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 18530 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9210 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9038 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18248 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4725 # num instructions producing a value +system.cpu.iew.wb_producers::1 4632 # num instructions producing a value +system.cpu.iew.wb_producers::total 9357 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6193 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6064 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12257 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.232230 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.231097 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.463326 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.767381 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.765847 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.766613 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.188163 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.184649 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.372811 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.762958 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.763852 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.763401 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12926 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12589 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1134 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26218 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487413 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.275738 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 957 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28025 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.455986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.237353 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20568 78.45% 78.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2989 11.40% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1062 4.05% 93.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 514 1.96% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 342 1.30% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 238 0.91% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 201 0.77% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.27% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 232 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22265 79.45% 79.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3171 11.31% 90.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1034 3.69% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 483 1.72% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 332 1.18% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 227 0.81% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 200 0.71% 98.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 76 0.27% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 237 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26218 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 28025 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -602,191 +603,191 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 237 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 123093 # The number of ROB reads -system.cpu.rob.rob_writes 54044 # The number of ROB writes -system.cpu.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13420 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 126869 # The number of ROB reads +system.cpu.rob.rob_writes 53172 # The number of ROB writes +system.cpu.timesIdled 388 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20877 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6373 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 6.232737 # CPI: Cycles Per Instruction -system.cpu.cpi::1 6.231759 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.116124 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.160443 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.160468 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.320911 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 24691 # number of integer regfile reads -system.cpu.int_regfile_writes 13868 # number of integer regfile writes +system.cpu.cpi::0 7.681576 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.680370 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.840486 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.130182 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.130202 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.260384 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 24701 # number of integer regfile reads +system.cpu.int_regfile_writes 13755 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.icache.replacements::0 7 # number of replacements +system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 7 # number of replacements -system.cpu.icache.tagsinuse 306.891389 # Cycle average of tags in use -system.cpu.icache.total_refs 4214 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.742400 # Average number of references to valid blocks. +system.cpu.icache.replacements::total 6 # number of replacements +system.cpu.icache.tagsinuse 292.522712 # Cycle average of tags in use +system.cpu.icache.total_refs 3780 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.057692 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 306.891389 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.149849 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.149849 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4214 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4214 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4214 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4214 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4214 # number of overall hits -system.cpu.icache.overall_hits::total 4214 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1030 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1030 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1030 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1030 # number of overall misses -system.cpu.icache.overall_misses::total 1030 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56718997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56718997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56718997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56718997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56718997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56718997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5244 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5244 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5244 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5244 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196415 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196415 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196415 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196415 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196415 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196415 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.987379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55066.987379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55066.987379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55066.987379 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2360 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 292.522712 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.142833 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.142833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 3780 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3780 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3780 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3780 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3780 # number of overall hits +system.cpu.icache.overall_hits::total 3780 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses +system.cpu.icache.overall_misses::total 1049 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 78577996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 78577996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 78577996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 78577996 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.865291 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.986301 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.986301 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12271498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12271498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30538998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30538998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30538998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30538998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055556 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055556 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064853 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064853 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90433.168317 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90433.168317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84051.356164 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84051.356164 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 3353b4aad..3cd467a4b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22838500 # Number of ticks simulated -final_tick 22838500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 23146500 # Number of ticks simulated +final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 21741 # Simulator instruction rate (inst/s) -host_op_rate 21740 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32746771 # Simulator tick rate (ticks/s) -host_mem_usage 278448 # Number of bytes of host memory used -host_seconds 0.70 # Real time elapsed on the host +host_inst_rate 62448 # Simulator instruction rate (inst/s) +host_op_rate 62442 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95315643 # Simulator tick rate (ticks/s) +host_mem_usage 230224 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 835081113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 386715415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1221796528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 835081113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 835081113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 835081113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 386715415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1221796528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 823969067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 381569568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1205538634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 823969067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 823969067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 823969067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 381569568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1205538634 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27904 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 76 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 84 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 22805000 # Total gap between requests +system.physmem.totGap 23113000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,41 +164,41 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2325934 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11335934 # Sum of mem lat for all requests -system.physmem.totBusLat 1744000 # Total cycles spent in databus access -system.physmem.totBankLat 7266000 # Total cycles spent in bank access -system.physmem.avgQLat 5334.71 # Average queueing delay per request -system.physmem.avgBankLat 16665.14 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25999.85 # Average memory access latency -system.physmem.avgRdBW 1221.80 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2156686 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12064186 # Sum of mem lat for all requests +system.physmem.totBusLat 2180000 # Total cycles spent in databus access +system.physmem.totBankLat 7727500 # Total cycles spent in bank access +system.physmem.avgQLat 4946.53 # Average queueing delay per request +system.physmem.avgBankLat 17723.62 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27670.15 # Average memory access latency +system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1221.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.64 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.50 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.42 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.52 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 359 # Number of row buffer hits during reads +system.physmem.readRowHits 339 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52305.05 # Average gap between requests -system.cpu.branchPred.lookups 5147 # Number of BP lookups +system.physmem.avgGap 53011.47 # Average gap between requests +system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2720 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4100 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2719 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.325287 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 66.317073 # BTB Hit Percentage system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 45678 # number of cpu cycles simulated +system.cpu.numCycles 46294 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 2894 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File @@ -217,12 +217,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21903 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21905 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28109 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17569 # Number of cycles cpu stages are processed. -system.cpu.activity 38.462717 # Percentage of cycles cpu is active +system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28726 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. +system.cpu.activity 37.948762 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -234,36 +234,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.012663 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.053291 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.012663 # CPI: Total CPI of All Threads -system.cpu.ipc 0.331932 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.053291 # CPI: Total CPI of All Threads +system.cpu.ipc 0.327515 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.331932 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32252 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.327515 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32868 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 29.392705 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36324 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9354 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 20.478130 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36874 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8804 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 19.274049 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 42800 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 29.001598 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36941 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 20.203482 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 37491 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 19.015423 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 43416 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 6.300626 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36369 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 6.216788 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36985 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 20.379614 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 20.108437 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.574474 # Cycle average of tags in use +system.cpu.icache.tagsinuse 172.164652 # Cycle average of tags in use system.cpu.icache.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.574474 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084265 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084265 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 172.164652 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084065 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084065 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -276,12 +276,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18868500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18868500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18868500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18868500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18868500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18868500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18686000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18686000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18686000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18686000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18686000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -294,12 +294,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49523.622047 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49523.622047 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49523.622047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49523.622047 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49044.619423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49044.619423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49044.619423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49044.619423 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,36 +320,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15157500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15157500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15157500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15157500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15157500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15157500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14960000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14960000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50357.142857 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50357.142857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49700.996678 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49700.996678 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 204.083022 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 203.582900 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.933146 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.149876 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005247 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000981 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006228 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.517590 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.065310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -367,17 +367,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14874500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2846000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17720500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4426000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4426000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14874500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7272000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14874500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7272000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22146500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14678000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3230000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17908000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4625000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14678000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7855000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22533000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -400,17 +400,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49747.491639 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53698.113208 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50342.329545 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52070.588235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52070.588235 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49747.491639 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50678.489703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49747.491639 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50678.489703 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49090.301003 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60943.396226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50875 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54411.764706 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54411.764706 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51562.929062 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51562.929062 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -430,17 +430,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11105481 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13287049 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11105481 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16669113 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11105481 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16669113 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10987236 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575826 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13563062 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10987236 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158896 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17146132 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10987236 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158896 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17146132 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -452,27 +452,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37142.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37747.298295 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37142.076923 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38144.423341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37142.076923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38144.423341 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36746.608696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48600.490566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38531.426136 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.764706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.764706 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.519804 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.519804 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024297 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024297 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 99.212064 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024222 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024222 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -491,14 +491,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3301000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3301000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19263500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19263500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22564500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22564500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22564500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22564500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3686000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3686000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19969500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19969500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23655500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23655500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23655500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23655500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -517,19 +517,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56913.793103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56913.793103 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45648.104265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45648.104265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47009.375000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47009.375000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 680 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63551.724138 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63551.724138 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47321.090047 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47321.090047 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49282.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49282.291667 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 760 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.352941 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -549,14 +549,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4514000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4514000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7414500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7414500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7414500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7414500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3284500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3284500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7997500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7997500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7997500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7997500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -565,14 +565,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54726.415094 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54726.415094 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53105.882353 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53105.882353 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61971.698113 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61971.698113 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55447.058824 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55447.058824 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 368690106..cd86d7e47 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23180500 # Number of ticks simulated -final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 23775500 # Number of ticks simulated +final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20805 # Simulator instruction rate (inst/s) -host_op_rate 20805 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33406458 # Simulator tick rate (ticks/s) -host_mem_usage 278444 # Number of bytes of host memory used -host_seconds 0.69 # Real time elapsed on the host +host_inst_rate 69212 # Simulator instruction rate (inst/s) +host_op_rate 69204 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113962469 # Simulator tick rate (ticks/s) +host_mem_usage 232268 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 927676280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 405858372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1333534652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 927676280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 927676280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 927676280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 405858372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1333534652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 904460474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 395701457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1300161931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 904460474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 904460474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 904460474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 395701457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1300161931 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 483 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 30912 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 75 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 91 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23120500 # Total gap between requests +system.physmem.totGap 23715500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,121 +164,121 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3040483 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12980483 # Sum of mem lat for all requests -system.physmem.totBusLat 1932000 # Total cycles spent in databus access -system.physmem.totBankLat 8008000 # Total cycles spent in bank access -system.physmem.avgQLat 6295.00 # Average queueing delay per request -system.physmem.avgBankLat 16579.71 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26874.71 # Average memory access latency -system.physmem.avgRdBW 1333.53 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 4632480 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15613730 # Sum of mem lat for all requests +system.physmem.totBusLat 2415000 # Total cycles spent in databus access +system.physmem.totBankLat 8566250 # Total cycles spent in bank access +system.physmem.avgQLat 9591.06 # Average queueing delay per request +system.physmem.avgBankLat 17735.51 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32326.56 # Average memory access latency +system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1333.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 8.33 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.56 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 10.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.66 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 394 # Number of row buffer hits during reads +system.physmem.readRowHits 369 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47868.53 # Average gap between requests -system.cpu.branchPred.lookups 6759 # Number of BP lookups -system.cpu.branchPred.condPredicted 4517 # Number of conditional branches predicted +system.physmem.avgGap 49100.41 # Average gap between requests +system.cpu.branchPred.lookups 6770 # Number of BP lookups +system.cpu.branchPred.condPredicted 4525 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4658 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2448 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4668 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2447 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.554745 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 52.420737 # BTB Hit Percentage system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 46362 # number of cpu cycles simulated +system.cpu.numCycles 47552 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9181 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3076 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8341 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12219 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8389 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5338 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.965953 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.157796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23362 71.79% 71.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4525 13.90% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 464 1.43% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 371 1.14% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1897 5.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23567 71.95% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4524 13.81% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 464 1.42% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 371 1.13% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 671 2.05% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 764 2.33% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 234 0.71% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 254 0.78% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1904 5.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.145787 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.678034 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9216 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8405 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1906 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29374 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1906 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8008 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12949 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9302 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8402 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13599 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8397 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8002 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 128 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24166 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49969 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 49969 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 138 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24189 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49982 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 49982 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10370 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2331 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2748 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3537 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2327 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22748 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22737 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21285 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8188 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21278 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5645 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32543 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.654058 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.275967 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.649650 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.272846 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23299 71.59% 71.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3475 10.68% 82.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 922 2.83% 97.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23497 71.74% 71.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3507 10.71% 82.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2330 7.11% 89.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1726 5.27% 94.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 921 2.81% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 469 1.43% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 236 0.72% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 48 0.15% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32543 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32753 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available @@ -314,69 +314,69 @@ system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15766 74.07% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3371 15.84% 89.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2148 10.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15764 74.09% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3369 15.83% 89.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2145 10.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21285 # Type of FU issued -system.cpu.iq.rate 0.459104 # Inst issue rate +system.cpu.iq.FU_type_0::total 21278 # Type of FU issued +system.cpu.iq.rate 0.447468 # Inst issue rate system.cpu.iq.fu_busy_cnt 153 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007188 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75371 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31612 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.007191 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75569 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31584 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21438 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21431 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 883 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 879 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1906 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1907 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24537 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 24523 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2331 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 3537 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2327 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -384,43 +384,43 @@ system.cpu.iew.memOrderViolationEvents 26 # Nu system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20207 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3221 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1078 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 20204 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3219 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1139 # number of nop insts executed -system.cpu.iew.exec_refs 5276 # number of memory reference insts executed -system.cpu.iew.exec_branches 4247 # Number of branches executed -system.cpu.iew.exec_stores 2055 # Number of stores executed -system.cpu.iew.exec_rate 0.435853 # Inst execution rate -system.cpu.iew.wb_sent 19873 # cumulative count of insts sent to commit +system.cpu.iew.exec_nop 1136 # number of nop insts executed +system.cpu.iew.exec_refs 5272 # number of memory reference insts executed +system.cpu.iew.exec_branches 4246 # Number of branches executed +system.cpu.iew.exec_stores 2053 # Number of stores executed +system.cpu.iew.exec_rate 0.424882 # Inst execution rate +system.cpu.iew.wb_sent 19870 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19647 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9210 # num instructions producing a value -system.cpu.iew.wb_consumers 11373 # num instructions consuming a value +system.cpu.iew.wb_producers 9208 # num instructions producing a value +system.cpu.iew.wb_consumers 11364 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.423774 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back +system.cpu.iew.wb_rate 0.413169 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.810278 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9300 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30637 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.494892 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.191683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 30846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.491539 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.188551 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23339 76.18% 76.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1377 4.49% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 324 1.06% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 65 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23538 76.31% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4051 13.13% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1362 4.42% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 765 2.48% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 357 1.16% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 268 0.87% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 325 1.05% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.21% 99.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30846 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -433,66 +433,66 @@ system.cpu.commit.int_insts 12174 # Nu system.cpu.commit.function_calls 187 # Number of function calls committed. system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54162 # The number of ROB reads -system.cpu.rob.rob_writes 50836 # The number of ROB writes +system.cpu.rob.rob_reads 54359 # The number of ROB reads +system.cpu.rob.rob_writes 50813 # The number of ROB writes system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13819 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14799 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.211554 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.211554 # CPI: Total CPI of All Threads -system.cpu.ipc 0.311376 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.311376 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32290 # number of integer regfile reads +system.cpu.cpi 3.293987 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.293987 # CPI: Total CPI of All Threads +system.cpu.ipc 0.303583 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.303583 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32289 # number of integer regfile reads system.cpu.int_regfile_writes 17967 # number of integer regfile writes -system.cpu.misc_regfile_reads 6967 # number of misc regfile reads +system.cpu.misc_regfile_reads 6962 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 191.466325 # Cycle average of tags in use -system.cpu.icache.total_refs 4845 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 190.534927 # Cycle average of tags in use +system.cpu.icache.total_refs 4850 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.349112 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 191.466325 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.093489 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.093489 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4845 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4845 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4845 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4845 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4845 # number of overall hits -system.cpu.icache.overall_hits::total 4845 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 493 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 493 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 493 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 493 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 493 # number of overall misses -system.cpu.icache.overall_misses::total 493 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23383000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23383000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23383000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23383000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23383000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23383000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5338 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5338 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5338 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5338 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092357 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092357 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092357 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092357 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092357 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092357 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47430.020284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47430.020284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47430.020284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47430.020284 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 190.534927 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.093035 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.093035 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4850 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4850 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4850 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4850 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4850 # number of overall hits +system.cpu.icache.overall_hits::total 4850 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 491 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 491 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 491 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 491 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 491 # number of overall misses +system.cpu.icache.overall_misses::total 491 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24328000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24328000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24328000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24328000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24328000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24328000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5341 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5341 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5341 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5341 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091930 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091930 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091930 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091930 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091930 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091930 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49547.861507 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49547.861507 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49547.861507 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49547.861507 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,48 +501,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 155 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 155 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 155 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 155 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 155 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 153 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 153 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 153 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 153 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17113500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17113500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17113500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17113500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17113500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17113500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063320 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.063320 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.063320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50631.656805 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50631.656805 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17616000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17616000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17616000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17616000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17616000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17616000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063284 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.063284 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.063284 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52118.343195 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52118.343195 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 225.767373 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.642209 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 190.872097 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.895277 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005825 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001065 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006890 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 189.932225 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.709984 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_misses::total 483 # nu system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 483 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20527500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4421500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4421500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16755500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8193500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24949000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16755500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8193500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24949000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17258000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4829500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22087500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5160500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5160500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17258000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9990000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27248000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17258000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9990000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27248000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) @@ -593,17 +593,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995876 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49867.559524 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58937.500000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51318.750000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53271.084337 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53271.084337 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51654.244306 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51654.244306 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51363.095238 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75460.937500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 55218.750000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 62174.698795 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 62174.698795 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56414.078675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56414.078675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,17 +623,17 @@ system.cpu.l2cache.demand_mshr_misses::total 483 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 483 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18906136 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099526 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042315 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141841 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145826 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145826 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099526 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188141 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21287667 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099526 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21287667 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -645,95 +645,95 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37288.726190 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38772.685000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40928.457831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40928.457831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38986.684524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63161.171875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42854.602500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.943036 # Cycle average of tags in use -system.cpu.dcache.total_refs 4019 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use +system.cpu.dcache.total_refs 4017 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.340136 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.326531 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.943036 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024400 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024400 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 2980 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2980 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 99.563734 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024308 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024308 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2978 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2978 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4013 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4013 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4013 # number of overall hits -system.cpu.dcache.overall_hits::total 4013 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4011 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4011 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4011 # number of overall hits +system.cpu.dcache.overall_hits::total 4011 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses -system.cpu.dcache.overall_misses::total 539 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6943000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6943000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19544474 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19544474 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26487474 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26487474 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26487474 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26487474 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3110 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 540 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 540 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 540 # number of overall misses +system.cpu.dcache.overall_misses::total 540 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8999000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8999000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21053474 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21053474 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30052474 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30052474 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30052474 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30052474 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3109 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3109 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4552 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4552 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4552 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4552 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041801 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.041801 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042136 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042136 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118409 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118409 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118409 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118409 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53407.692308 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53407.692308 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47786 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47786 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49141.881262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49141.881262 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.118655 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118655 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118655 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118655 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68694.656489 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68694.656489 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51475.486553 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51475.486553 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55652.729630 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55652.729630 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 429 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.321429 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 393 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 393 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 393 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -742,30 +742,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8342000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8342000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8342000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8342000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020579 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10138500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10138500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10138500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10138500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020585 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020585 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032293 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032293 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54283.132530 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54283.132530 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032301 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032301 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76468.750000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76468.750000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63186.746988 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63186.746988 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3f4fe5ffb..3dd8cecd5 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,87 +1,87 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 104832500 # Number of ticks simulated -final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000106 # Number of seconds simulated +sim_ticks 105801500 # Number of ticks simulated +final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81452 # Simulator instruction rate (inst/s) -host_op_rate 81452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8250764 # Simulator tick rate (ticks/s) -host_mem_usage 293492 # Number of bytes of host memory used -host_seconds 12.71 # Real time elapsed on the host -sim_insts 1034907 # Number of instructions simulated -sim_ops 1034907 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory +host_inst_rate 99938 # Simulator instruction rate (inst/s) +host_op_rate 99937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10207562 # Simulator tick rate (ticks/s) +host_mem_usage 247464 # Number of bytes of host memory used +host_seconds 10.37 # Real time elapsed on the host +sim_insts 1035849 # Number of instructions simulated +sim_ops 1035849 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28416 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 81 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 658 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 217337181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 102563613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49450314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 12209954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1831493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7936470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2441991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7936470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 401707486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 217337181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49450314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1831493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2441991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271060978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 217337181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 102563613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49450314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 12209954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1831493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7936470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2441991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7936470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401707486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 659 # Total number of read requests seen +system.physmem.num_reads::total 660 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 215951570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101624268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 48392509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 12098127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 3629438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7863783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1814719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7863783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 399238196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 215951570 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 48392509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 3629438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1814719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269788236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 215951570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101624268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 48392509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 661 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 42112 # Total number of bytes read from memory +system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 42240 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42112 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 72 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 78 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 44 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -100,14 +100,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 104804500 # Total gap between requests +system.physmem.totGap 105773500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 659 # Categorize read packet sizes +system.physmem.readPktSize::6 661 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,14 +125,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 72 # categorize neither packet sizes +system.physmem.neitherpktsize::6 71 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -194,336 +194,336 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2976655 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17750655 # Sum of mem lat for all requests -system.physmem.totBusLat 2636000 # Total cycles spent in databus access -system.physmem.totBankLat 12138000 # Total cycles spent in bank access -system.physmem.avgQLat 4516.93 # Average queueing delay per request -system.physmem.avgBankLat 18418.82 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26935.74 # Average memory access latency -system.physmem.avgRdBW 401.71 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 4077160 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20692160 # Sum of mem lat for all requests +system.physmem.totBusLat 3305000 # Total cycles spent in databus access +system.physmem.totBankLat 13310000 # Total cycles spent in bank access +system.physmem.avgQLat 6168.17 # Average queueing delay per request +system.physmem.avgBankLat 20136.16 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 31304.33 # Average memory access latency +system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 401.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.51 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 506 # Number of row buffer hits during reads +system.physmem.readRowHits 465 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads +system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 159035.66 # Average gap between requests -system.cpu0.branchPred.lookups 82004 # Number of BP lookups -system.cpu0.branchPred.condPredicted 79765 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 79291 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 77227 # Number of BTB hits +system.physmem.avgGap 160020.42 # Average gap between requests +system.cpu0.branchPred.lookups 82232 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80005 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 79512 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 77444 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.396930 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 516 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 97.399135 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 209666 # number of cpu cycles simulated +system.cpu0.numCycles 211604 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12561 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 16980 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 488068 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82232 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77969 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 160105 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3869 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13032 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 483 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 192912 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.522928 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215898 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1378 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5906 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 485 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 193984 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.516022 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216359 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33275 17.25% 17.25% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79042 40.97% 58.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 987 0.51% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 75108 38.93% 98.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 578 0.30% 98.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33879 17.46% 17.46% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79263 40.86% 58.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 997 0.51% 59.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 75310 38.82% 98.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 571 0.29% 98.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 376 0.19% 98.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2516 1.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 192912 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391117 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.321325 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14019 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 483730 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12784 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 193984 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.388613 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.306516 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17628 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14487 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 159104 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2484 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 484973 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2484 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18279 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 710 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13181 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 158767 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 563 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 482144 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 329027 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 958899 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 958899 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 315995 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 399553 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10756 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9264 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 192912 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.071167 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.088883 # Number of insts issued each cycle +system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 329947 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 961518 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 961518 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 316491 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13456 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 888 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3585 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 154112 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 77863 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75108 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 74923 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 403093 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 921 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 400275 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11012 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9891 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 362 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 193984 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.063443 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.093968 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 32280 16.73% 16.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4842 2.51% 19.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 76824 39.82% 59.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76328 39.57% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1590 0.82% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 686 0.36% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33040 17.03% 17.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4899 2.53% 19.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 76941 39.66% 59.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76443 39.41% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1604 0.83% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 703 0.36% 99.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 261 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 76 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 192912 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 193984 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 53 23.66% 49.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 114 50.89% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 51 22.67% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 62 27.56% 50.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 49.78% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 169105 42.32% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 153315 38.37% 80.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77133 19.30% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 169361 42.31% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 153636 38.38% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77278 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 399553 # Type of FU issued -system.cpu0.iq.rate 1.905664 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 992374 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 413873 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 397773 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 400275 # Type of FU issued +system.cpu0.iq.rate 1.891623 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000562 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 994851 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 415081 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 398443 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 399777 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 400500 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 74634 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2133 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1389 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2277 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2438 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 389 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 478542 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 300 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 153720 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 77689 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2484 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 441 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 479665 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 154112 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 77863 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 809 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 398478 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 152978 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1075 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 399178 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 153293 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 75469 # number of nop insts executed -system.cpu0.iew.exec_refs 230010 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79152 # Number of branches executed -system.cpu0.iew.exec_stores 77032 # Number of stores executed -system.cpu0.iew.exec_rate 1.900537 # Inst execution rate -system.cpu0.iew.wb_sent 398087 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 397773 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 235728 # num instructions producing a value -system.cpu0.iew.wb_consumers 238247 # num instructions consuming a value +system.cpu0.iew.exec_nop 75651 # number of nop insts executed +system.cpu0.iew.exec_refs 230462 # number of memory reference insts executed +system.cpu0.iew.exec_branches 79264 # Number of branches executed +system.cpu0.iew.exec_stores 77169 # Number of stores executed +system.cpu0.iew.exec_rate 1.886439 # Inst execution rate +system.cpu0.iew.wb_sent 398782 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 398443 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 236156 # num instructions producing a value +system.cpu0.iew.wb_consumers 238721 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.897175 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.882965 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989255 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12542 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 190474 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.448334 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.135304 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 191500 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.439102 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136121 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32805 17.22% 17.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2339 1.23% 59.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 74329 39.02% 99.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33551 17.52% 17.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 78896 41.20% 58.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2340 1.22% 59.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 696 0.36% 60.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 545 0.28% 60.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 74448 38.88% 99.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 466 0.24% 99.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 256 0.13% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 190474 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 466344 # Number of instructions committed -system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 191500 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 467088 # Number of instructions committed +system.cpu0.commit.committedOps 467088 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 227887 # Number of memory references committed -system.cpu0.commit.loads 151587 # Number of loads committed +system.cpu0.commit.refs 228259 # Number of memory references committed +system.cpu0.commit.loads 151835 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 78187 # Number of branches committed +system.cpu0.commit.branches 78311 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 314326 # Number of committed integer instructions. +system.cpu0.commit.int_insts 314822 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 667504 # The number of ROB reads -system.cpu0.rob.rob_writes 959472 # The number of ROB writes -system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 16754 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 391341 # Number of Instructions Simulated -system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated -system.cpu0.cpi 0.535763 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535763 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.866497 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.866497 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 712766 # number of integer regfile reads -system.cpu0.int_regfile_writes 321389 # number of integer regfile writes +system.cpu0.rob.rob_reads 669667 # The number of ROB reads +system.cpu0.rob.rob_writes 961765 # The number of ROB writes +system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 17620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 391961 # Number of Instructions Simulated +system.cpu0.committedOps 391961 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 391961 # Number of Instructions Simulated +system.cpu0.cpi 0.539860 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.539860 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.852333 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.852333 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 714059 # number of integer regfile reads +system.cpu0.int_regfile_writes 321926 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 231850 # number of misc regfile reads +system.cpu0.misc_regfile_reads 232286 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 297 # number of replacements -system.cpu0.icache.tagsinuse 245.463196 # Cycle average of tags in use -system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks. +system.cpu0.icache.replacements 298 # number of replacements +system.cpu0.icache.tagsinuse 245.557795 # Cycle average of tags in use +system.cpu0.icache.total_refs 5162 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.764007 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 245.463196 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.479420 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.479420 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5129 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5129 # number of overall hits -system.cpu0.icache.overall_hits::total 5129 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 742 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 742 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 742 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses -system.cpu0.icache.overall_misses::total 742 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25596000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 25596000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 25596000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 25596000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 25596000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 25596000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5871 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5871 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5871 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126384 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.126384 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126384 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34495.956873 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 34495.956873 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 34495.956873 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 34495.956873 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 245.557795 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.479605 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.479605 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5162 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5162 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5162 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5162 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5162 # number of overall hits +system.cpu0.icache.overall_hits::total 5162 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses +system.cpu0.icache.overall_misses::total 744 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26547500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 26547500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 26547500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 26547500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 26547500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 26547500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5906 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5906 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5906 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5906 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5906 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5906 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125974 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125974 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125974 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125974 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125974 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125974 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35682.123656 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 35682.123656 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 35682.123656 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 35682.123656 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,468 +538,469 @@ system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20466000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20466000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20466000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20466000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20466000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20466000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34806.122449 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21154500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21154500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21154500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21154500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21154500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21154500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099898 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.099898 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.099898 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35855.084746 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 143.865824 # Cycle average of tags in use -system.cpu0.dcache.total_refs 153562 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 143.429999 # Cycle average of tags in use +system.cpu0.dcache.total_refs 153854 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 903.305882 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 905.023529 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 143.865824 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.280988 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.280988 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 77931 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77931 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75708 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75708 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153639 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153639 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153639 # number of overall hits -system.cpu0.dcache.overall_hits::total 153639 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 550 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1021 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1021 # number of overall misses -system.cpu0.dcache.overall_misses::total 1021 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23032998 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 23032998 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34118498 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34118498 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34118498 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34118498 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78402 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78402 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 143.429999 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.280137 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.280137 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 78105 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78105 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75839 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75839 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 153944 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153944 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153944 # number of overall hits +system.cpu0.dcache.overall_hits::total 153944 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses +system.cpu0.dcache.overall_misses::total 1018 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11909000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11909000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24675495 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24675495 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 605500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 605500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 36584495 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 36584495 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 36584495 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 36584495 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78580 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78580 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76382 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76382 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154660 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154660 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154660 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154660 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006007 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006007 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006602 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006602 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006602 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41878.178182 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41878.178182 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33416.746327 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33416.746327 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 154962 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 154962 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154962 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154962 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006045 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007109 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007109 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006569 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006569 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006569 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006569 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25071.578947 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25071.578947 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45442.900552 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45442.900552 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28833.333333 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 28833.333333 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35937.617878 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35937.617878 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 384 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 384 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 661 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 661 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 661 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 661 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 194 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 194 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5613000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5613000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10507000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10507000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10507000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10507000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002474 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002474 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002328 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33813.253012 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33813.253012 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 660 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5409500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5409500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5718500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5718500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 563500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 563500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11128000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11128000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11128000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11128000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002392 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002310 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002310 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28773.936170 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28773.936170 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33638.235294 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33638.235294 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52905 # Number of BP lookups -system.cpu1.branchPred.condPredicted 50239 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1268 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46829 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 46139 # Number of BTB hits +system.cpu1.branchPred.lookups 58098 # Number of BP lookups +system.cpu1.branchPred.condPredicted 55415 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 51986 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 51313 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.526554 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.705421 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 648 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 174086 # number of cpu cycles simulated +system.cpu1.numCycles 174790 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46798 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 103837 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 29303 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6120 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 169684 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.752693 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.165174 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 24349 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 331605 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 58098 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 51961 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 112635 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 23829 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 15584 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 170350 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.946610 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.217345 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65847 38.81% 38.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52567 30.98% 69.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 36567 21.55% 96.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 57715 33.88% 33.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 56197 32.99% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4087 2.40% 69.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3199 1.88% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 641 0.38% 71.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43239 25.38% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1271 0.75% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 756 0.44% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 169684 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.303902 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.708374 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 26238 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 98390 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 293931 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11856 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 94084 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 291897 # Number of instructions processed by rename -system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 205023 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 562534 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 562534 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 192188 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 83198 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 39823 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 39558 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 34786 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 242793 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 244436 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10755 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10381 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 169684 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.440537 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 170350 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.332387 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.897162 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27574 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 22245 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 108585 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3208 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2341 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 328108 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2341 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28283 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 9804 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11660 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 105676 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 6189 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 325946 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 230320 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 636644 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 636644 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 217343 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1083 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1203 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8803 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 95013 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 46485 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 44692 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41453 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 273191 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 4270 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 273407 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10726 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 170350 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.604972 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.301874 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 63215 37.25% 37.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 39931 23.53% 73.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 40651 23.96% 97.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54964 32.27% 32.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16569 9.73% 41.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46599 27.35% 69.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 47325 27.78% 97.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3328 1.95% 99.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1208 0.71% 99.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 245 0.14% 99.93% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 169684 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 170350 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 68 23.05% 28.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 5.69% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 72 24.08% 29.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 118250 48.38% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 87046 35.61% 83.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 39140 16.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 130168 47.61% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 97443 35.64% 83.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 45796 16.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 244436 # Type of FU issued -system.cpu1.iq.rate 1.404111 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 658939 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 259411 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 242683 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 273407 # Type of FU issued +system.cpu1.iq.rate 1.564203 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 299 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001094 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 717543 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 288232 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 271609 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 244731 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 273706 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 34550 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 41212 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2369 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1440 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 289064 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 83198 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 39823 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2341 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1392 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 323061 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 95013 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 46485 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1042 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 243277 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 82228 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1159 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 928 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1384 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 272209 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 94088 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1198 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 40453 # number of nop insts executed -system.cpu1.iew.exec_refs 121292 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49718 # Number of branches executed -system.cpu1.iew.exec_stores 39064 # Number of stores executed -system.cpu1.iew.exec_rate 1.397453 # Inst execution rate -system.cpu1.iew.wb_sent 242950 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 242683 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 138076 # num instructions producing a value -system.cpu1.iew.wb_consumers 142766 # num instructions consuming a value +system.cpu1.iew.exec_nop 45600 # number of nop insts executed +system.cpu1.iew.exec_refs 139806 # number of memory reference insts executed +system.cpu1.iew.exec_branches 54914 # Number of branches executed +system.cpu1.iew.exec_stores 45718 # Number of stores executed +system.cpu1.iew.exec_rate 1.557349 # Inst execution rate +system.cpu1.iew.wb_sent 271881 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 271609 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 156621 # num instructions producing a value +system.cpu1.iew.wb_consumers 161297 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.394041 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.967149 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.553916 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.971010 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161216 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.716349 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.045856 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12317 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 3766 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 161612 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.922772 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.097017 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 62245 38.61% 38.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47765 29.63% 68.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 35063 21.75% 98.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 52280 32.35% 32.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 52948 32.76% 65.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6058 3.75% 68.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 4700 2.91% 71.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41692 25.80% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 528 0.33% 98.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1013 0.63% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161216 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 276703 # Number of instructions committed -system.cpu1.commit.committedOps 276703 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161612 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 310743 # Number of instructions committed +system.cpu1.commit.committedOps 310743 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 119194 # Number of memory references committed -system.cpu1.commit.loads 80803 # Number of loads committed -system.cpu1.commit.membars 4532 # Number of memory barriers committed -system.cpu1.commit.branches 48886 # Number of branches committed +system.cpu1.commit.refs 137689 # Number of memory references committed +system.cpu1.commit.loads 92644 # Number of loads committed +system.cpu1.commit.membars 3055 # Number of memory barriers committed +system.cpu1.commit.branches 54067 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 190203 # Number of committed integer instructions. +system.cpu1.commit.int_insts 213879 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 448873 # The number of ROB reads -system.cpu1.rob.rob_writes 580482 # The number of ROB writes -system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4402 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 232494 # Number of Instructions Simulated -system.cpu1.committedOps 232494 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 232494 # Number of Instructions Simulated -system.cpu1.cpi 0.748776 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.748776 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.335512 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.335512 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 422524 # number of integer regfile reads -system.cpu1.int_regfile_writes 197153 # number of integer regfile writes +system.cpu1.rob.rob_reads 483263 # The number of ROB reads +system.cpu1.rob.rob_writes 648465 # The number of ROB writes +system.cpu1.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4440 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 262828 # Number of Instructions Simulated +system.cpu1.committedOps 262828 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 262828 # Number of Instructions Simulated +system.cpu1.cpi 0.665036 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.665036 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.503679 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.503679 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 478110 # number of integer regfile reads +system.cpu1.int_regfile_writes 222397 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 122878 # number of misc regfile reads +system.cpu1.misc_regfile_reads 141404 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 85.782711 # Cycle average of tags in use -system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 85.239071 # Cycle average of tags in use +system.cpu1.icache.total_refs 15102 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 35.534118 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 85.782711 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.167544 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.167544 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 18178 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 18178 # number of overall hits -system.cpu1.icache.overall_hits::total 18178 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 85.239071 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.166483 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.166483 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 15102 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15102 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15102 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15102 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15102 # number of overall hits +system.cpu1.icache.overall_hits::total 15102 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses system.cpu1.icache.overall_misses::total 482 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9897000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9897000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9897000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9897000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9897000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9897000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 18660 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 18660 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 18660 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025831 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.025831 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025831 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20533.195021 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20533.195021 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20533.195021 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20533.195021 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10460500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10460500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10460500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10460500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10460500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10460500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15584 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15584 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15584 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15584 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15584 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15584 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030929 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030929 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030929 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030929 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030929 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030929 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21702.282158 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21702.282158 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21702.282158 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21702.282158 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1020,94 +1021,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8054000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8054000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8054000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8054000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8054000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8054000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022776 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022776 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022776 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18950.588235 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8302000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8302000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8302000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8302000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8302000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8302000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027272 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027272 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027272 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19534.117647 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.224520 # Cycle average of tags in use -system.cpu1.dcache.total_refs 44407 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.071497 # Cycle average of tags in use +system.cpu1.dcache.total_refs 51063 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1585.964286 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1823.678571 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.224520 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 47255 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 47255 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 38187 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 38187 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 85442 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 85442 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 85442 # number of overall hits -system.cpu1.dcache.overall_hits::total 85442 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 407 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 407 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 53 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 53 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 544 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 544 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 544 # number of overall misses -system.cpu1.dcache.overall_misses::total 544 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6159500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6159500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2641000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2641000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 528500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 528500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8800500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8800500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8800500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8800500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 47662 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 47662 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 38324 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 38324 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 85986 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 85986 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 85986 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 85986 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008539 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008539 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003575 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003575 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.791045 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.791045 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006327 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006327 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006327 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006327 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19277.372263 # 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number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 52421 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 44839 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 44839 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 97260 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 97260 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 97260 # number of overall hits +system.cpu1.dcache.overall_hits::total 97260 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 438 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 141 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 141 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # 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number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11693500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11693500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11693500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 52859 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 52859 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 44980 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 44980 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 97839 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 97839 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 97839 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 97839 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008286 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008286 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003135 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003135 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.830769 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005918 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005918 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005918 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005918 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19482.876712 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19482.876712 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22411.347518 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22411.347518 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9444.444444 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9444.444444 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20196.027634 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20196.027634 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1116,365 +1117,365 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 252 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 284 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 284 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 284 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 284 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1381000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1381000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2911000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2911000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2911000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2911000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.791045 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.791045 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003024 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13152.380952 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13152.380952 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 152 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1798500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1487000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1487000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 402000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 402000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3285500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3285500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3285500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3285500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002876 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002876 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.830769 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002647 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002647 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11832.236842 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11832.236842 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13897.196262 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13897.196262 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7444.444444 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7444.444444 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 43658 # Number of BP lookups -system.cpu2.branchPred.condPredicted 40905 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1282 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 37514 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 36718 # Number of BTB hits +system.cpu2.branchPred.lookups 45099 # Number of BP lookups +system.cpu2.branchPred.condPredicted 42400 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1262 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 39025 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 38304 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.878125 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.152466 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 646 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 173761 # number of cpu cycles simulated +system.cpu2.numCycles 174459 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 41181 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6111 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 172028 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.367876 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.005593 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 32669 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 244823 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 45099 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 38950 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 90929 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 39674 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 6379 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 24269 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 265 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 172730 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.417374 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.028063 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 83801 48.71% 48.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 732 0.43% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 24119 14.02% 96.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1119 0.65% 97.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 764 0.44% 98.08% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3307 1.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 81801 47.36% 47.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 47495 27.50% 74.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8404 4.87% 79.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3201 1.85% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 675 0.39% 81.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 25947 15.02% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1207 0.70% 97.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 760 0.44% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3240 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 172028 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.251253 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.354234 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 35179 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 231751 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12001 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 158064 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 425055 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 425055 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 145196 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12868 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1106 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 17601 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 61347 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 27349 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 30218 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 22307 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 186544 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11059 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10957 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 172028 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.110238 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.273778 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 172730 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.258508 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.403327 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 39762 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 34129 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 82888 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 7209 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2363 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 241309 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2363 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 40462 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 21352 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11989 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 75976 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14209 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 239275 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 36 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 165256 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 446077 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 446077 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 152520 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12736 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1091 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1215 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 16777 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 64738 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 29196 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 31698 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 24168 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 195168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8612 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 199473 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 10767 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10430 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 172730 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.154825 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.283743 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 81447 47.35% 47.35% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3303 1.92% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1178 0.68% 99.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 79387 45.96% 45.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 29099 16.85% 62.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 29295 16.96% 79.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 30090 17.42% 97.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3300 1.91% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1204 0.70% 99.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 247 0.14% 99.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 172028 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172730 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16 5.67% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 56 19.86% 25.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 74.47% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 96218 50.38% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 68109 35.66% 86.04% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 26665 13.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 99688 49.98% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 71251 35.72% 85.70% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 28534 14.30% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued -system.cpu2.iq.rate 1.099165 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 554408 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 206613 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 189211 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 199473 # Type of FU issued +system.cpu2.iq.rate 1.143380 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 282 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001414 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 572030 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 214590 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 197726 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 191279 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 199755 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 22028 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 23953 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2518 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2414 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1460 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1398 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 904 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 226591 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 61347 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 27349 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1066 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2363 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 870 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 236415 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 392 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 64738 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 29196 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 189819 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1173 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 913 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 198312 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 63718 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1161 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 31084 # number of nop insts executed -system.cpu2.iew.exec_refs 86815 # number of memory reference insts executed -system.cpu2.iew.exec_branches 40244 # Number of branches executed -system.cpu2.iew.exec_stores 26584 # Number of stores executed -system.cpu2.iew.exec_rate 1.092414 # Inst execution rate -system.cpu2.iew.wb_sent 189481 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 189211 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 103581 # num instructions producing a value -system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value +system.cpu2.iew.exec_nop 32635 # number of nop insts executed +system.cpu2.iew.exec_refs 92179 # number of memory reference insts executed +system.cpu2.iew.exec_branches 41831 # Number of branches executed +system.cpu2.iew.exec_stores 28461 # Number of stores executed +system.cpu2.iew.exec_rate 1.136726 # Inst execution rate +system.cpu2.iew.wb_sent 197998 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 197726 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 108943 # num instructions producing a value +system.cpu2.iew.wb_consumers 113613 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.088915 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.133367 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.958896 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 163491 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.308145 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.875240 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12414 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7958 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1262 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 163988 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.365838 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.905647 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 83403 51.01% 51.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1555 0.95% 84.76% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 22612 13.83% 98.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 481 0.29% 98.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1011 0.62% 99.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 815 0.50% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 80806 49.28% 49.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 39854 24.30% 73.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6054 3.69% 77.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8882 5.42% 82.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1574 0.96% 83.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 24481 14.93% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 507 0.31% 98.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1010 0.62% 99.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 820 0.50% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 163491 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 213870 # Number of instructions committed -system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 163988 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 223981 # Number of instructions committed +system.cpu2.commit.committedOps 223981 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 84718 # Number of memory references committed -system.cpu2.commit.loads 58829 # Number of loads committed -system.cpu2.commit.membars 7592 # Number of memory barriers committed -system.cpu2.commit.branches 39438 # Number of branches committed +system.cpu2.commit.refs 90122 # Number of memory references committed +system.cpu2.commit.loads 62324 # Number of loads committed +system.cpu2.commit.membars 7244 # Number of memory barriers committed +system.cpu2.commit.branches 41003 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 146274 # Number of committed integer instructions. +system.cpu2.commit.int_insts 153248 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 820 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 388660 # The number of ROB reads -system.cpu2.rob.rob_writes 455572 # The number of ROB writes -system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1733 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 176057 # Number of Instructions Simulated -system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated -system.cpu2.cpi 0.986959 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.986959 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.013214 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.013214 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 319023 # number of integer regfile reads -system.cpu2.int_regfile_writes 150022 # number of integer regfile writes +system.cpu2.rob.rob_reads 398976 # The number of ROB reads +system.cpu2.rob.rob_writes 475157 # The number of ROB writes +system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1729 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 184944 # Number of Instructions Simulated +system.cpu2.committedOps 184944 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 184944 # Number of Instructions Simulated +system.cpu2.cpi 0.943307 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.943307 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.060100 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.060100 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 335090 # number of integer regfile reads +system.cpu2.int_regfile_writes 157371 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88368 # number of misc regfile reads +system.cpu2.misc_regfile_reads 93758 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.replacements 319 # number of replacements -system.cpu2.icache.tagsinuse 80.119801 # Cycle average of tags in use -system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks. +system.cpu2.icache.tagsinuse 83.416337 # Cycle average of tags in use +system.cpu2.icache.total_refs 23791 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 55.327907 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 80.119801 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 24566 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 24566 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 24566 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 24566 # number of overall hits -system.cpu2.icache.overall_hits::total 24566 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 475 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 475 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses -system.cpu2.icache.overall_misses::total 475 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6355000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6355000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6355000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6355000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6355000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6355000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 25041 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 25041 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 25041 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018969 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.018969 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018969 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13378.947368 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13378.947368 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13378.947368 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13378.947368 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 83.416337 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.162923 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.162923 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 23791 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 23791 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 23791 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 23791 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 23791 # number of overall hits +system.cpu2.icache.overall_hits::total 23791 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses +system.cpu2.icache.overall_misses::total 478 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6751000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6751000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6751000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6751000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6751000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6751000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 24269 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 24269 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 24269 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 24269 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 24269 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 24269 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.019696 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.019696 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.019696 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.019696 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.019696 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.019696 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14123.430962 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14123.430962 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14123.430962 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14123.430962 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1483,106 +1484,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 46 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 46 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 429 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 429 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 429 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5129000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5129000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5129000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5129000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5129000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5129000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017132 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.017132 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.017132 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11955.710956 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 48 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 48 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 48 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 430 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5435000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5435000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5435000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5435000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5435000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5435000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017718 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.017718 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.017718 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12639.534884 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 24.751060 # Cycle average of tags in use -system.cpu2.dcache.total_refs 32016 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 25.649065 # Cycle average of tags in use +system.cpu2.dcache.total_refs 33911 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1104 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1169.344828 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.751060 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048342 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048342 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 37788 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 37788 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 25681 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 25681 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 63469 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 63469 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 63469 # number of overall hits -system.cpu2.dcache.overall_hits::total 63469 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 397 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 397 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 530 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 530 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 530 # number of overall misses -system.cpu2.dcache.overall_misses::total 530 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5134500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5134500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2352000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2352000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 565000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 565000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 7486500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 7486500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 7486500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 7486500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 38185 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 38185 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 25814 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 25814 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 75 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 75 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 63999 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 63999 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 63999 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 63999 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010397 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.010397 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005152 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.005152 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.786667 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.786667 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008281 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12933.249370 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 12933.249370 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17684.210526 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17684.210526 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14125.471698 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14125.471698 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 25.649065 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050096 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050096 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 39345 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 39345 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 27592 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 27592 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 66937 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 66937 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 66937 # number of overall hits +system.cpu2.dcache.overall_hits::total 66937 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 402 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 402 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 138 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 138 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 540 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 540 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 540 # number of overall misses +system.cpu2.dcache.overall_misses::total 540 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5276000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5276000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2759500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2759500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 558000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 558000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8035500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8035500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8035500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8035500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 39747 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 39747 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 27730 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 27730 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 67477 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 67477 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 67477 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 67477 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010114 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010114 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004977 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004977 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.779412 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.779412 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008003 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.008003 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008003 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.008003 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13124.378109 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13124.378109 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19996.376812 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 19996.376812 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10528.301887 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10528.301887 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14880.555556 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14880.555556 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1591,365 +1592,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 227 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 32 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 259 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 259 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 259 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1408000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1408000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1144000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1144000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2552000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2552000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2552000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2552000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003913 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.786667 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.786667 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8282.352941 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8282.352941 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11326.732673 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11326.732673 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 274 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 274 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 274 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 53 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 266 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 266 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1358500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1358500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1350500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1350500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 452000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 452000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2709000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2709000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2709000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2709000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004051 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004051 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003787 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003787 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.779412 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003942 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003942 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8437.888199 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8437.888199 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 12861.904762 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 12861.904762 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8528.301887 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8528.301887 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 53689 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50963 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1276 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 47522 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 46772 # Number of BTB hits +system.cpu3.branchPred.lookups 47073 # Number of BP lookups +system.cpu3.branchPred.condPredicted 44334 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1289 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 40998 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 40129 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.421784 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 661 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.880384 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 173451 # number of cpu cycles simulated +system.cpu3.numCycles 174149 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 47433 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 105433 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 31334 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 257802 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 47073 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 40794 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 94093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3784 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 37693 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6129 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 172033 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.751780 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.162655 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6388 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 691 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23091 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 172622 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.493448 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.066617 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 66600 38.71% 38.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 53421 31.05% 69.77% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 37060 21.54% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 78529 45.49% 45.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 48697 28.21% 73.70% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7780 4.51% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3181 1.84% 80.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 739 0.43% 80.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 28510 16.52% 97.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1109 0.64% 97.64% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 774 0.45% 98.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3303 1.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 172033 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.309534 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.737459 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 99740 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 297875 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 95160 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 295501 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 206976 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 568781 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 568781 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 194055 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 84323 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 40264 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 40234 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 35231 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 245467 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 247268 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10933 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10571 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 172033 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.437329 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.311411 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 172622 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.270303 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.480353 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 38095 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 32492 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 86590 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 6639 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2418 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 254216 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2418 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 38798 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 19631 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12074 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 80231 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 13082 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 251848 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 33 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 174600 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 473869 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 473869 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 161804 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12796 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1100 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1222 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 15769 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 69165 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 31749 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33643 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 26714 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 206536 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7999 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 210100 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10964 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10853 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 623 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 172622 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.217110 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.294923 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 63997 37.20% 37.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 40282 23.42% 73.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 41064 23.87% 97.14% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 76068 44.07% 44.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 27297 15.81% 59.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31861 18.46% 78.34% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 32569 18.87% 97.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3286 1.90% 99.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1177 0.68% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 258 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 172033 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 172622 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 11 3.79% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 69 23.79% 27.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 72.41% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 119306 48.25% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 88375 35.74% 83.99% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 39587 16.01% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 104024 49.51% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 75016 35.70% 85.22% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31060 14.78% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 247268 # Type of FU issued -system.cpu3.iq.rate 1.425578 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 666940 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 262506 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 245488 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 210100 # Type of FU issued +system.cpu3.iq.rate 1.206438 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 290 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001380 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 593222 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 225545 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 208328 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 247555 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 210390 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 34962 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26418 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2499 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1475 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 292672 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 84323 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 40264 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2418 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 854 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 249047 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 69165 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 31749 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1065 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 246092 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 83308 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1408 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 208934 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 68077 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 41144 # number of nop insts executed -system.cpu3.iew.exec_refs 122814 # number of memory reference insts executed -system.cpu3.iew.exec_branches 50378 # Number of branches executed -system.cpu3.iew.exec_stores 39506 # Number of stores executed -system.cpu3.iew.exec_rate 1.418798 # Inst execution rate -system.cpu3.iew.wb_sent 245754 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 245488 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 139611 # num instructions producing a value -system.cpu3.iew.wb_consumers 144276 # num instructions consuming a value +system.cpu3.iew.exec_nop 34512 # number of nop insts executed +system.cpu3.iew.exec_refs 99056 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43690 # Number of branches executed +system.cpu3.iew.exec_stores 30979 # Number of stores executed +system.cpu3.iew.exec_rate 1.199743 # Inst execution rate +system.cpu3.iew.wb_sent 208597 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 208328 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 115832 # num instructions producing a value +system.cpu3.iew.wb_consumers 120507 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.415316 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.967666 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.196263 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.961206 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 163517 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.713131 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.043728 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12582 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7376 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1289 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 163816 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.443357 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.942306 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 63246 38.68% 38.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48405 29.60% 68.28% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 35438 21.67% 98.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 76810 46.89% 46.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 41800 25.52% 72.40% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6086 3.72% 76.12% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8257 5.04% 81.16% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1545 0.94% 82.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 27022 16.50% 98.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 472 0.29% 98.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1012 0.62% 99.50% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 163517 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 280126 # Number of instructions committed -system.cpu3.commit.committedOps 280126 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 163816 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 236445 # Number of instructions committed +system.cpu3.commit.committedOps 236445 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 120655 # Number of memory references committed -system.cpu3.commit.loads 81860 # Number of loads committed -system.cpu3.commit.membars 4779 # Number of memory barriers committed -system.cpu3.commit.branches 49541 # Number of branches committed +system.cpu3.commit.refs 96940 # Number of memory references committed +system.cpu3.commit.loads 66666 # Number of loads committed +system.cpu3.commit.membars 6656 # Number of memory barriers committed +system.cpu3.commit.branches 42889 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 192316 # Number of committed integer instructions. +system.cpu3.commit.int_insts 161946 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 454770 # The number of ROB reads -system.cpu3.rob.rob_writes 587696 # The number of ROB writes -system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1418 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 36213 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 235015 # Number of Instructions Simulated -system.cpu3.committedOps 235015 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 235015 # Number of Instructions Simulated -system.cpu3.cpi 0.738042 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.738042 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.354936 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.354936 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 427046 # number of integer regfile reads -system.cpu3.int_regfile_writes 198986 # number of integer regfile writes +system.cpu3.rob.rob_reads 411444 # The number of ROB reads +system.cpu3.rob.rob_writes 500477 # The number of ROB writes +system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1527 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 196116 # Number of Instructions Simulated +system.cpu3.committedOps 196116 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 196116 # Number of Instructions Simulated +system.cpu3.cpi 0.887990 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.887990 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.126139 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.126139 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 355696 # number of integer regfile reads +system.cpu3.int_regfile_writes 166589 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 124374 # number of misc regfile reads +system.cpu3.misc_regfile_reads 100584 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 83.494084 # Cycle average of tags in use -system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks. +system.cpu3.icache.tagsinuse 80.204482 # Cycle average of tags in use +system.cpu3.icache.total_refs 22614 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 52.713287 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 83.494084 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 18731 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 18731 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 18731 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 18731 # number of overall hits -system.cpu3.icache.overall_hits::total 18731 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 474 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 474 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 474 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 474 # number of overall misses -system.cpu3.icache.overall_misses::total 474 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6189500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6189500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6189500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6189500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6189500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6189500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 19205 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 19205 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 19205 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024681 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.024681 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024681 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13058.016878 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13058.016878 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13058.016878 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13058.016878 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 80.204482 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.156649 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.156649 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 22614 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 22614 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 22614 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 22614 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 22614 # 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number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6252000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 23091 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 23091 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 23091 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 23091 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 23091 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 23091 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020657 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.020657 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020657 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.020657 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020657 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.020657 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13106.918239 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13106.918239 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13106.918239 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13106.918239 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # 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number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 428 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4969500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4969500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4969500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4969500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4969500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4969500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022286 # 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number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4992500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4992500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4992500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4992500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4992500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4992500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.018579 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.018579 # 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Cycle average of tags in use -system.cpu3.dcache.total_refs 44812 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 24.557568 # Cycle average of tags in use +system.cpu3.dcache.total_refs 36284 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1600.428571 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1295.857143 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.854191 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050496 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050496 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 47902 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 47902 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 38586 # 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number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 71841 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 71841 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 71841 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 71841 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009030 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009030 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004305 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004305 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797297 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.797297 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007043 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007043 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12982.712766 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12982.712766 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19534.615385 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19534.615385 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9254.237288 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9254.237288 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14666.007905 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 14666.007905 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14666.007905 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 14666.007905 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2066,288 +2067,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 273 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 273 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 306 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 306 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 153 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1264000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1264000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1158000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1158000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 443000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 443000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2422000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2422000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2422000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2422000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003166 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002815 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002815 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003010 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003010 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8261.437908 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8261.437908 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10623.853211 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10623.853211 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7910.714286 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7910.714286 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 218 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 30 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 30 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 248 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 248 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 258 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 258 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1328000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1328000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1243000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1243000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 428000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 428000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2571000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2571000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2571000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2571000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003794 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003794 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003311 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003311 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797297 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797297 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003591 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003591 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8405.063291 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8405.063291 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12430 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12430 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7254.237288 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7254.237288 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 425.291959 # Cycle average of tags in use -system.l2c.total_refs 1448 # Total number of references to valid blocks. -system.l2c.sampled_refs 525 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.758095 # Average number of references to valid blocks. +system.l2c.tagsinuse 425.230692 # Cycle average of tags in use +system.l2c.total_refs 1445 # Total number of references to valid blocks. +system.l2c.sampled_refs 527 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.828889 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 289.887816 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.267955 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 63.508377 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.639601 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2.310233 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.728238 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 2.354132 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.766718 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.832857 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 61.730806 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 4.388881 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.722095 # 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Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000067 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 230 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 418 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 424 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38460 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28752 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.926415 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64520 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index eb01eb1c6..e7866c92f 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 18434818132 # Simulator tick rate (ticks/s) -host_mem_usage 219256 # Number of bytes of host memory used -host_seconds 5.42 # Real time elapsed on the host +host_tick_rate 29045358432 # Simulator tick rate (ticks/s) +host_mem_usage 222412 # Number of bytes of host memory used +host_seconds 3.44 # Real time elapsed on the host system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory @@ -25,21 +25,21 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 210200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 210200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 208000 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -86,18 +86,18 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3267797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 52471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -152,25 +152,25 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2980562702 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 63351670702 # Sum of mem lat for all requests -system.physmem.totBusLat 13333600000 # Total cycles spent in databus access -system.physmem.totBankLat 47037508000 # Total cycles spent in bank access -system.physmem.avgQLat 894.15 # Average queueing delay per request -system.physmem.avgBankLat 14110.97 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19005.12 # Average memory access latency +system.physmem.totQLat 6115686626 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 69505296626 # Sum of mem lat for all requests +system.physmem.totBusLat 16667000000 # Total cycles spent in databus access +system.physmem.totBankLat 46722610000 # Total cycles spent in bank access +system.physmem.avgQLat 1834.67 # Average queueing delay per request +system.physmem.avgBankLat 14016.50 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 20851.17 # Average memory access latency system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 13.33 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.63 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 16.67 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.70 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3281300 # Number of row buffer hits during reads +system.physmem.readRowHits 3229200 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 96.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 29999.40 # Average gap between requests system.monitor.readBurstLengthHist::samples 3333400 # Histogram of burst lengths of transmitted packets @@ -278,20 +278,20 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.readLatencyHist::samples 3333399 # Read request-response latency -system.monitor.readLatencyHist::mean 19061.873685 # Read request-response latency -system.monitor.readLatencyHist::gmean 18381.352509 # Read request-response latency -system.monitor.readLatencyHist::stdev 11230.520439 # Read request-response latency -system.monitor.readLatencyHist::0-32767 3267631 98.03% 98.03% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 52364 1.57% 99.60% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 2680 0.08% 99.68% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 2415 0.07% 99.75% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 2133 0.06% 99.81% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 1602 0.05% 99.86% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 1620 0.05% 99.91% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 1066 0.03% 99.94% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 802 0.02% 99.97% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 812 0.02% 99.99% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 274 0.01% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 20879.051770 # Read request-response latency +system.monitor.readLatencyHist::gmean 19622.150808 # Read request-response latency +system.monitor.readLatencyHist::stdev 15688.008500 # Read request-response latency +system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 4826 0.14% 99.50% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 4267 0.13% 99.63% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 3205 0.10% 99.73% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 3236 0.10% 99.82% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 2130 0.06% 99.89% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 1602 0.05% 99.94% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 1620 0.05% 99.98% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 546 0.02% 100.00% # Read request-response latency system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency |