diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:15:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:15:59 -0400 |
| commit | b387d8e2136b6eccf590e5223096dce6830a66ec (patch) | |
| tree | e1ec53e315c313a54a612b54b74164375dcc0a1d /tests/quick | |
| parent | 6f6adbf0f6a4ca96cf44a24ea575860af56eb7b2 (diff) | |
| download | gem5-b387d8e2136b6eccf590e5223096dce6830a66ec.tar.xz | |
stats: Update the stats to reflect the 1GHz default system clock
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
Diffstat (limited to 'tests/quick')
5 files changed, 1987 insertions, 1987 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e568ced30..ab95e5b1c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.950813 # Number of seconds simulated -sim_ticks 1950813247500 # Number of ticks simulated -final_tick 1950813247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.950814 # Number of seconds simulated +sim_ticks 1950813955500 # Number of ticks simulated +final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1287440 # Simulator instruction rate (inst/s) -host_op_rate 1287440 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41184614921 # Simulator tick rate (ticks/s) +host_inst_rate 770652 # Simulator instruction rate (inst/s) +host_op_rate 770652 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24652738853 # Simulator tick rate (ticks/s) host_mem_usage 325660 # Number of bytes of host memory used -host_seconds 47.37 # Real time elapsed on the host -sim_insts 60982794 # Number of instructions simulated -sim_ops 60982794 # Number of ops (including micro ops) simulated +host_seconds 79.13 # Real time elapsed on the host +sim_insts 60983017 # Number of instructions simulated +sim_ops 60983017 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24727680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 439808 # Number of bytes read from this memory -system.physmem.bytes_read::total 28684096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory +system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7706368 # Number of bytes written to this memory -system.physmem.bytes_written::total 7706368 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory +system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386370 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6872 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448189 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120412 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120412 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12675575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1358859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 225449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14703661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3950336 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3950336 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3950336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12675575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1358859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 225449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18653997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448189 # Total number of read requests seen -system.physmem.writeReqs 120412 # Total number of write requests seen -system.physmem.cpureqs 599134 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28684096 # Total number of bytes read from memory -system.physmem.bytesWritten 7706368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28684096 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7706368 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448191 # Total number of read requests seen +system.physmem.writeReqs 120414 # Total number of write requests seen +system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28684224 # Total number of bytes read from memory +system.physmem.bytesWritten 7706496 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7172 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis @@ -72,7 +72,7 @@ system.physmem.perBankRdReqs::11 28196 # Tr system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27647 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis @@ -88,17 +88,17 @@ system.physmem.perBankWrReqs::11 7772 # Tr system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 522 # Number of times wr buffer was full causing retry -system.physmem.totGap 1950759532000 # Total gap between requests +system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry +system.physmem.totGap 1950760240000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448189 # Categorize read packet sizes +system.physmem.readPktSize::6 448191 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 120934 # categorize write packet sizes +system.physmem.writePktSize::6 120944 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,29 +116,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 7172 # categorize neither packet sizes +system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 409832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1753 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 409750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -152,13 +152,13 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5228 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see @@ -175,24 +175,24 @@ system.physmem.wrQLenPdf::19 5235 # Wh system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2865774804 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10947900804 # Sum of mem lat for all requests -system.physmem.totBusLat 1792528000 # Total cycles spent in databus access -system.physmem.totBankLat 6289598000 # Total cycles spent in bank access -system.physmem.avgQLat 6394.93 # Average queueing delay per request -system.physmem.avgBankLat 14035.15 # Average bank access latency per request +system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests +system.physmem.totBusLat 1792536000 # Total cycles spent in databus access +system.physmem.totBankLat 6288996000 # Total cycles spent in bank access +system.physmem.avgQLat 6509.40 # Average queueing delay per request +system.physmem.avgBankLat 14033.74 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24430.08 # Average memory access latency +system.physmem.avgMemAccLat 24543.14 # Average memory access latency system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s @@ -200,177 +200,177 @@ system.physmem.avgConsumedWrBW 3.95 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.50 # Average write queue length over time -system.physmem.readRowHits 428033 # Number of row buffer hits during reads -system.physmem.writeRowHits 76777 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads +system.physmem.avgWrQLen 10.51 # Average write queue length over time +system.physmem.readRowHits 428061 # Number of row buffer hits during reads +system.physmem.writeRowHits 76773 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes -system.physmem.avgGap 3430805.67 # Average gap between requests -system.l2c.replacements 341333 # number of replacements -system.l2c.tagsinuse 65247.038846 # Cycle average of tags in use -system.l2c.total_refs 2438074 # Total number of references to valid blocks. -system.l2c.sampled_refs 406309 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.000541 # Average number of references to valid blocks. +system.physmem.avgGap 3430782.78 # Average gap between requests +system.l2c.replacements 341335 # number of replacements +system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use +system.l2c.total_refs 2438054 # Total number of references to valid blocks. +system.l2c.sampled_refs 406311 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.000463 # Average number of references to valid blocks. system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55545.297156 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4807.218464 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4686.690338 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 164.376104 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 43.456784 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.847554 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 55545.332470 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4807.217204 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4686.652945 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 164.376424 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 43.456861 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.847555 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 674220 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 658221 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 328583 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 113537 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774561 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 791464 # number of Writeback hits -system.l2c.Writeback_hits::total 791464 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits +system.l2c.ReadReq_hits::cpu0.inst 674205 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 658217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 328581 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 113535 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774538 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 791470 # number of Writeback hits +system.l2c.Writeback_hits::total 791470 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 738 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 123896 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48958 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172854 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 674220 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 782117 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 328583 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 162495 # number of demand (read+write) hits -system.l2c.demand_hits::total 1947415 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 674220 # number of overall hits -system.l2c.overall_hits::cpu0.data 782117 # number of overall hits -system.l2c.overall_hits::cpu1.inst 328583 # number of overall hits -system.l2c.overall_hits::cpu1.data 162495 # number of overall hits -system.l2c.overall_hits::total 1947415 # number of overall hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 123887 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 48972 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172859 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 674205 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 782104 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 328581 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 162507 # number of demand (read+write) hits +system.l2c.demand_hits::total 1947397 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 674205 # number of overall hits +system.l2c.overall_hits::cpu0.data 782104 # number of overall hits +system.l2c.overall_hits::cpu1.inst 328581 # number of overall hits +system.l2c.overall_hits::cpu1.data 162507 # number of overall hits +system.l2c.overall_hits::total 1947397 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 12926 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 271631 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 612 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 247 # number of ReadReq misses system.l2c.ReadReq_misses::total 285416 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2967 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1807 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4774 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2969 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1806 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4775 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 939 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 942 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1881 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115504 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6643 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122147 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 944 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1883 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115505 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6644 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122149 # number of ReadExReq misses system.l2c.demand_misses::cpu0.inst 12926 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387135 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387136 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 612 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6890 # number of demand (read+write) misses -system.l2c.demand_misses::total 407563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6891 # number of demand (read+write) misses +system.l2c.demand_misses::total 407565 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 12926 # number of overall misses -system.l2c.overall_misses::cpu0.data 387135 # number of overall misses +system.l2c.overall_misses::cpu0.data 387136 # number of overall misses system.l2c.overall_misses::cpu1.inst 612 # number of overall misses -system.l2c.overall_misses::cpu1.data 6890 # number of overall misses -system.l2c.overall_misses::total 407563 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 713316000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11504038499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 34128500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 15210000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 12266692999 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.data 6891 # number of overall misses +system.l2c.overall_misses::total 407565 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 706675500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11506519500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 33342000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 15821000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 12262358000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 1244500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10405497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11649997 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 841000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 205500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1046500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5694760500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 427293500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6122054000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 713316000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 17198798999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 34128500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 442503500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 18388746999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 713316000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 17198798999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 34128500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 442503500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 18388746999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 687146 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 929852 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 329195 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 113784 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2059977 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 791464 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 791464 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_miss_latency::cpu1.data 10405997 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11650497 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 840000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1022000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5700012000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 427427500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6127439500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 706675500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 17206531500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 33342000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 443248500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 18389797500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 706675500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 17206531500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 33342000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 443248500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 18389797500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 687131 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 929848 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 329193 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 113782 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2059954 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 791470 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 791470 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3143 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2374 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5517 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2370 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5513 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 975 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 965 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1940 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 239400 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 55601 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295001 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 687146 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1169252 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 329195 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 169385 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2354978 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 687146 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1169252 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 329195 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 169385 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2354978 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018811 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.292123 # miss rate for ReadReq accesses +system.l2c.SCUpgradeReq_accesses::cpu1.data 968 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1943 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 239392 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 55616 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295008 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 687131 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1169240 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 329193 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 169398 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2354962 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 687131 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1169240 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 329193 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 169398 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2354962 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018812 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.292124 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.001859 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.002171 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138553 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944003 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.761163 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.865325 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.138555 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944639 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.762025 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.866135 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963077 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976166 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.969588 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.482473 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.119476 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.414056 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018811 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.331096 # miss rate for demand accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975207 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969120 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.482493 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.119462 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.414053 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018812 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.331101 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.001859 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.040677 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173064 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018811 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.331096 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu1.data 0.040679 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173066 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018812 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.331101 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.001859 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.040677 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173064 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55184.589200 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 42351.714270 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55765.522876 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 61578.947368 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 42978.294836 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 419.447253 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5758.437742 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2440.301005 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 895.633653 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 218.152866 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 556.353004 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49303.578231 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64322.369411 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 50120.379543 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55184.589200 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 44425.843695 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 55765.522876 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 64224.020319 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 45118.784087 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55184.589200 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 44425.843695 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 55765.522876 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 64224.020319 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 45118.784087 # average overall miss latency +system.l2c.overall_miss_rate::cpu1.data 0.040679 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173066 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 54670.857187 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 42360.847989 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54480.392157 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 64052.631579 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 42963.106483 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 419.164702 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5761.903101 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2439.894660 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 894.568690 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 192.796610 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 542.750929 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49348.616943 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64332.856713 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 50163.648495 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 54670.857187 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 44445.702544 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 54480.392157 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 64322.812364 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 45121.140186 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 54670.857187 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 44445.702544 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 54480.392157 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 64322.812364 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 45121.140186 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,8 +379,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 78892 # number of writebacks -system.l2c.writebacks::total 78892 # number of writebacks +system.l2c.writebacks::writebacks 78894 # number of writebacks +system.l2c.writebacks::total 78894 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits @@ -392,106 +392,106 @@ system.l2c.ReadReq_mshr_misses::cpu0.data 271631 # n system.l2c.ReadReq_mshr_misses::cpu1.inst 601 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 247 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 285405 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2967 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1807 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4774 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2969 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1806 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4775 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 939 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 942 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1881 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 115504 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6643 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122147 # number of ReadExReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 944 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1883 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115505 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6644 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122149 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 12926 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387135 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387136 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 601 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6890 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407552 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6891 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407554 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 12926 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387135 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387136 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 601 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6890 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407552 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 549819387 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7975375490 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 25997165 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12059975 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 8563252017 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29825962 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18084304 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 47910266 # number of UpgradeReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.data 6891 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407554 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 543164896 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7977851486 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 25213167 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12672975 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 8558902524 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29845964 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18081803 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47927767 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9405923 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9420942 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 18826865 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4202676375 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 343429954 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4546106329 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 549819387 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 12178051865 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 25997165 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 355489929 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 13109358346 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 549819387 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 12178051865 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 25997165 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 355489929 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 13109358346 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370389500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18130000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1388519500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2151186500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 682990000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2834176500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3521576000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701120000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4222696000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292123 # mshr miss rate for ReadReq accesses +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9440944 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 18846867 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207932893 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 343549452 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4551482345 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 543164896 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12185784379 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 25213167 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 356222427 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 13110384869 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 543164896 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12185784379 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 25213167 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 356222427 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 13110384869 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373080000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18172000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1391252000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2155311500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 683999000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2839310500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3528391500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 702171000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4230562500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292124 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002171 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.138548 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944003 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.761163 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.865325 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138549 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944639 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.762025 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.866135 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.963077 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976166 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969588 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482473 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119476 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.414056 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for demand accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975207 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969120 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482493 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119462 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.414053 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173060 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173062 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173060 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29361.065158 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48825.809717 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 30003.861239 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.565554 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10007.915883 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.665270 # average UpgradeReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173062 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29370.180451 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 51307.591093 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 29988.621517 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.530818 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.072536 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.228691 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.957401 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.965976 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36385.548336 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51698.021075 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37218.321604 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.957515 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36430.742332 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51708.225768 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37261.724165 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -503,12 +503,12 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.562945 # Cycle average of tags in use +system.iocache.tagsinuse 0.562950 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.562945 # Average occupied blocks per requestor +system.iocache.occ_blocks::tsunami.ide 0.562950 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses @@ -521,12 +521,12 @@ system.iocache.overall_misses::tsunami.ide 41728 # system.iocache.overall_misses::total 41728 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9455401806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9455401806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9476670804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9476670804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9476670804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9476670804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -545,17 +545,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 227555.877118 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 227555.877118 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227105.799559 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227105.799559 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 186741 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23044 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.103671 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -571,12 +571,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41728 system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7292629022 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7292629022 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7304745022 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7304745022 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7304745022 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7304745022 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -587,12 +587,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175506.089286 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 175506.089286 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -610,15 +610,15 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7424678 # DTB read hits +system.cpu0.dtb.read_hits 7424685 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5011102 # DTB write hits +system.cpu0.dtb.write_hits 5011105 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12435780 # DTB hits +system.cpu0.dtb.data_hits 12435790 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses @@ -638,28 +638,28 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3900399022 # number of cpu cycles simulated +system.cpu0.numCycles 3900399041 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47350752 # Number of instructions committed -system.cpu0.committedOps 47350752 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43919757 # Number of integer alu accesses +system.cpu0.committedInsts 47350784 # Number of instructions committed +system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses system.cpu0.num_func_calls 1188579 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5567605 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43919757 # number of integer instructions +system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43919786 # number of integer instructions system.cpu0.num_fp_insts 206365 # number of float instructions -system.cpu0.num_int_register_reads 60378447 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32741783 # number of times the integer registers were written +system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written -system.cpu0.num_mem_refs 12475681 # number of memory refs -system.cpu0.num_load_insts 7451619 # Number of load instructions -system.cpu0.num_store_insts 5024062 # Number of store instructions -system.cpu0.num_idle_cycles 3698907701.219057 # Number of idle cycles -system.cpu0.num_busy_cycles 201491320.780943 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051659 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948341 # Percentage of idle cycles +system.cpu0.num_mem_refs 12475691 # number of memory refs +system.cpu0.num_load_insts 7451626 # Number of load instructions +system.cpu0.num_store_insts 5024065 # Number of store instructions +system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles +system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed @@ -675,12 +675,12 @@ system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # nu system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898626830000 97.36% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93050500 0.00% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 759970000 0.04% 97.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 326793000 0.02% 97.42% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 50392837500 2.58% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1950199481000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -745,8 +745,8 @@ system.cpu0.kern.mode_switch_good::kernel 0.186890 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1946498286500 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3408187000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3025 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -780,51 +780,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 686559 # number of replacements -system.cpu0.icache.tagsinuse 509.179293 # Cycle average of tags in use -system.cpu0.icache.total_refs 46672188 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 687071 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.929207 # Average number of references to valid blocks. +system.cpu0.icache.replacements 686544 # number of replacements +system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use +system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.179293 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 46672188 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46672188 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46672188 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46672188 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46672188 # number of overall hits -system.cpu0.icache.overall_hits::total 46672188 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687164 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687164 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687164 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687164 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687164 # number of overall misses -system.cpu0.icache.overall_misses::total 687164 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9577778500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9577778500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9577778500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9577778500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9577778500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9577778500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359352 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47359352 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47359352 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47359352 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47359352 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47359352 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014510 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014510 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014510 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014510 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014510 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014510 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13938.126124 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13938.126124 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13938.126124 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13938.126124 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 46672235 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46672235 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46672235 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46672235 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46672235 # number of overall hits +system.cpu0.icache.overall_hits::total 46672235 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687149 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687149 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687149 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687149 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687149 # number of overall misses +system.cpu0.icache.overall_misses::total 687149 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9571696500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9571696500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9571696500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9571696500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9571696500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9571696500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359384 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47359384 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47359384 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47359384 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47359384 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47359384 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014509 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014509 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014509 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014509 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014509 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014509 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13929.579320 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13929.579320 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13929.579320 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13929.579320 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,112 +833,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687164 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687164 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687164 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687164 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687164 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687164 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8203450500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8203450500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8203450500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8203450500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8203450500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8203450500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014510 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014510 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014510 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11938.126124 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687149 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687149 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687149 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687149 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687149 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687149 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8197398500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8197398500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8197398500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8197398500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8197398500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8197398500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014509 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014509 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014509 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11929.579320 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1171741 # number of replacements -system.cpu0.dcache.tagsinuse 505.264481 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11253752 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1172158 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.600883 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1171731 # number of replacements +system.cpu0.dcache.tagsinuse 505.264467 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11253773 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1172148 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.600983 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.264481 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 505.264467 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6351991 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6351991 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4607363 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4607363 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138394 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138394 # number of LoadLockedReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 6351999 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6351999 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4607371 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4607371 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138396 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138396 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10959354 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10959354 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10959354 # number of overall hits -system.cpu0.dcache.overall_hits::total 10959354 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 933040 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 933040 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249280 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249280 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13436 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13436 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 10959370 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10959370 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10959370 # number of overall hits +system.cpu0.dcache.overall_hits::total 10959370 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 933038 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 933038 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 249274 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 249274 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13435 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13435 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1182320 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1182320 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1182320 # number of overall misses -system.cpu0.dcache.overall_misses::total 1182320 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20820883000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 20820883000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7761604000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7761604000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144502500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 144502500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43447000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 43447000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 28582487000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28582487000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 28582487000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28582487000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285031 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7285031 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856643 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4856643 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151830 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1182312 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1182312 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1182312 # number of overall misses +system.cpu0.dcache.overall_misses::total 1182312 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20824713000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 20824713000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7766651000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7766651000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144248500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 144248500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43490500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 43490500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 28591364000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 28591364000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 28591364000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 28591364000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285037 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7285037 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856645 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4856645 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151831 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 151831 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12141674 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12141674 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12141674 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12141674 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12141682 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12141682 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12141682 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12141682 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051328 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051328 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088494 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088494 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051326 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051326 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088487 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088487 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097377 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097377 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097377 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097377 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22315.102246 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22315.102246 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31136.087933 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31136.087933 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10754.874963 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10754.874963 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7581.050427 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7581.050427 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24174.916266 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24174.916266 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097376 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097376 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097376 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097376 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22319.254950 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22319.254950 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31157.084172 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31157.084172 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10736.769632 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10736.769632 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7588.640726 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7588.640726 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24182.588014 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24182.588014 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,62 +947,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672349 # number of writebacks -system.cpu0.dcache.writebacks::total 672349 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933040 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 933040 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249280 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249280 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13436 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13436 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 672345 # number of writebacks +system.cpu0.dcache.writebacks::total 672345 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933038 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 933038 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249274 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249274 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13435 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13435 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182320 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1182320 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182320 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1182320 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18954803000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18954803000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7263044000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7263044000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117630500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117630500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31985000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31985000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26217847000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26217847000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26217847000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26217847000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465453500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465453500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285524000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285524000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750977500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182312 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1182312 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182312 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088494 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088494 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097377 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097377 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20315.102246 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20315.102246 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29136.087933 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29136.087933 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8754.874963 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8754.874963 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5581.050427 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5581.050427 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1014,15 +1014,15 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2500235 # DTB read hits +system.cpu1.dtb.read_hits 2500361 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1820988 # DTB write hits +system.cpu1.dtb.write_hits 1820984 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4321223 # DTB hits +system.cpu1.dtb.data_hits 4321345 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses @@ -1042,26 +1042,26 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3901626495 # number of cpu cycles simulated +system.cpu1.numCycles 3901627911 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13632042 # Number of instructions committed -system.cpu1.committedOps 13632042 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12571491 # Number of integer alu accesses +system.cpu1.committedInsts 13632233 # Number of instructions committed +system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses -system.cpu1.num_func_calls 426717 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1355011 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12571491 # number of integer instructions +system.cpu1.num_func_calls 426713 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12571690 # number of integer instructions system.cpu1.num_fp_insts 180459 # number of float instructions -system.cpu1.num_int_register_reads 17311598 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9221787 # number of times the integer registers were written +system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written -system.cpu1.num_mem_refs 4345531 # number of memory refs -system.cpu1.num_load_insts 2514982 # Number of load instructions -system.cpu1.num_store_insts 1830549 # Number of store instructions -system.cpu1.num_idle_cycles 3850258507.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 51367987.001974 # Number of busy cycles +system.cpu1.num_mem_refs 4345653 # number of memory refs +system.cpu1.num_load_insts 2515108 # Number of load instructions +system.cpu1.num_store_insts 1830545 # Number of store instructions +system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles +system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -1077,11 +1077,11 @@ system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # nu system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1907138262500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705201000 0.04% 97.80% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 364168000 0.02% 97.82% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42604858000 2.18% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1950812489500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -1118,65 +1118,65 @@ system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # nu system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.callpal::total 73828 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2126 # number of protection mode switches +system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2924 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches system.cpu1.kern.mode_good::kernel 915 system.cpu1.kern.mode_good::user 465 system.cpu1.kern.mode_good::idle 450 -system.cpu1.kern.mode_switch_good::kernel 0.430386 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153899 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18665784500 0.96% 0.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1711228500 0.09% 1.04% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1930435473000 98.96% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2086 # number of times the context was actually changed -system.cpu1.icache.replacements 328648 # number of replacements -system.cpu1.icache.tagsinuse 446.257828 # Cycle average of tags in use -system.cpu1.icache.total_refs 13306209 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 329160 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.424745 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1948917036000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 446.257828 # Average occupied blocks per requestor +system.cpu1.icache.replacements 328646 # number of replacements +system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use +system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 13306209 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13306209 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13306209 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13306209 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13306209 # number of overall hits -system.cpu1.icache.overall_hits::total 13306209 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 329196 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 329196 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 329196 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 329196 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 329196 # number of overall misses -system.cpu1.icache.overall_misses::total 329196 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4347354500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4347354500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4347354500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4347354500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4347354500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4347354500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635405 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13635405 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13635405 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13635405 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13635405 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13635405 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024143 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024143 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024143 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024143 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024143 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024143 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13205.976075 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13205.976075 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13205.976075 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13205.976075 # average overall miss latency +system.cpu1.icache.ReadReq_hits::cpu1.inst 13306402 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13306402 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13306402 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13306402 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13306402 # number of overall hits +system.cpu1.icache.overall_hits::total 13306402 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 329194 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 329194 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 329194 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 329194 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 329194 # number of overall misses +system.cpu1.icache.overall_misses::total 329194 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4346536000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4346536000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4346536000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4346536000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4346536000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4346536000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635596 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13635596 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13635596 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13635596 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13635596 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13635596 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024142 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024142 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024142 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024142 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024142 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024142 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13203.569931 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13203.569931 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13203.569931 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,112 +1185,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329196 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 329196 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 329196 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 329196 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 329196 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 329196 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688962500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688962500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688962500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3688962500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688962500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3688962500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024143 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024143 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024143 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11205.976075 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329194 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 329194 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 329194 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 329194 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 329194 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 329194 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688148000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688148000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688148000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3688148000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688148000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3688148000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024142 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024142 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024142 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11203.569931 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 172786 # number of replacements -system.cpu1.dcache.tagsinuse 487.450805 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4146223 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 173298 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 23.925394 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 62292634000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.450805 # Average occupied blocks per requestor +system.cpu1.dcache.replacements 172801 # number of replacements +system.cpu1.dcache.tagsinuse 487.450819 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4146327 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 173313 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 23.923924 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 62292445000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.450819 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.952052 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.952052 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2329094 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2329094 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1699243 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1699243 # number of WriteReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 2329216 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2329216 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1699225 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1699225 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50220 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52927 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 52927 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4028337 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4028337 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4028337 # number of overall hits -system.cpu1.dcache.overall_hits::total 4028337 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123236 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123236 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 64754 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 64754 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9347 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9347 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6143 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6143 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 187990 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 187990 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 187990 # number of overall misses -system.cpu1.dcache.overall_misses::total 187990 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1493692000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1493692000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166299500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1166299500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85390000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 85390000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44515500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 44515500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2659991500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2659991500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2659991500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2659991500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452330 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2452330 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763997 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1763997 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59567 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59567 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59070 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59070 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4216327 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4216327 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4216327 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4216327 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050253 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050253 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036709 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036709 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156916 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156916 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103995 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103995 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044586 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044586 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044586 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044586 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12120.581648 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12120.581648 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.234827 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.234827 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.551514 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.551514 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7246.540778 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7246.540778 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14149.643598 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14149.643598 # average overall miss latency +system.cpu1.dcache.demand_hits::cpu1.data 4028441 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4028441 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4028441 # number of overall hits +system.cpu1.dcache.overall_hits::total 4028441 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 123241 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 123241 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 64769 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 64769 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9346 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9346 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6142 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6142 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 188010 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 188010 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 188010 # number of overall misses +system.cpu1.dcache.overall_misses::total 188010 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1494406500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1494406500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166606000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1166606000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85391000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 85391000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44592000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 44592000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2661012500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2661012500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2661012500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2661012500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452457 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2452457 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763994 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1763994 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59566 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 59566 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59069 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59069 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4216451 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4216451 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4216451 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4216451 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050252 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050252 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036717 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036717 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156902 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156902 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103980 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103980 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044590 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044590 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044590 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044590 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12125.887489 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12125.887489 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.795766 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.795766 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9136.635994 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9136.635994 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7260.175838 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7260.175838 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14153.568959 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14153.568959 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1299,62 +1299,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119115 # number of writebacks -system.cpu1.dcache.writebacks::total 119115 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123236 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123236 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64754 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 64754 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9347 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9347 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6143 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6143 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 187990 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 187990 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 187990 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 187990 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247220000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247220000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1036791500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1036791500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66696000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66696000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32229500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32229500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284011500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2284011500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284011500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2284011500 # number of overall MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 119125 # number of writebacks +system.cpu1.dcache.writebacks::total 119125 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123241 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 123241 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64769 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 64769 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9346 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9346 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6142 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6142 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 188010 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 188010 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 188010 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 188010 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247924500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247924500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723171500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723171500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742552500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742552500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050253 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050253 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036709 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036709 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156916 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156916 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103995 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103995 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044586 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044586 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10120.581648 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10120.581648 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.234827 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.234827 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.551514 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.551514 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5246.540778 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5246.540778 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 997f2e448..dfbac48e1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.910582 # Nu sim_ticks 1910582068000 # Number of ticks simulated final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1092208 # Simulator instruction rate (inst/s) -host_op_rate 1092208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37180157619 # Simulator tick rate (ticks/s) -host_mem_usage 321564 # Number of bytes of host memory used -host_seconds 51.39 # Real time elapsed on the host +host_inst_rate 942466 # Simulator instruction rate (inst/s) +host_op_rate 942466 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32082735017 # Simulator tick rate (ticks/s) +host_mem_usage 321492 # Number of bytes of host memory used +host_seconds 59.55 # Real time elapsed on the host sim_insts 56125446 # Number of instructions simulated sim_ops 56125446 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory @@ -815,12 +815,12 @@ system.cpu.l2cache.demand_mshr_miss_latency::total 12860525290 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 561273079 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1891670000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1891670000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223220000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223220000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229367500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229367500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 70af125f4..af19e8e2a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,84 +1,84 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.182883 # Number of seconds simulated -sim_ticks 1182883077500 # Number of ticks simulated -final_tick 1182883077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1182883275000 # Number of ticks simulated +final_tick 1182883275000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 330156 # Simulator instruction rate (inst/s) -host_op_rate 420694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6355289452 # Simulator tick rate (ticks/s) -host_mem_usage 400808 # Number of bytes of host memory used -host_seconds 186.13 # Real time elapsed on the host -sim_insts 61450599 # Number of instructions simulated -sim_ops 78301940 # Number of ops (including micro ops) simulated +host_inst_rate 656929 # Simulator instruction rate (inst/s) +host_op_rate 837075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12645375755 # Simulator tick rate (ticks/s) +host_mem_usage 400812 # Number of bytes of host memory used +host_seconds 93.54 # Real time elapsed on the host +sim_insts 61450949 # Number of instructions simulated +sim_ops 78302298 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4712308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4708212 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4776304 # Number of bytes read from this memory -system.physmem.bytes_read::total 62110116 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4780336 # Number of bytes read from this memory +system.physmem.bytes_read::total 62110052 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4085952 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4085888 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7113296 # Number of bytes written to this memory +system.physmem.bytes_written::total 7113232 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73702 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73638 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74656 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6653925 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 63843 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 74719 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6653924 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63842 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820679 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43879664 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 820678 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43879657 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3983748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3980285 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4037850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52507401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4041258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52507338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3454232 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3454177 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6013524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3454232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43879664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 6013469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3454177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43879657 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3998120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3994656 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6582771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58520925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6653925 # Total number of read requests seen -system.physmem.writeReqs 820679 # Total number of write requests seen -system.physmem.cpureqs 271820 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425851200 # Total number of bytes read from memory -system.physmem.bytesWritten 52523456 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62110116 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7113296 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.data 6586178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58520807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6653924 # Total number of read requests seen +system.physmem.writeReqs 820678 # Total number of write requests seen +system.physmem.cpureqs 271841 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425851136 # Total number of bytes read from memory +system.physmem.bytesWritten 52523392 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62110052 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7113232 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11750 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 11752 # Reqs where no action is needed system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415464 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis @@ -94,7 +94,7 @@ system.physmem.perBankRdReqs::15 415324 # Tr system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50650 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis @@ -109,14 +109,14 @@ system.physmem.perBankWrReqs::14 51455 # Tr system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182878628500 # Total gap between requests +system.physmem.totGap 1182878800500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159036 # Categorize read packet sizes +system.physmem.readPktSize::6 159035 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,7 +125,7 @@ system.physmem.writePktSize::2 756836 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 63843 # categorize write packet sizes +system.physmem.writePktSize::6 63842 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,26 +134,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11750 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11752 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 6597380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6596894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 41002 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1803 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -185,7 +185,7 @@ system.physmem.wrQLenPdf::11 35682 # Wh system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see @@ -203,14 +203,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3516126974 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 123045854974 # Sum of mem lat for all requests -system.physmem.totBusLat 26615172000 # Total cycles spent in databus access -system.physmem.totBankLat 92914556000 # Total cycles spent in bank access -system.physmem.avgQLat 528.44 # Average queueing delay per request -system.physmem.avgBankLat 13964.15 # Average bank access latency per request +system.physmem.totQLat 3569461684 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 123099843684 # Sum of mem lat for all requests +system.physmem.totBusLat 26615168000 # Total cycles spent in databus access +system.physmem.totBankLat 92915214000 # Total cycles spent in bank access +system.physmem.avgQLat 536.46 # Average queueing delay per request +system.physmem.avgBankLat 13964.25 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18492.59 # Average memory access latency +system.physmem.avgMemAccLat 18500.71 # Average memory access latency system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s @@ -218,12 +218,12 @@ system.physmem.avgConsumedWrBW 6.01 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.53 # Data bus utilization in percentage system.physmem.avgRdQLen 0.10 # Average read queue length over time -system.physmem.avgWrQLen 15.12 # Average write queue length over time -system.physmem.readRowHits 6625021 # Number of row buffer hits during reads -system.physmem.writeRowHits 788582 # Number of row buffer hits during writes +system.physmem.avgWrQLen 15.10 # Average write queue length over time +system.physmem.readRowHits 6624970 # Number of row buffer hits during reads +system.physmem.writeRowHits 788587 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 96.09 # Row buffer hit rate for writes -system.physmem.avgGap 158253.02 # Average gap between requests +system.physmem.avgGap 158253.08 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -242,67 +242,67 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 68923 # number of replacements -system.l2c.tagsinuse 53039.119781 # Cycle average of tags in use -system.l2c.total_refs 1673706 # Total number of references to valid blocks. -system.l2c.sampled_refs 134114 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.479726 # Average number of references to valid blocks. +system.l2c.replacements 68922 # number of replacements +system.l2c.tagsinuse 53038.398444 # Cycle average of tags in use +system.l2c.total_refs 1676342 # Total number of references to valid blocks. +system.l2c.sampled_refs 134082 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.502364 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40183.428696 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40183.482743 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000405 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.001414 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3728.892697 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4238.506487 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3728.899373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4237.689144 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 2.742166 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2823.934351 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2061.613566 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613150 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu1.inst 2823.942801 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2061.640399 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.613151 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.056898 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064674 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064662 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.043090 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.031458 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809313 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4148 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1813 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 206316 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1906 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464180 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143508 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1247033 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571732 # number of Writeback hits -system.l2c.Writeback_hits::total 571732 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1159 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 640 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1799 # number of UpgradeReq hits +system.l2c.occ_percent::total 0.809302 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4216 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1874 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 419651 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 206094 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5524 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1914 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464156 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143505 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1246934 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571634 # number of Writeback hits +system.l2c.Writeback_hits::total 571634 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1136 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1711 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 215 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56965 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52844 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109809 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4148 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1813 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419656 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 263281 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5506 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1906 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464180 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196352 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356842 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4148 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1813 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419656 # number of overall hits -system.l2c.overall_hits::cpu0.data 263281 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5506 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1906 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464180 # number of overall hits -system.l2c.overall_hits::cpu1.data 196352 # number of overall hits -system.l2c.overall_hits::total 1356842 # number of overall hits +system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 314 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56997 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52866 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109863 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4216 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1874 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 419651 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 263091 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5524 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 196371 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356797 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4216 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1874 # number of overall hits +system.l2c.overall_hits::cpu0.inst 419651 # number of overall hits +system.l2c.overall_hits::cpu0.data 263091 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5524 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1914 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464156 # number of overall hits +system.l2c.overall_hits::cpu1.data 196371 # number of overall hits +system.l2c.overall_hits::total 1356797 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses @@ -311,168 +311,168 @@ system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 3621 # number of ReadReq misses system.l2c.ReadReq_misses::total 22264 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4676 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3594 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8270 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 474 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1038 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67114 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72101 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139215 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4681 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3591 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8272 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 561 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 470 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1031 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 67060 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72161 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139221 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74973 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74919 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 75722 # number of demand (read+write) misses -system.l2c.demand_misses::total 161479 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 75782 # number of demand (read+write) misses +system.l2c.demand_misses::total 161485 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses -system.l2c.overall_misses::cpu0.data 74973 # number of overall misses +system.l2c.overall_misses::cpu0.data 74919 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses -system.l2c.overall_misses::cpu1.data 75722 # number of overall misses -system.l2c.overall_misses::total 161479 # number of overall misses +system.l2c.overall_misses::cpu1.data 75782 # number of overall misses +system.l2c.overall_misses::total 161485 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 67500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 285133000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 404030000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 285527000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 405599500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 261135000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 212169500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1162851500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 12638997 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 11749999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24388996 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1751500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2408500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4160000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3003544975 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3416776995 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6420321970 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 259776000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 211385500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1162672000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 12888997 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 11730499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 24619496 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1705500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2384500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4090000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 2999097972 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3428190491 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6427288463 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 67500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 285133000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3407574975 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 285527000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3404697472 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 261135000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3628946495 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7583173470 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 259776000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3639575991 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7589960463 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 67500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 285133000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3407574975 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 285527000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3404697472 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 261135000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3628946495 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7583173470 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4149 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1815 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 425389 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 214175 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5510 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1906 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 469224 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 147129 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1269297 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 571732 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 571732 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5835 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4234 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10069 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 571 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1350 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 124079 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 124945 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249024 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4149 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1815 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 425389 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 338254 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5510 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1906 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 469224 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 272074 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1518321 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4149 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1815 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 425389 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 338254 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5510 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1906 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 469224 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 272074 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1518321 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001102 # miss rate for ReadReq accesses +system.l2c.overall_miss_latency::cpu1.inst 259776000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3639575991 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7589960463 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4217 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1876 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 425384 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 213953 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5528 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1914 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 469200 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 147126 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1269198 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 571634 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 571634 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5817 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4166 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9983 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1345 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 124057 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 125027 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249084 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4217 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1876 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 425384 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 338010 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5528 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1914 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 469200 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 272153 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1518282 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4217 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1876 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 425384 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 338010 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5528 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1914 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 469200 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 272153 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1518282 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001066 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013477 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036694 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036732 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024611 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017540 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801371 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848843 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.821333 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.724005 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.830123 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.768889 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.540897 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.577062 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.559043 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001102 # miss rate for demand accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024612 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017542 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.804710 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.861978 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.828609 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.722938 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826011 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.766543 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.540558 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.577163 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.558932 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001066 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.013477 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.221647 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.278314 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.106354 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001102 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu1.data 0.278454 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.106360 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001066 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.013477 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.221647 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.278314 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.106354 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.278454 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.106360 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 33750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49735.391593 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 51409.848581 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49804.116518 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 51609.555923 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51771.411578 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 58594.172880 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52230.124865 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2702.950599 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3269.337507 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2949.092624 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3105.496454 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5081.223629 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4007.707129 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44752.882782 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47388.760142 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 46118.033042 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51501.982554 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 58377.658105 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52222.062522 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2753.470840 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3266.638541 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2976.244681 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3040.106952 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5073.404255 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3967.022308 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44722.606203 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47507.524716 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 46166.084592 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 49735.391593 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 45450.695250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51771.411578 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 47924.599126 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 46960.740839 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 47001.024634 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 49735.391593 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 45450.695250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51771.411578 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 47924.599126 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 46960.740839 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 47001.024634 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,8 +481,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 63843 # number of writebacks -system.l2c.writebacks::total 63843 # number of writebacks +system.l2c.writebacks::writebacks 63842 # number of writebacks +system.l2c.writebacks::total 63842 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -497,143 +497,143 @@ system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 3621 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 22263 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4676 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3594 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8270 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 474 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1038 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67114 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72101 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139215 # number of ReadExReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4681 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3591 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8272 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 561 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 470 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1031 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67060 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 72161 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139221 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 74973 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 74919 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 75722 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 161478 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 75782 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 161484 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 74973 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 74919 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 75722 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 161478 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 75782 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 161484 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56002 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 42004 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 212317379 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 303283129 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 212718377 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 304840627 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 196008 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 197074983 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 165938649 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 878908154 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 46908094 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36050560 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 82958654 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5654558 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4769959 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10424517 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2158776151 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2496303754 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4655079905 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 195716490 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 165149154 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 878718662 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 46986078 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 35996056 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 82982134 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5623056 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4727457 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10350513 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2155048026 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2506935370 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4661983396 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 42004 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 212317379 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2462059280 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 212718377 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2459888653 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 196008 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 197074983 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2662242403 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5533988059 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 195716490 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2672084524 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5540702058 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56002 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 42004 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 212317379 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2462059280 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 212718377 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2459888653 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 196008 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 197074983 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2662242403 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5533988059 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 195716490 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2672084524 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5540702058 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 197971583 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448379609 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12452500109 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3031674 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154289730543 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166939113409 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000300750 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8208718440 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 9209019190 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154310795041 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166964298407 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000517750 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209233939 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9209751689 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 197971583 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13448680359 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13453017859 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3031674 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162498448983 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 176148132599 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162520028980 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176174050096 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036694 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036732 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024611 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017540 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801371 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848843 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.821333 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830123 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.768889 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540897 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577062 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.559043 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024612 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.804710 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.861978 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.828609 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.722938 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826011 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.766543 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540558 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577163 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.558932 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.106353 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106360 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.106353 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106360 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38590.549561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38788.729737 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45826.746479 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39478.424022 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.671086 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.762382 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.276179 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.812057 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.204641 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.887283 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32165.809682 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34622.318054 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33438.062745 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45608.714167 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39469.912501 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.615467 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.964355 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.689313 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10023.272727 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.419149 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.294859 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.117298 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34740.862377 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33486.208230 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -656,9 +656,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7072899 # DTB read hits -system.cpu0.dtb.read_misses 3762 # DTB read misses -system.cpu0.dtb.write_hits 5658444 # DTB write hits +system.cpu0.dtb.read_hits 7072907 # DTB read hits +system.cpu0.dtb.read_misses 3765 # DTB read misses +system.cpu0.dtb.write_hits 5658426 # DTB write hits system.cpu0.dtb.write_misses 809 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -666,16 +666,16 @@ system.cpu0.dtb.flush_tlb_mva_asid 1439 # Nu system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7076661 # DTB read accesses -system.cpu0.dtb.write_accesses 5659253 # DTB write accesses +system.cpu0.dtb.read_accesses 7076672 # DTB read accesses +system.cpu0.dtb.write_accesses 5659235 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12731343 # DTB hits -system.cpu0.dtb.misses 4571 # DTB misses -system.cpu0.dtb.accesses 12735914 # DTB accesses -system.cpu0.itb.inst_hits 29570664 # ITB inst hits +system.cpu0.dtb.hits 12731333 # DTB hits +system.cpu0.dtb.misses 4574 # DTB misses +system.cpu0.dtb.accesses 12735907 # DTB accesses +system.cpu0.itb.inst_hits 29570611 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -692,79 +692,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29572869 # ITB inst accesses -system.cpu0.itb.hits 29570664 # DTB hits +system.cpu0.itb.inst_accesses 29572816 # ITB inst accesses +system.cpu0.itb.hits 29570611 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29572869 # DTB accesses -system.cpu0.numCycles 2365766155 # number of cpu cycles simulated +system.cpu0.itb.accesses 29572816 # DTB accesses +system.cpu0.numCycles 2365766550 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28872728 # Number of instructions committed -system.cpu0.committedOps 37219681 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33106320 # Number of integer alu accesses +system.cpu0.committedInsts 28872677 # Number of instructions committed +system.cpu0.committedOps 37219640 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33106294 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241688 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33106320 # number of integer instructions +system.cpu0.num_func_calls 1241693 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373343 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33106294 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190095843 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36231130 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190095681 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36231150 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13399483 # number of memory refs -system.cpu0.num_load_insts 7410404 # Number of load instructions -system.cpu0.num_store_insts 5989079 # Number of store instructions -system.cpu0.num_idle_cycles 2224921697.356119 # Number of idle cycles -system.cpu0.num_busy_cycles 140844457.643881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059534 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940466 # Percentage of idle cycles +system.cpu0.num_mem_refs 13399479 # number of memory refs +system.cpu0.num_load_insts 7410420 # Number of load instructions +system.cpu0.num_store_insts 5989059 # Number of store instructions +system.cpu0.num_idle_cycles 2224930438.354119 # Number of idle cycles +system.cpu0.num_busy_cycles 140836111.645881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed -system.cpu0.icache.replacements 425421 # number of replacements +system.cpu0.kern.inst.quiesce 46695 # number of quiesce instructions executed +system.cpu0.icache.replacements 425420 # number of replacements system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use -system.cpu0.icache.total_refs 29144714 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 425933 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.425583 # Average number of references to valid blocks. +system.cpu0.icache.total_refs 29144662 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 425932 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.425622 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29144714 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29144714 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29144714 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29144714 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29144714 # number of overall hits -system.cpu0.icache.overall_hits::total 29144714 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425933 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425933 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425933 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425933 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425933 # number of overall misses -system.cpu0.icache.overall_misses::total 425933 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794506500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5794506500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5794506500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5794506500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5794506500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5794506500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570647 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29570647 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29570647 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29570647 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29570647 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29570647 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29144662 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29144662 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29144662 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29144662 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29144662 # number of overall hits +system.cpu0.icache.overall_hits::total 29144662 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425932 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425932 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425932 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425932 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425932 # number of overall misses +system.cpu0.icache.overall_misses::total 425932 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794628000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5794628000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5794628000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5794628000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5794628000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5794628000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570594 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29570594 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29570594 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29570594 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29570594 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29570594 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.014404 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014404 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014404 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.267573 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.267573 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13604.267573 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13604.267573 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.584769 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.584769 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13604.584769 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13604.584769 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,18 +773,18 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425933 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425933 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425933 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425933 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425933 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425933 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942640500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942640500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942640500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4942640500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942640500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4942640500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425932 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425932 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425932 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425932 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425932 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425932 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942764000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942764000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942764000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4942764000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942764000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4942764000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles @@ -795,98 +795,98 @@ system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014404 system.cpu0.icache.demand_mshr_miss_rate::total 0.014404 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014404 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.267573 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.267573 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.267573 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.584769 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330958 # number of replacements -system.cpu0.dcache.tagsinuse 453.838533 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12275558 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331470 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.033692 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330832 # number of replacements +system.cpu0.dcache.tagsinuse 453.835370 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12275735 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 331344 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.048309 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 453.838533 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.886403 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.886403 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6602415 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6602415 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5353315 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5353315 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149687 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149687 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11955730 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11955730 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11955730 # number of overall hits -system.cpu0.dcache.overall_hits::total 11955730 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 228156 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 228156 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141693 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141693 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9329 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9329 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7496 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7496 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369849 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369849 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369849 # number of overall misses -system.cpu0.dcache.overall_misses::total 369849 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3134416000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3134416000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4131327000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4131327000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88312000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88312000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44497000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44497000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 7265743000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7265743000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7265743000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7265743000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6830571 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6830571 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495008 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5495008 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157268 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157268 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157183 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157183 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12325579 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12325579 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12325579 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12325579 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033402 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033402 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025786 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025786 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059319 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059319 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047690 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047690 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030007 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.030007 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030007 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.030007 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13738.038886 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13738.038886 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29156.888484 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29156.888484 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9466.395112 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9466.395112 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5936.099253 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5936.099253 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19645.160593 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19645.160593 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 453.835370 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.886397 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.886397 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6602660 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6602660 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5353299 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5353299 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147927 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147927 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149680 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149680 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11955959 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11955959 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11955959 # number of overall hits +system.cpu0.dcache.overall_hits::total 11955959 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227931 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227931 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141702 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141702 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9328 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9328 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369633 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369633 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369633 # number of overall misses +system.cpu0.dcache.overall_misses::total 369633 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3133125500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3133125500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4126730000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4126730000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88286000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88286000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44416500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44416500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 7259855500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7259855500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 7259855500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7259855500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6830591 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6830591 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495001 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5495001 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157255 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157255 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157172 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157172 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12325592 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12325592 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12325592 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12325592 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033369 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033369 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025787 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025787 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059318 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059318 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047668 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047668 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029989 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029989 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029989 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029989 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13745.938464 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13745.938464 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29122.595306 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29122.595306 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9464.622642 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9464.622642 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5928.523759 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5928.523759 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19640.712545 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19640.712545 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306622 # number of writebacks -system.cpu0.dcache.writebacks::total 306622 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228156 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228156 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141693 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141693 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9329 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9329 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7493 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7493 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369849 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369849 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369849 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369849 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678104000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678104000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3847941000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3847941000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69654000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69654000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29513000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29513000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6526045000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6526045000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6526045000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6526045000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559793500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559793500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128518500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128518500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688312000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688312000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033402 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025786 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025786 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059319 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059319 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047671 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047671 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030007 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11738.038886 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11738.038886 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27156.888484 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27156.888484 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7466.395112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7466.395112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3938.742827 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3938.742827 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306514 # number of writebacks +system.cpu0.dcache.writebacks::total 306514 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227931 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227931 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141702 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141702 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9328 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9328 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369633 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369633 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369633 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369633 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2677263500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2677263500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3843326000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3843326000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29442500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29442500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6520589500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6520589500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6520589500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6520589500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13560077000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13560077000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128521500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128521500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688598500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688598500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033369 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025787 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025787 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059318 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059318 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047648 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047648 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029989 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029989 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.938464 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.938464 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27122.595306 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27122.595306 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7464.622642 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7464.622642 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3931.432768 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3931.432768 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,26 +964,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8308478 # DTB read hits -system.cpu1.dtb.read_misses 3644 # DTB read misses -system.cpu1.dtb.write_hits 5825596 # DTB write hits -system.cpu1.dtb.write_misses 1434 # DTB write misses +system.cpu1.dtb.read_hits 8308581 # DTB read hits +system.cpu1.dtb.read_misses 3643 # DTB read misses +system.cpu1.dtb.write_hits 5825594 # DTB write hits +system.cpu1.dtb.write_misses 1436 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8312122 # DTB read accesses +system.cpu1.dtb.read_accesses 8312224 # DTB read accesses system.cpu1.dtb.write_accesses 5827030 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14134074 # DTB hits -system.cpu1.dtb.misses 5078 # DTB misses -system.cpu1.dtb.accesses 14139152 # DTB accesses -system.cpu1.itb.inst_hits 33188345 # ITB inst hits +system.cpu1.dtb.hits 14134175 # DTB hits +system.cpu1.dtb.misses 5079 # DTB misses +system.cpu1.dtb.accesses 14139254 # DTB accesses +system.cpu1.itb.inst_hits 33188757 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1000,79 +1000,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33190516 # ITB inst accesses -system.cpu1.itb.hits 33188345 # DTB hits +system.cpu1.itb.inst_accesses 33190928 # ITB inst accesses +system.cpu1.itb.hits 33188757 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33190516 # DTB accesses -system.cpu1.numCycles 2364324255 # number of cpu cycles simulated +system.cpu1.itb.accesses 33190928 # DTB accesses +system.cpu1.numCycles 2364324282 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32577871 # Number of instructions committed -system.cpu1.committedOps 41082259 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37307050 # Number of integer alu accesses +system.cpu1.committedInsts 32578272 # Number of instructions committed +system.cpu1.committedOps 41082658 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37307259 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses system.cpu1.num_func_calls 961975 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732476 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37307050 # number of integer instructions +system.cpu1.num_conditional_control_insts 3732574 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37307259 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213626787 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39450306 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213628675 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39450611 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14671800 # number of memory refs -system.cpu1.num_load_insts 8630367 # Number of load instructions -system.cpu1.num_store_insts 6041433 # Number of store instructions -system.cpu1.num_idle_cycles 1868325738.966939 # Number of idle cycles -system.cpu1.num_busy_cycles 495998516.033061 # Number of busy cycles -system.cpu1.not_idle_fraction 0.209784 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.790216 # Percentage of idle cycles +system.cpu1.num_mem_refs 14671912 # number of memory refs +system.cpu1.num_load_insts 8630468 # Number of load instructions +system.cpu1.num_store_insts 6041444 # Number of store instructions +system.cpu1.num_idle_cycles 1868307269.461274 # Number of idle cycles +system.cpu1.num_busy_cycles 496017012.538726 # Number of busy cycles +system.cpu1.not_idle_fraction 0.209792 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.790208 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43884 # number of quiesce instructions executed -system.cpu1.icache.replacements 469230 # number of replacements -system.cpu1.icache.tagsinuse 478.783120 # Cycle average of tags in use -system.cpu1.icache.total_refs 32718599 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469742 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.652275 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 43897 # number of quiesce instructions executed +system.cpu1.icache.replacements 469210 # number of replacements +system.cpu1.icache.tagsinuse 478.783126 # Cycle average of tags in use +system.cpu1.icache.total_refs 32719031 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 469722 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.656160 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.783120 # Average occupied blocks per requestor +system.cpu1.icache.occ_blocks::cpu1.inst 478.783126 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32718599 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32718599 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32718599 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32718599 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32718599 # number of overall hits -system.cpu1.icache.overall_hits::total 32718599 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469742 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469742 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469742 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469742 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469742 # number of overall misses -system.cpu1.icache.overall_misses::total 469742 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6348514000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6348514000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6348514000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6348514000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6348514000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6348514000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188341 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33188341 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33188341 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33188341 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33188341 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33188341 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014154 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014154 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014154 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014154 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014154 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014154 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13514.895411 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13514.895411 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13514.895411 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13514.895411 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13514.895411 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13514.895411 # average overall miss latency +system.cpu1.icache.ReadReq_hits::cpu1.inst 32719031 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32719031 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32719031 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32719031 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32719031 # number of overall hits +system.cpu1.icache.overall_hits::total 32719031 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 469722 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 469722 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 469722 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 469722 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 469722 # number of overall misses +system.cpu1.icache.overall_misses::total 469722 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6346616500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6346616500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6346616500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6346616500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6346616500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6346616500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188753 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33188753 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33188753 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33188753 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33188753 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33188753 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13511.431230 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13511.431230 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13511.431230 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13511.431230 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,120 +1081,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469742 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 469742 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 469742 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 469742 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 469742 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 469742 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5409030000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5409030000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5409030000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5409030000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5409030000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5409030000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469722 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 469722 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 469722 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 469722 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 469722 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 469722 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5407172500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5407172500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5407172500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5407172500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5407172500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5407172500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014154 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014154 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014154 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11514.895411 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11514.895411 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11514.895411 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11511.431230 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 291659 # number of replacements -system.cpu1.dcache.tagsinuse 472.058793 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11957529 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292006 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.949600 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 291698 # number of replacements +system.cpu1.dcache.tagsinuse 472.096881 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11957476 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 292067 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.940866 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 83625331000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 472.058793 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.921990 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.921990 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6944275 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6944275 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4825543 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4825543 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81753 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81753 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82700 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82700 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11769818 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11769818 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11769818 # number of overall hits -system.cpu1.dcache.overall_hits::total 11769818 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170271 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170271 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 149767 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 149767 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11060 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11060 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10038 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10038 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320038 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320038 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320038 # number of overall misses -system.cpu1.dcache.overall_misses::total 320038 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2152137500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2152137500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4507881000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4507881000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91883000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 91883000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51759500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 51759500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6660018500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6660018500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6660018500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6660018500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114546 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7114546 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975310 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4975310 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92813 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 92813 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92738 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92738 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12089856 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12089856 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12089856 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12089856 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023933 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030102 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030102 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119164 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119164 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108240 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108240 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026472 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026472 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026472 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026472 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12639.483529 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12639.483529 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30099.294237 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30099.294237 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8307.685353 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8307.685353 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5156.355848 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5156.355848 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20810.086615 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20810.086615 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 472.096881 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.922064 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.922064 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6944335 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6944335 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4825513 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4825513 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81763 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81763 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82710 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82710 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11769848 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11769848 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11769848 # number of overall hits +system.cpu1.dcache.overall_hits::total 11769848 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170295 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170295 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 149789 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 149789 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11069 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11069 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10034 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10034 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320084 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320084 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320084 # number of overall misses +system.cpu1.dcache.overall_misses::total 320084 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2151167000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2151167000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4518557500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4518557500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92001000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 92001000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51654000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 51654000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6669724500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6669724500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6669724500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6669724500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114630 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7114630 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975302 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4975302 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92832 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92832 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92744 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92744 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12089932 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12089932 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12089932 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12089932 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023936 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023936 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030107 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030107 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119237 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119237 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108190 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108190 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026475 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026475 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026475 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026475 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12632.003288 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12632.003288 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30166.150385 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30166.150385 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8311.590930 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8311.590930 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5147.897150 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5147.897150 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20837.419240 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20837.419240 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1203,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265110 # number of writebacks -system.cpu1.dcache.writebacks::total 265110 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170271 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170271 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149767 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149767 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11060 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11060 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10034 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10034 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320038 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320038 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320038 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320038 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1811595500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1811595500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4208347000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4208347000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69763000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69763000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31693500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31693500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 265120 # number of writebacks +system.cpu1.dcache.writebacks::total 265120 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170295 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170295 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149789 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149789 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11069 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11069 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10028 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10028 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320084 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320084 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320084 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320084 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1810577000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1810577000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4218979500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4218979500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69863000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69863000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31600000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6019942500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6019942500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6019942500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6019942500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168625975500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168625975500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666930000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666930000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186292905500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186292905500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023933 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023933 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030102 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030102 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119164 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119164 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108197 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108197 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026472 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026472 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10639.483529 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10639.483529 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28099.294237 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28099.294237 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6307.685353 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6307.685353 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3158.610724 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3158.610724 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6029556500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6029556500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6029556500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6029556500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168626695000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168626695000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666887000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666887000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186293582000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186293582000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023936 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023936 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030107 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030107 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119237 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119237 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108126 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108126 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026475 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026475 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10632.003288 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10632.003288 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28166.150385 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28166.150385 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6311.590930 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6311.590930 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3151.176705 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3151.176705 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446709885400 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 446709885400 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446709885400 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 446709885400 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446757532781 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 446757532781 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446757532781 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 446757532781 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index e97027568..50e9a8afa 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.603636 # Nu sim_ticks 2603636076000 # Number of ticks simulated final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 485506 # Simulator instruction rate (inst/s) -host_op_rate 617798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20998999798 # Simulator tick rate (ticks/s) +host_inst_rate 264193 # Simulator instruction rate (inst/s) +host_op_rate 336182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11426847777 # Simulator tick rate (ticks/s) host_mem_usage 395692 # Number of bytes of host memory used -host_seconds 123.99 # Real time elapsed on the host +host_seconds 227.85 # Real time elapsed on the host sim_insts 60197128 # Number of instructions simulated sim_ops 76599899 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory @@ -120,23 +120,23 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 15419651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -186,14 +186,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3755940486 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 281915228486 # Sum of mem lat for all requests +system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests system.physmem.totBusLat 61975012000 # Total cycles spent in databus access -system.physmem.totBankLat 216184276000 # Total cycles spent in bank access -system.physmem.avgQLat 242.42 # Average queueing delay per request -system.physmem.avgBankLat 13953.00 # Average bank access latency per request +system.physmem.totBankLat 216185438000 # Total cycles spent in bank access +system.physmem.avgQLat 242.04 # Average queueing delay per request +system.physmem.avgBankLat 13953.07 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18195.41 # Average memory access latency +system.physmem.avgMemAccLat 18195.12 # Average memory access latency system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s @@ -202,7 +202,7 @@ system.physmem.peakBW 16000.00 # Th system.physmem.busUtil 2.51 # Data bus utilization in percentage system.physmem.avgRdQLen 0.11 # Average read queue length over time system.physmem.avgWrQLen 12.38 # Average write queue length over time -system.physmem.readRowHits 15449465 # Number of row buffer hits during reads +system.physmem.readRowHits 15449450 # Number of row buffer hits during reads system.physmem.writeRowHits 784611 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes @@ -285,39 +285,39 @@ system.cpu.num_fp_register_writes 2780 # nu system.cpu.num_mem_refs 27393681 # number of memory refs system.cpu.num_load_insts 15659530 # Number of load instructions system.cpu.num_store_insts 11734151 # Number of store instructions -system.cpu.num_idle_cycles 4579082960.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628189191.423759 # Number of busy cycles +system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles system.cpu.idle_fraction 0.879363 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855498 # number of replacements +system.cpu.icache.replacements 855500 # number of replacements system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use -system.cpu.icache.total_refs 60635058 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856010 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.834521 # Average number of references to valid blocks. +system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635058 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635058 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635058 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635058 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635058 # number of overall hits -system.cpu.icache.overall_hits::total 60635058 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856010 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856010 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856010 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856010 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856010 # number of overall misses -system.cpu.icache.overall_misses::total 856010 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11542526000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11542526000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11542526000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11542526000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11542526000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11542526000 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 60635056 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635056 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635056 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635056 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635056 # number of overall hits +system.cpu.icache.overall_hits::total 60635056 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856012 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856012 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856012 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856012 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856012 # number of overall misses +system.cpu.icache.overall_misses::total 856012 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11543876000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11543876000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11543876000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11543876000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11543876000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11543876000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses @@ -330,12 +330,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13484.101821 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13484.101821 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13484.101821 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13484.101821 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13485.647397 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13485.647397 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13485.647397 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13485.647397 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,18 +344,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856010 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856010 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856010 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856010 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856010 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856010 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9830506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9830506000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9830506000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9830506000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9830506000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9830506000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856012 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856012 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856012 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856012 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856012 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856012 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9831852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9831852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831852000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9831852000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles @@ -366,12 +366,12 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11484.101821 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11484.101821 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11485.647397 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11485.647397 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency @@ -408,16 +408,16 @@ system.cpu.dcache.demand_misses::cpu.data 619265 # n system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses system.cpu.dcache.overall_misses::total 619265 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5206335000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5206335000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061427000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8061427000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154571000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 154571000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13267762000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13267762000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13267762000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13267762000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205933000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5205933000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061519000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8061519000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154593000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 154593000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13267452000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13267452000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13267452000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13267452000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses) @@ -440,16 +440,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14118.376844 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14118.376844 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.088375 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.088375 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13558.859649 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13558.859649 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21425.015139 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21425.015139 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14117.286713 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14117.286713 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.455637 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.455637 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.789474 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.789474 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21424.514545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21424.514545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21424.514545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,22 +470,22 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 619265 system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468809000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468809000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560423000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560423000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131771000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131771000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12029232000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12029232000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12029232000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12029232000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182087740500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182087740500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708092000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708092000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200795832500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200795832500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468407000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468407000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560515000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560515000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131793000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131793000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028922000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12028922000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028922000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12028922000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182088074500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182088074500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708050000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708050000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200796124500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200796124500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses @@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12118.376844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12118.376844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.088375 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.088375 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11558.859649 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11558.859649 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12117.286713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12117.286713 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.455637 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.455637 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11560.789474 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11560.789474 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19424.514545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19424.514545 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -514,16 +514,16 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 61906 # number of replacements -system.cpu.l2cache.tagsinuse 50893.840844 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1682731 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 50893.840705 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1682733 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.219871 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 13.219887 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37868.665500 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 37868.665520 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6995.476724 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6025.811636 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 6995.476581 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6025.811619 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -532,9 +532,9 @@ system.cpu.l2cache.occ_percent::cpu.data 0.091947 # Av system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 843786 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 843788 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226341 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226343 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits @@ -543,14 +543,14 @@ system.cpu.l2cache.ReadExReq_hits::cpu.data 114418 # system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 843786 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 843788 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340759 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1340761 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 843786 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 843788 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340759 # number of overall hits +system.cpu.l2cache.overall_hits::total 1340761 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses @@ -572,28 +572,28 @@ system.cpu.l2cache.overall_misses::cpu.data 143044 # system.cpu.l2cache.overall_misses::total 153651 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 535011000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 517367000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1052802500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 536335000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 516987000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1053746500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102272500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6102272500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102367500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6102367500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 535011000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6619639500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7155075000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 536335000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6619354500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7156114000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 535011000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6619639500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7155075000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 536335000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6619354500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7156114000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8707 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854385 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 854387 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 380163 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1246806 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1246808 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 596013 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 596013 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) @@ -602,14 +602,14 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 247604 system.cpu.l2cache.ReadExReq_accesses::total 247604 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8707 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854385 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 854387 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 627767 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494410 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494412 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8707 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854385 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 854387 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 627767 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494410 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494412 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012405 # miss rate for ReadReq accesses @@ -631,23 +631,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.227862 system.cpu.l2cache.overall_miss_rate::total 0.102817 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50477.497877 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52481.943599 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51444.050818 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50602.415322 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52443.396226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51490.178353 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.167131 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.167131 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45817.672278 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45817.672278 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45818.385566 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45818.385566 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50477.497877 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46276.946254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46567.057813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46573.819891 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50477.497877 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46276.946254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46567.057813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50602.415322 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.953860 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46573.819891 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -679,31 +679,31 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 143044 system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 397346579 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389320096 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 786988691 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28812314 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28812314 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371883715 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371883715 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398671075 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 388940100 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 787933191 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28807316 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28807316 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371975723 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371975723 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 397346579 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4761203811 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5158872406 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398671075 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4760915823 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5159908914 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 397346579 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4761203811 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5158872406 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398671075 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4760915823 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5159908914 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688827565 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166886294116 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9174375606 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9174375606 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166694484565 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166891951116 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175103106 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175103106 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175863203171 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176060669722 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175869587671 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176067054222 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses @@ -725,23 +725,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37489.063025 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39492.807466 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38455.347716 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.142758 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.142758 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32825.399929 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32825.399929 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37614.027267 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39454.260499 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38501.499682 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.402507 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.402507 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32826.090753 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32826.090753 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37614.027267 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33582.006717 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1052670853165 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1052670853165 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 11970e7f1..b63186d21 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.191113 # Nu sim_ticks 5191112864000 # Number of ticks simulated final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 414932 # Simulator instruction rate (inst/s) -host_op_rate 799857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16795720800 # Simulator tick rate (ticks/s) -host_mem_usage 384032 # Number of bytes of host memory used -host_seconds 309.07 # Real time elapsed on the host +host_inst_rate 1106680 # Simulator instruction rate (inst/s) +host_op_rate 2133324 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44796411922 # Simulator tick rate (ticks/s) +host_mem_usage 384016 # Number of bytes of host memory used +host_seconds 115.88 # Real time elapsed on the host sim_insts 128244614 # Number of instructions simulated -sim_ops 247214605 # Number of ops (including micro ops) simulated +sim_ops 247214600 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory @@ -179,14 +179,14 @@ system.physmem.wrQLenPdf::29 1 # Wh system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2876260269 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6438486269 # Sum of mem lat for all requests +system.physmem.totQLat 2876233269 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6438459269 # Sum of mem lat for all requests system.physmem.totBusLat 793712000 # Total cycles spent in databus access system.physmem.totBankLat 2768514000 # Total cycles spent in bank access -system.physmem.avgQLat 14495.23 # Average queueing delay per request +system.physmem.avgQLat 14495.10 # Average queueing delay per request system.physmem.avgBankLat 13952.23 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32447.47 # Average memory access latency +system.physmem.avgMemAccLat 32447.33 # Average memory access latency system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s @@ -308,71 +308,71 @@ system.cpu.numCycles 10382225728 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 128244614 # Number of instructions committed -system.cpu.committedOps 247214605 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231949866 # Number of integer alu accesses +system.cpu.committedOps 247214600 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231949861 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23149724 # number of instructions that are conditional controls -system.cpu.num_int_insts 231949866 # number of integer instructions +system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls +system.cpu.num_int_insts 231949861 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566905537 # number of times the integer registers were read -system.cpu.num_int_register_writes 293156479 # number of times the integer registers were written +system.cpu.num_int_register_reads 566905512 # number of times the integer registers were read +system.cpu.num_int_register_writes 293156466 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 22227093 # number of memory refs system.cpu.num_load_insts 13866667 # Number of load instructions system.cpu.num_store_insts 8360426 # Number of store instructions -system.cpu.num_idle_cycles 9781583042.374115 # Number of idle cycles -system.cpu.num_busy_cycles 600642685.625884 # Number of busy cycles +system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles system.cpu.idle_fraction 0.942147 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.icache.replacements 790930 # number of replacements system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use -system.cpu.icache.total_refs 144455336 # Total number of references to valid blocks. +system.cpu.icache.total_refs 144455339 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.521696 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 182.521700 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144455336 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144455336 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144455336 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144455336 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144455336 # number of overall hits -system.cpu.icache.overall_hits::total 144455336 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 144455339 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144455339 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144455339 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144455339 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144455339 # number of overall hits +system.cpu.icache.overall_hits::total 144455339 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses system.cpu.icache.overall_misses::total 791449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871283000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10871283000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10871283000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10871283000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10871283000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10871283000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145246785 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145246785 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145246785 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145246785 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145246785 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145246785 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871281000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10871281000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10871281000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145246788 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145246788 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145246788 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145246788 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145246788 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145246788 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.923603 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13735.923603 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.923603 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13735.923603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.923603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13735.923603 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.921076 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13735.921076 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13735.921076 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13735.921076 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,24 +387,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 791449 system.cpu.icache.demand_mshr_misses::total 791449 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 791449 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 791449 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9288385000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9288385000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9288385000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9288385000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9288385000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9288385000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9288383000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9288383000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9288383000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9288383000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9288383000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9288383000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.923603 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.923603 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11735.923603 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11735.923603 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11735.923603 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11735.923603 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.921076 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.921076 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11735.921076 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11735.921076 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11735.921076 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11735.921076 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3663 # number of replacements system.cpu.itb_walker_cache.tagsinuse 3.069768 # Cycle average of tags in use @@ -570,39 +570,39 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8766.151838 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1620900 # number of replacements +system.cpu.dcache.replacements 1620901 # number of replacements system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use -system.cpu.dcache.total_refs 20018689 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621412 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.346454 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20018688 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621413 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.346446 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11981581 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11981581 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20016507 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20016507 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20016507 # number of overall hits -system.cpu.dcache.overall_hits::total 20016507 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308144 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308144 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 20016506 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20016506 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20016506 # number of overall hits +system.cpu.dcache.overall_hits::total 20016506 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308145 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308145 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 315486 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623630 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623630 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623630 # number of overall misses -system.cpu.dcache.overall_misses::total 1623630 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313652000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18313652000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702722500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8702722500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27016374500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27016374500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27016374500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27016374500 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 1623631 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623631 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623631 # number of overall misses +system.cpu.dcache.overall_misses::total 1623631 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313644000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18313644000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702717500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8702717500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27016361500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27016361500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27016361500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27016361500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses) @@ -619,14 +619,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.075029 system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.721743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.721743 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.130560 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.130560 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.489600 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16639.489600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.489600 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16639.489600 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.704926 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.704926 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.114712 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.114712 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16639.471345 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16639.471345 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,30 +635,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538027 # number of writebacks -system.cpu.dcache.writebacks::total 1538027 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308144 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1308144 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 1538028 # number of writebacks +system.cpu.dcache.writebacks::total 1538028 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308145 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308145 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 315486 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1623630 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1623630 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1623630 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1623630 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697364000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697364000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769114500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23769114500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769114500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23769114500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1623631 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1623631 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1623631 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1623631 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697354000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697354000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071745500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071745500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769099500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23769099500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769099500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23769099500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469669500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469669500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616845500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616845500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469978500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469978500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96617154500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96617154500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098433 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098433 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037781 # mshr miss rate for WriteReq accesses @@ -667,14 +667,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075029 system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.721743 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.721743 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.130560 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.130560 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.489600 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.489600 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.489600 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.489600 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.704926 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.704926 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -683,14 +683,14 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 87015 # number of replacements -system.cpu.l2cache.tagsinuse 64709.520699 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3488529 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 64709.520704 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3488531 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 151765 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.986387 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 22.986400 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50328.696687 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 50328.696692 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140121 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3391.684310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3391.684309 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 10988.999582 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.767955 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy @@ -700,10 +700,10 @@ system.cpu.l2cache.occ_percent::total 0.987389 # Av system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6912 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3076 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 778529 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1278876 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2067393 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1542258 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1542258 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1278877 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2067394 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1542259 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1542259 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 324 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 324 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 199770 # number of ReadExReq hits @@ -711,13 +711,13 @@ system.cpu.l2cache.ReadExReq_hits::total 199770 # nu system.cpu.l2cache.demand_hits::cpu.dtb.walker 6912 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3076 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 778529 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1478646 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2267163 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1478647 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2267164 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6912 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3076 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 778529 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1478646 # number of overall hits -system.cpu.l2cache.overall_hits::total 2267163 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1478647 # number of overall hits +system.cpu.l2cache.overall_hits::total 2267164 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 12907 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 28433 # number of ReadReq misses @@ -735,28 +735,28 @@ system.cpu.l2cache.overall_misses::cpu.inst 12907 # system.cpu.l2cache.overall_misses::cpu.data 141963 # number of overall misses system.cpu.l2cache.overall_misses::total 154875 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711633000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599623500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2311601500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711631000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599602500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2311578500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16623000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 16623000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5723748500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5723748500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5723743500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5723743500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 711633000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7323372000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8035350000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 711631000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7323346000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8035322000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 711633000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7323372000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8035350000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 711631000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7323346000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8035322000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6912 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3081 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 791436 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307309 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108738 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1542258 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1542258 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307310 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108739 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1542259 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1542259 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1664 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 313300 # number of ReadExReq accesses(hits+misses) @@ -764,13 +764,13 @@ system.cpu.l2cache.ReadExReq_accesses::total 313300 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6912 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3081 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 791436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1620609 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422038 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1620610 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2422039 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6912 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3081 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 791436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1620609 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422038 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1620610 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422039 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001623 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016308 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021749 # miss rate for ReadReq accesses @@ -781,28 +781,28 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362368 system.cpu.l2cache.ReadExReq_miss_rate::total 0.362368 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001623 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016308 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087599 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087598 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.063944 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001623 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016308 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087599 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087598 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.063944 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.430387 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56259.399290 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 55910.061676 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.275432 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.660711 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.505382 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.176341 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.176341 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.132300 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.132300 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.430387 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.483802 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51882.808717 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51882.627926 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.430387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.483802 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51882.808717 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51882.627926 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -830,27 +830,27 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 12907 system.cpu.l2cache.overall_mshr_misses::cpu.data 141963 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544175395 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1231005255 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775460660 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544173395 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230984255 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775437660 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249338352 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249338352 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249333352 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249333352 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280010 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544175395 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480343607 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6024799012 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544173395 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480317607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6024771012 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280010 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544175395 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480343607 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6024799012 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587770000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587770000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305910000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305910000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893680000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893680000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544173395 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480317607 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6024771012 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86592298500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86592298500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2307004500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2307004500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88899303000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88899303000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021749 # mshr miss rate for ReadReq accesses @@ -861,28 +861,28 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362368 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362368 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087599 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.063944 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087599 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.260944 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.947948 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.572500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.105989 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.209369 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.016205 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.211239 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.211239 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.167198 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.260944 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38604.027859 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38901.042854 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.260944 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38604.027859 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.042854 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |