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authorGabe Black <gblack@eecs.umich.edu>2009-02-01 17:02:16 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-01 17:02:16 -0800
commitd824af340ec98a9d7ac34a3c358666191df1f83f (patch)
tree4e5a3b050c54b0a76e4487a3490c4c3ecb176215 /tests/quick
parent7b585114704532133c3aed01847fa534167018b3 (diff)
downloadgem5-d824af340ec98a9d7ac34a3c358666191df1f83f.tar.xz
X86: Update stats now that the micropc isn't always reset on faults.
Diffstat (limited to 'tests/quick')
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-atomic/simout14
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt16
-rwxr-xr-xtests/quick/00.hello/ref/x86/linux/simple-timing/simout14
-rw-r--r--tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt50
4 files changed, 47 insertions, 47 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 7fa8be29e..66f32751d 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 5 2008 23:03:02
-M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
-M5 commit date Wed Nov 05 16:19:17 2008 -0500
-M5 started Nov 6 2008 00:18:22
-M5 executing on zizzer
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-atomic
+M5 compiled Dec 26 2008 18:29:56
+M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
+M5 commit date Fri Dec 26 18:25:21 2008 -0800
+M5 started Dec 26 2008 18:30:07
+M5 executing on fajita
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 5518000 because target called exit()
+Exiting @ tick 5513500 because target called exit()
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 3c3c458ce..2ee3e5703 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,17 +1,17 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 557395 # Simulator instruction rate (inst/s)
-host_mem_usage 190704 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 320851262 # Simulator tick rate (ticks/s)
+host_inst_rate 5132 # Simulator instruction rate (inst/s)
+host_mem_usage 192872 # Number of bytes of host memory used
+host_seconds 1.85 # Real time elapsed on the host
+host_tick_rate 2983162 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 9493 # Number of instructions simulated
+sim_insts 9484 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
-sim_ticks 5518000 # Number of ticks simulated
+sim_ticks 5513500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 11037 # number of cpu cycles simulated
-system.cpu.num_insts 9493 # Number of instructions executed
+system.cpu.numCycles 11028 # number of cpu cycles simulated
+system.cpu.num_insts 9484 # Number of instructions executed
system.cpu.num_refs 2003 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index 9c811f04f..e9fb59225 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 7 2008 03:21:37
-M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5
-M5 commit date Thu Nov 06 23:13:50 2008 -0800
-M5 started Nov 8 2008 00:19:20
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/00.hello/x86/linux/simple-timing
+M5 compiled Dec 26 2008 18:29:56
+M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
+M5 commit date Fri Dec 26 18:25:21 2008 -0800
+M5 started Dec 26 2008 19:57:21
+M5 executing on fajita
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 33851000 because target called exit()
+Exiting @ tick 33842000 because target called exit()
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index cb9de2cde..4bf18211b 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 106773 # Simulator instruction rate (inst/s)
-host_mem_usage 197592 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 379942758 # Simulator tick rate (ticks/s)
+host_inst_rate 494241 # Simulator instruction rate (inst/s)
+host_mem_usage 200332 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1743803782 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 9493 # Number of instructions simulated
+sim_insts 9484 # Number of instructions simulated
sim_seconds 0.000034 # Number of seconds simulated
-sim_ticks 33851000 # Number of ticks simulated
+sim_ticks 33842000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
@@ -76,53 +76,53 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 81.582554 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 81.592815 # Cycle average of tags in use
system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_accesses 11007 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses 10998 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 10779 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits 10770 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.020714 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate 0.020731 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.020714 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate 0.020731 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 47.276316 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 47.236842 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 11007 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 10998 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
-system.cpu.icache.demand_hits 10779 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 10770 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.020714 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate 0.020731 # miss rate for demand accesses
system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.020714 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate 0.020731 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 11007 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 10998 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 10779 # number of overall hits
+system.cpu.icache.overall_hits 10770 # number of overall hits
system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.020714 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate 0.020731 # miss rate for overall accesses
system.cpu.icache.overall_misses 228 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.020714 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate 0.020731 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@@ -138,8 +138,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 107.509501 # Cycle average of tags in use
-system.cpu.icache.total_refs 10779 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 107.523643 # Cycle average of tags in use
+system.cpu.icache.total_refs 10770 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
@@ -219,13 +219,13 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 129.102217 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 129.119087 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 67702 # number of cpu cycles simulated
-system.cpu.num_insts 9493 # Number of instructions executed
+system.cpu.numCycles 67684 # number of cpu cycles simulated
+system.cpu.num_insts 9484 # Number of instructions executed
system.cpu.num_refs 2003 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls