diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-03-07 14:30:55 -0800 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-03-07 14:30:55 -0800 |
| commit | 5cf060576623f3681b497c46934fb4fe6f8853a6 (patch) | |
| tree | e9b005046f2118e537528178da5f935dc55dc5c1 /tests/quick | |
| parent | ac7bda0212a22d86d9e24665998f294b96869680 (diff) | |
| download | gem5-5cf060576623f3681b497c46934fb4fe6f8853a6.tar.xz | |
tests: update tests because of changes in stat names and in the stats package
Diffstat (limited to 'tests/quick')
8 files changed, 292 insertions, 268 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 0d9f81ac8..f448ee025 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:22:12 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:22:19 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index b0c4635e4..21437f2a4 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,43 +1,41 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 806 # Number of BTB hits -global.BPredUnit.BTBLookups 1937 # Number of BTB lookups -global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1370 # Number of conditional branches predicted -global.BPredUnit.lookups 2263 # Number of BP lookups -global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. -host_inst_rate 68343 # Simulator instruction rate (inst/s) -host_mem_usage 200684 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 133183507 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1266 # Number of stores inserted to the mem dependence unit. +host_inst_rate 83921 # Simulator instruction rate (inst/s) +host_mem_usage 202572 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 163392144 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated sim_ticks 12474500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 806 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1370 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2263 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 12416 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 9513 7661.89% - 1 1627 1310.41% - 2 488 393.04% - 3 267 215.05% - 4 153 123.23% - 5 104 83.76% - 6 96 77.32% - 7 53 42.69% - 8 115 92.62% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 12416 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 9513 76.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 153 1.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 115 0.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12416 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.515706 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.304935 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -147,21 +145,23 @@ system.cpu.fetch.branchRate 0.090701 # Nu system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 13314 -system.cpu.fetch.rateDist.min_value 0 - 0 10844 8144.81% - 1 252 189.27% - 2 238 178.76% - 3 230 172.75% - 4 272 204.30% - 5 162 121.68% - 6 232 174.25% - 7 129 96.89% - 8 955 717.29% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 13314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 10844 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 252 1.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 238 1.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 230 1.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 272 2.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 162 1.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 232 1.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 129 0.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 955 7.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 13314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.995268 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.362110 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency @@ -296,21 +296,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 13314 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 9113 6844.67% - 1 1716 1288.87% - 2 1071 804.42% - 3 725 544.54% - 4 355 266.64% - 5 172 129.19% - 6 115 86.38% - 7 34 25.54% - 8 13 9.76% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% +system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 13314 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued @@ -394,6 +396,10 @@ system.cpu.l2cache.tagsinuse 214.901533 # Cy system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 24950 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index d373e353b..038644e5f 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:22:12 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:16:36 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index af633c5e8..14b605eaa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,43 +1,41 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 198 # Number of BTB hits -global.BPredUnit.BTBLookups 684 # Number of BTB lookups -global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 447 # Number of conditional branches predicted -global.BPredUnit.lookups 859 # Number of BP lookups -global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. -host_inst_rate 22600 # Simulator instruction rate (inst/s) -host_mem_usage 199684 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 67889683 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit. +host_inst_rate 39458 # Simulator instruction rate (inst/s) +host_mem_usage 201572 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 118256203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated sim_ticks 7183000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 198 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 684 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 447 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 859 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6196 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 5239 8455.46% - 1 263 424.47% - 2 334 539.06% - 3 134 216.27% - 4 73 117.82% - 5 63 101.68% - 6 32 51.65% - 7 20 32.28% - 8 38 61.33% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 6196 +system.cpu.commit.COM:committed_per_cycle::min_value 0 +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% +system.cpu.commit.COM:committed_per_cycle::0-1 5239 84.55% +system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% +system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% +system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% +system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% +system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% +system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% +system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% +system.cpu.commit.COM:committed_per_cycle::8 38 0.61% +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% +system.cpu.commit.COM:committed_per_cycle::total 6196 +system.cpu.commit.COM:committed_per_cycle::max_value 8 +system.cpu.commit.COM:committed_per_cycle::mean 0.415752 +system.cpu.commit.COM:committed_per_cycle::stdev 1.208059 system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -147,21 +145,23 @@ system.cpu.fetch.branchRate 0.059790 # Nu system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6528 -system.cpu.fetch.rateDist.min_value 0 - 0 5595 8570.77% - 1 36 55.15% - 2 100 153.19% - 3 69 105.70% - 4 130 199.14% - 5 72 110.29% - 6 45 68.93% - 7 48 73.53% - 8 433 663.30% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 6528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 5595 85.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 36 0.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 100 1.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 69 1.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 130 1.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 72 1.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 45 0.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 48 0.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 433 6.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 6528 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.826134 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.219931 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency @@ -296,21 +296,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6528 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 5051 7737.44% - 1 569 871.63% - 2 331 507.05% - 3 253 387.56% - 4 172 263.48% - 5 97 148.59% - 6 39 59.74% - 7 11 16.85% - 8 5 7.66% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% +system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 6528 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued @@ -393,6 +395,10 @@ system.cpu.l2cache.tagsinuse 110.762790 # Cy system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 738 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 411 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 14367 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 73f0d5969..7101807df 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:22:12 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:23:16 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index c9242b886..783867939 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,29 +1,21 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 916 # Number of BTB hits -global.BPredUnit.BTBLookups 4733 # Number of BTB lookups -global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 3153 # Number of conditional branches predicted -global.BPredUnit.lookups 5548 # Number of BP lookups -global.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. -host_inst_rate 67823 # Simulator instruction rate (inst/s) -host_mem_usage 201212 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 75589135 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 58 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 32 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1282 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1303 # Number of stores inserted to the mem dependence unit. +host_inst_rate 106034 # Simulator instruction rate (inst/s) +host_mem_usage 203088 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 118060043 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated sim_ticks 14251500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 4733 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 3153 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5548 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 2102 # Number of branches committed system.cpu.commit.COM:branches_0 1051 # Number of branches committed system.cpu.commit.COM:branches_1 1051 # Number of branches committed @@ -31,21 +23,23 @@ system.cpu.commit.COM:bw_lim_events 122 # nu system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 22837 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 16880 7391.51% - 1 3016 1320.66% - 2 1386 606.91% - 3 576 252.22% - 4 326 142.75% - 5 268 117.35% - 6 170 74.44% - 7 93 40.72% - 8 122 53.42% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 22837 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 16880 73.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 3016 13.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1386 6.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 576 2.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 326 1.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 268 1.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 170 0.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 93 0.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 122 0.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 22837 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.560800 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.272250 # Number of insts commited each cycle system.cpu.commit.COM:count 12807 # Number of instructions committed system.cpu.commit.COM:count_0 6403 # Number of instructions committed system.cpu.commit.COM:count_1 6404 # Number of instructions committed @@ -239,21 +233,23 @@ system.cpu.fetch.branchRate 0.194639 # Nu system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 22904 -system.cpu.fetch.rateDist.min_value 0 - 0 17622 7693.85% - 1 416 181.63% - 2 353 154.12% - 3 477 208.26% - 4 425 185.56% - 5 349 152.38% - 6 442 192.98% - 7 261 113.95% - 8 2559 1117.27% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 22904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 17622 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 416 1.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 353 1.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 477 2.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 425 1.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 349 1.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 442 1.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 261 1.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2559 11.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 22904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.351249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.742840 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency @@ -530,21 +526,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 22904 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 14156 6180.58% - 1 3289 1435.99% - 2 2351 1026.46% - 3 1373 599.46% - 4 854 372.86% - 5 535 233.58% - 6 261 113.95% - 7 57 24.89% - 8 28 12.22% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% +system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 22904 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued @@ -702,6 +700,14 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1282 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 58 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 32 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1303 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 28504 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index d0efe85b3..f1994d462 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:17:34 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing +M5 compiled Mar 6 2009 18:29:06 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:30:50 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d /n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 0584aa2e2..67e62423e 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,43 +1,41 @@ ---------- Begin Simulation Statistics ---------- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 4398 # Number of BTB hits -global.BPredUnit.BTBLookups 9844 # Number of BTB lookups -global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted -global.BPredUnit.lookups 11413 # Number of BP lookups -global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 30716 # Simulator instruction rate (inst/s) -host_mem_usage 201632 # Number of bytes of host memory used -host_seconds 0.47 # Real time elapsed on the host -host_tick_rate 58973694 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 3415 # Number of stores inserted to the mem dependence unit. +host_inst_rate 66771 # Simulator instruction rate (inst/s) +host_mem_usage 203496 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 128111456 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated sim_ticks 27756500 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 4398 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 9844 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11413 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 11413 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 3359 # Number of branches committed system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 42766 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 34594 8089.14% - 1 4804 1123.32% - 2 1741 407.10% - 3 720 168.36% - 4 413 96.57% - 5 144 33.67% - 6 196 45.83% - 7 51 11.93% - 8 103 24.08% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 42766 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 34594 80.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 4804 11.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1741 4.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 720 1.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 413 0.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 144 0.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 196 0.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 51 0.12% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 103 0.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 42766 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.354838 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 0.957636 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -134,21 +132,23 @@ system.cpu.fetch.branchRate 0.205588 # Nu system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 47090 -system.cpu.fetch.rateDist.min_value 0 - 0 30448 6465.92% - 1 7532 1599.49% - 2 1217 258.44% - 3 1059 224.89% - 4 1060 225.10% - 5 1193 253.34% - 6 711 150.99% - 7 327 69.44% - 8 3543 752.39% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 47090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 30448 64.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 7532 15.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1217 2.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 1059 2.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 1060 2.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1193 2.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 711 1.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 327 0.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3543 7.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 47090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.236929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.372442 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency @@ -283,21 +283,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 47090 -system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 34112 7244.00% - 1 5516 1171.37% - 2 3070 651.94% - 3 2146 455.72% - 4 997 211.72% - 5 653 138.67% - 6 342 72.63% - 7 211 44.81% - 8 43 9.13% -system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle.end_dist - +system.cpu.iq.ISSUE:issued_per_cycle::samples 47090 +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::0-1 34112 72.44% +system.cpu.iq.ISSUE:issued_per_cycle::1-2 5516 11.71% +system.cpu.iq.ISSUE:issued_per_cycle::2-3 3070 6.52% +system.cpu.iq.ISSUE:issued_per_cycle::3-4 2146 4.56% +system.cpu.iq.ISSUE:issued_per_cycle::4-5 997 2.12% +system.cpu.iq.ISSUE:issued_per_cycle::5-6 653 1.39% +system.cpu.iq.ISSUE:issued_per_cycle::6-7 342 0.73% +system.cpu.iq.ISSUE:issued_per_cycle::7-8 211 0.45% +system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% +system.cpu.iq.ISSUE:issued_per_cycle::total 47090 +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.620514 +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.275912 system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued @@ -377,6 +379,10 @@ system.cpu.l2cache.tagsinuse 251.642612 # Cy system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.memDep0.conflictingLoads 26 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 3415 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 55514 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed |