diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests/quick | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests/quick')
6 files changed, 3505 insertions, 3511 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index de241166d..181c5df24 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962054 # Number of seconds simulated -sim_ticks 1962054431000 # Number of ticks simulated -final_tick 1962054431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962058 # Number of seconds simulated +sim_ticks 1962057812000 # Number of ticks simulated +final_tick 1962057812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2014980 # Simulator instruction rate (inst/s) -host_op_rate 2014979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66592137800 # Simulator tick rate (ticks/s) -host_mem_usage 297124 # Number of bytes of host memory used -host_seconds 29.46 # Real time elapsed on the host -sim_insts 59368818 # Number of instructions simulated -sim_ops 59368818 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 834816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24594240 # Number of bytes read from this memory +host_inst_rate 1235183 # Simulator instruction rate (inst/s) +host_op_rate 1235183 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40819911602 # Simulator tick rate (ticks/s) +host_mem_usage 297060 # Number of bytes of host memory used +host_seconds 48.07 # Real time elapsed on the host +sim_insts 59370518 # Number of instructions simulated +sim_ops 59370518 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 834432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24593280 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 572928 # Number of bytes read from this memory -system.physmem.bytes_read::total 28681856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 834816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 29056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7716416 # Number of bytes written to this memory -system.physmem.bytes_written::total 7716416 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384285 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 29312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 572992 # Number of bytes read from this memory +system.physmem.bytes_read::total 28680832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 834432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 29312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7715456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7715456 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384270 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448154 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120569 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12534943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 292004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14618277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3932825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3932825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3932825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12534943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 292004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18551102 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 341254 # number of replacements -system.l2c.tagsinuse 65290.172220 # Cycle average of tags in use -system.l2c.total_refs 2492312 # Total number of references to valid blocks. -system.l2c.sampled_refs 406269 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.134635 # Average number of references to valid blocks. +system.physmem.num_reads::cpu1.inst 458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8953 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448138 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12534432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 292036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14617730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3932329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3932329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3932329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12534432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 292036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18550059 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 341238 # number of replacements +system.l2c.tagsinuse 65290.171288 # Cycle average of tags in use +system.l2c.total_refs 2492514 # Total number of references to valid blocks. +system.l2c.sampled_refs 406253 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.135374 # Average number of references to valid blocks. system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55481.040218 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4824.761707 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4855.330442 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.015324 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 13.024529 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.846573 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073620 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 55481.148199 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4824.640956 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4855.323185 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 116.032373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 13.026576 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.846575 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073618 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.074086 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001770 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001771 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000199 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.996249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 902302 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 773944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 31910 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1794895 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820354 # number of Writeback hits -system.l2c.Writeback_hits::total 820354 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 162 # number of UpgradeReq hits +system.l2c.ReadReq_hits::cpu0.inst 902430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 773977 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 86748 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 31919 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1795074 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 820361 # number of Writeback hits +system.l2c.Writeback_hits::total 820361 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 161 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 23 # number of SCUpgradeReq hits +system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 44 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.137144 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937644 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.895604 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.930344 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.603448 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadReq_mshr_uncacheable_latency::total 1388705000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1966544000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 505236000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2471780000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3335999000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524486000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3860485000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259663 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010110 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.137131 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.895795 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.930640 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.618182 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710526 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396328 # mshr miss rate for ReadExReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.718121 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396294 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412613 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.397444 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.288994 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.168917 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.170582 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.288994 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.168917 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.170582 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.814648 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41280 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.624989 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.630542 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.512821 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::total 0.397412 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.288979 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.168904 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.170563 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.288979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.168904 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.170563 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.899374 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41276.073620 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.307076 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.640657 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.612245 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.641026 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.950765 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40003.180886 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40002.307071 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.904973 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.440686 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.476762 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40015.321323 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.440686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.476762 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40015.321323 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.118716 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.568602 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.568602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +345,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41698 # number of replacements -system.iocache.tagsinuse 0.566768 # Cycle average of tags in use +system.iocache.tagsinuse 0.566822 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1754521474000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.566768 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035423 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035423 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 0.566822 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035426 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035426 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -363,12 +363,12 @@ system.iocache.overall_misses::tsunami.ide 41730 # system.iocache.overall_misses::total 41730 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21239998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21239998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7628774806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7628774806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7650014804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7650014804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7650014804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7650014804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11448106806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11448106806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11469346804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11469346804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11469346804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11469346804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -387,17 +387,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183595.851126 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183595.851126 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183321.706302 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183321.706302 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7551000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275512.774499 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275512.774499 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274846.556530 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274846.556530 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199371000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7072 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24657 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1067.731900 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8085.776858 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -413,12 +413,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41730 system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5467915000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5467915000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5479898000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5479898000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5479898000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5479898000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287247000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9287247000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9299230000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9299230000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9299230000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9299230000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -429,12 +429,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131592.101463 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131592.101463 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223509.024836 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223509.024836 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8658373 # DTB read hits +system.cpu0.dtb.read_hits 8658368 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.read_acv 174 # DTB read access violations system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.write_hits 6036768 # DTB write hits +system.cpu0.dtb.write_hits 6036843 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses system.cpu0.dtb.write_acv 115 # DTB write access violations system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.data_hits 14695141 # DTB hits +system.cpu0.dtb.data_hits 14695211 # DTB hits system.cpu0.dtb.data_misses 8485 # DTB misses system.cpu0.dtb.data_acv 289 # DTB access violations system.cpu0.dtb.data_accesses 719860 # DTB accesses -system.cpu0.itb.fetch_hits 3948342 # ITB hits +system.cpu0.itb.fetch_hits 3948323 # ITB hits system.cpu0.itb.fetch_misses 3841 # ITB misses system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_accesses 3952183 # ITB accesses +system.cpu0.itb.fetch_accesses 3952164 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3924108862 # number of cpu cycles simulated +system.cpu0.numCycles 3924115624 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54115388 # Number of instructions committed -system.cpu0.committedOps 54115388 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50086021 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 302769 # Number of float alu accesses -system.cpu0.num_func_calls 1426994 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6243543 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50086021 # number of integer instructions -system.cpu0.num_fp_insts 302769 # number of float instructions -system.cpu0.num_int_register_reads 68608752 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37121526 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 149232 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 152287 # number of times the floating registers were written -system.cpu0.num_mem_refs 14741011 # number of memory refs -system.cpu0.num_load_insts 8689642 # Number of load instructions -system.cpu0.num_store_insts 6051369 # Number of store instructions -system.cpu0.num_idle_cycles 3676810844.998126 # Number of idle cycles -system.cpu0.num_busy_cycles 247298017.001874 # Number of busy cycles +system.cpu0.committedInsts 54116505 # Number of instructions committed +system.cpu0.committedOps 54116505 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50087098 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 302903 # Number of float alu accesses +system.cpu0.num_func_calls 1426970 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6243728 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50087098 # number of integer instructions +system.cpu0.num_fp_insts 302903 # number of float instructions +system.cpu0.num_int_register_reads 68610814 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37122288 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 149298 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 152355 # number of times the floating registers were written +system.cpu0.num_mem_refs 14741096 # number of memory refs +system.cpu0.num_load_insts 8689646 # Number of load instructions +system.cpu0.num_store_insts 6051450 # Number of store instructions +system.cpu0.num_idle_cycles 3676817171.998126 # Number of idle cycles +system.cpu0.num_busy_cycles 247298452.001874 # Number of busy cycles system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6365 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202758 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72603 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 134 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202757 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72604 40.61% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104051 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178773 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71234 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 134 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 104050 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 178770 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71235 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71230 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144583 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900684456500 96.87% 96.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 103099000 0.01% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 795217500 0.04% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 71229 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144580 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900688314000 96.87% 96.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 102511500 0.01% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 795126500 0.04% 96.92% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60465248000 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962053593000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60465450000 3.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962056974000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684568 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808752 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684565 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808749 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed @@ -565,33 +565,33 @@ system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3870 2.06% 2.11% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3872 2.06% 2.11% # number of callpals executed system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 171949 91.52% 93.66% # number of callpals executed +system.cpu0.kern.callpal::swpipl 171948 91.52% 93.66% # number of callpals executed system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed -system.cpu0.kern.callpal::rti 4706 2.50% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4705 2.50% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.callpal::total 187881 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7232 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 7233 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1235 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1229 -system.cpu0.kern.mode_good::user 1230 +system.cpu0.kern.mode_good::kernel 1234 +system.cpu0.kern.mode_good::user 1235 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.169939 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170607 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.290593 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958392751000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3660835000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.291568 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958395542000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3661425000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3871 # number of times the context was actually changed +system.cpu0.kern.swap_context 3873 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -623,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 914730 # number of replacements -system.cpu0.icache.tagsinuse 508.781983 # Cycle average of tags in use -system.cpu0.icache.total_refs 53208794 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915241 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.136375 # Average number of references to valid blocks. +system.cpu0.icache.replacements 914851 # number of replacements +system.cpu0.icache.tagsinuse 508.781994 # Cycle average of tags in use +system.cpu0.icache.total_refs 53209789 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915362 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.129777 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.781983 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 508.781994 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53208794 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53208794 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53208794 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53208794 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53208794 # number of overall hits -system.cpu0.icache.overall_hits::total 53208794 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915369 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915369 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915369 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915369 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915369 # number of overall misses -system.cpu0.icache.overall_misses::total 915369 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13645389000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13645389000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13645389000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13645389000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13645389000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13645389000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54124163 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54124163 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54124163 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54124163 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54124163 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54124163 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016912 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016912 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016912 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016912 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016912 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016912 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.981775 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.981775 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14906.981775 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14906.981775 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 53209789 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53209789 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53209789 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53209789 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53209789 # number of overall hits +system.cpu0.icache.overall_hits::total 53209789 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915491 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915491 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915491 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915491 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915491 # number of overall misses +system.cpu0.icache.overall_misses::total 915491 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13646549000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13646549000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13646549000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13646549000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13646549000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13646549000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54125280 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54125280 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54125280 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54125280 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54125280 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54125280 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016914 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016914 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016914 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016914 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016914 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016914 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.262323 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.262323 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14906.262323 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14906.262323 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,112 +676,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915369 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915369 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915369 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915369 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915369 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915369 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10898588000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10898588000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10898588000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10898588000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10898588000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10898588000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016912 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016912 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016912 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11906.223610 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915491 # 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number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016914 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016914 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.504806 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1337806 # number of replacements -system.cpu0.dcache.tagsinuse 506.531092 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13370025 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338318 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.990170 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337819 # number of replacements +system.cpu0.dcache.tagsinuse 506.532892 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13370103 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1338331 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.990132 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.531092 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989319 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989319 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7444474 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7444474 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5554839 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5554839 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175825 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 175825 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191178 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191178 # 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number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326922 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326922 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326922 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113316000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26113316000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963970000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8963970000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238512000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 238512000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4951000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4951000 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191626 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14326235 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14326235 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14326235 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14326235 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122330 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122330 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049504 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049504 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087036 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087036 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002338 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002338 # miss rate for StoreCondReq accesses +system.cpu0.dcache.occ_blocks::cpu0.data 506.532892 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.989322 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.989322 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7444463 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7444463 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5554933 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5554933 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175817 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 175817 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191182 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191182 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12999396 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12999396 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12999396 # number of overall hits +system.cpu0.dcache.overall_hits::total 12999396 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1037635 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1037635 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 289296 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 289296 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16772 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16772 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 445 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 445 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326931 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326931 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326931 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326931 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113637000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 26113637000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963228000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8963228000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238633000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 238633000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4867000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4867000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 35076865000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 35076865000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 35076865000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 35076865000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482098 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8482098 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5844229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192589 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 192589 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191627 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191627 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14326327 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14326327 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14326327 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14326327 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122332 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122332 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049501 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087087 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087087 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002322 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002322 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092622 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.647392 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.647392 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30984.390230 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30984.390230 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14229.328242 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14229.328242 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11051.339286 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11051.339286 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26435.077570 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26435.077570 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.495926 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.495926 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30982.896411 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30982.896411 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14228.058669 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14228.058669 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10937.078652 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10937.078652 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26434.580999 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26434.580999 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -790,62 +790,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 785164 # number of writebacks -system.cpu0.dcache.writebacks::total 785164 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037616 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1037616 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289306 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 289306 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8096051001 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188226000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188226000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3606001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3606001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096456023 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31096456023 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096456023 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31096456023 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1463096000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1463096000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2089087000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2089087000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3552183000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3552183000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122330 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122330 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049504 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049504 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002338 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.writebacks::writebacks 785166 # number of writebacks +system.cpu0.dcache.writebacks::total 785166 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037635 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1037635 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289296 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 289296 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16772 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16772 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 445 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 445 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326931 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326931 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326931 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326931 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000669022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000669022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8095339001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8095339001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3531001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3531001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096008023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31096008023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096008023 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31096008023 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461823000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461823000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2088243000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2088243000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3550066000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3550066000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122332 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122332 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049501 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049501 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002322 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.092622 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.092622 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.586697 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.586697 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27984.386777 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27984.386777 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11229.328242 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11229.328242 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8049.109375 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8049.109375 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.435232 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.435232 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27982.892957 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27982.892957 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11228.058669 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11228.058669 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7934.833708 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7934.833708 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -857,22 +857,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1027490 # DTB read hits +system.cpu1.dtb.read_hits 1027530 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.read_acv 36 # DTB read access violations system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.write_hits 663174 # DTB write hits +system.cpu1.dtb.write_hits 663193 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses system.cpu1.dtb.write_acv 48 # DTB write access violations system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.data_hits 1690664 # DTB hits +system.cpu1.dtb.data_hits 1690723 # DTB hits system.cpu1.dtb.data_misses 3106 # DTB misses system.cpu1.dtb.data_acv 84 # DTB access violations system.cpu1.dtb.data_accesses 302878 # DTB accesses -system.cpu1.itb.fetch_hits 1394882 # ITB hits +system.cpu1.itb.fetch_hits 1394871 # ITB hits system.cpu1.itb.fetch_misses 1246 # ITB misses system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_accesses 1396128 # ITB accesses +system.cpu1.itb.fetch_accesses 1396117 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -885,51 +885,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923836450 # number of cpu cycles simulated +system.cpu1.numCycles 3923836552 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5253430 # Number of instructions committed -system.cpu1.committedOps 5253430 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4920456 # Number of integer alu accesses +system.cpu1.committedInsts 5254013 # Number of instructions committed +system.cpu1.committedOps 5254013 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4921025 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses -system.cpu1.num_func_calls 157592 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 506756 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4920456 # number of integer instructions +system.cpu1.num_func_calls 157600 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 506865 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4921025 # number of integer instructions system.cpu1.num_fp_insts 25430 # number of float instructions -system.cpu1.num_int_register_reads 6826440 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3699681 # number of times the integer registers were written +system.cpu1.num_int_register_reads 6827399 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3700117 # number of times the integer registers were written system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written -system.cpu1.num_mem_refs 1700289 # number of memory refs -system.cpu1.num_load_insts 1033544 # Number of load instructions -system.cpu1.num_store_insts 666745 # Number of store instructions -system.cpu1.num_idle_cycles 3903109824.944130 # Number of idle cycles -system.cpu1.num_busy_cycles 20726625.055870 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005282 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994718 # Percentage of idle cycles +system.cpu1.num_mem_refs 1700348 # number of memory refs +system.cpu1.num_load_insts 1033584 # Number of load instructions +system.cpu1.num_store_insts 666764 # Number of store instructions +system.cpu1.num_idle_cycles 3903107404.303190 # Number of idle cycles +system.cpu1.num_busy_cycles 20729147.696810 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005283 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994717 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 35943 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 35942 # number of hwrei instructions executed system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17500 60.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28707 # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17499 60.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28706 # number of times we switched to this ipl system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1920768070500 97.90% 97.90% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 725778000 0.04% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 67189500 0.00% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40357157000 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961918195000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1920766593500 97.90% 97.90% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 726074500 0.04% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 67017000 0.00% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 40358561000 2.06% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961918246000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.516800 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.705159 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.516830 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.705184 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed @@ -959,7 +959,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24055 81.82% 83.15% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24054 81.82% 83.15% # number of callpals executed system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed @@ -969,66 +969,66 @@ system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # nu system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29400 # number of callpals executed +system.cpu1.kern.callpal::total 29399 # number of callpals executed system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches -system.cpu1.kern.mode_switch::user 516 # number of protection mode switches +system.cpu1.kern.mode_switch::user 515 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 532 -system.cpu1.kern.mode_good::user 516 +system.cpu1.kern.mode_good::kernel 531 +system.cpu1.kern.mode_good::user 515 system.cpu1.kern.mode_good::idle 16 -system.cpu1.kern.mode_switch_good::kernel 0.605233 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.604096 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.306628 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4074736000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1594048000 0.08% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955463610000 99.71% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.306140 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4075179000 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1593973000 0.08% 0.29% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1955466537000 99.71% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 366 # number of times the context was actually changed -system.cpu1.icache.replacements 86665 # number of replacements -system.cpu1.icache.tagsinuse 419.761966 # Cycle average of tags in use -system.cpu1.icache.total_refs 5169415 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 87177 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.297923 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1958459766000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.761966 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819848 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819848 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5169415 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5169415 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5169415 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5169415 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5169415 # number of overall hits -system.cpu1.icache.overall_hits::total 5169415 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87205 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87205 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87205 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87205 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87205 # number of overall misses -system.cpu1.icache.overall_misses::total 87205 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1314538500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1314538500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1314538500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1314538500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1314538500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1314538500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5256620 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5256620 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5256620 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5256620 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5256620 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5256620 # number of overall (read+write) accesses +system.cpu1.icache.replacements 86678 # number of replacements +system.cpu1.icache.tagsinuse 419.761864 # Cycle average of tags in use +system.cpu1.icache.total_refs 5169985 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 87190 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.295619 # 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mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12073.751505 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12073.751505 # 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Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.170322 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1941569697000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 416.811918 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.814086 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.814086 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 982724 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 982724 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 626457 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 626457 # number of WriteReq hits +system.cpu1.dcache.replacements 53530 # number of replacements +system.cpu1.dcache.tagsinuse 416.811223 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1627239 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 53938 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 30.168694 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1941569871000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 416.811223 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.814084 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.814084 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 982758 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 982758 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 626472 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 626472 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11708 # 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number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034983 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.034983 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034840 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034840 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081459 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081459 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044323 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044323 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034922 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034922 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034922 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034922 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13600.477260 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13600.477260 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30710.437859 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30710.437859 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12156.530409 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12156.530409 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13042.357274 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13042.357274 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20244.066632 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20244.066632 # average overall miss latency +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044405 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044405 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034927 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034927 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034927 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034927 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13599.449840 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13599.449840 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30707.260989 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30707.260989 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12155.533400 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12155.533400 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13027.573529 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13027.573529 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20242.239011 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20242.239011 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1151,62 +1151,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 35190 # number of writebacks -system.cpu1.dcache.writebacks::total 35190 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35620 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 35620 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22610 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 22610 # number of WriteReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 35195 # number of writebacks +system.cpu1.dcache.writebacks::total 35195 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35626 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 35626 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22614 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 22614 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 543 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 543 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 58230 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 58230 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 58230 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 58230 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377581004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377581004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626529004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626529004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9184000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9184000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5453000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5453000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004110008 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1004110008 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004110008 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1004110008 # number of overall MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 544 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 544 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 58240 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 58240 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 58240 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 58240 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377607005 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377607005 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626568004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626568004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9183000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9183000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5455000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5455000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004175009 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1004175009 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004175009 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1004175009 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534607500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534607500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555172500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555172500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034978 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034978 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034835 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534647000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534647000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555212000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555212000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034983 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034983 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034840 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034840 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044323 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044323 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034922 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034922 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10600.252779 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10600.252779 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27710.261123 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27710.261123 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9156.530409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9156.530409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10042.357274 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10042.357274 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044405 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044405 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034927 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034927 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10599.197356 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10599.197356 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27707.084284 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27707.084284 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9155.533400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9155.533400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10027.573529 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10027.573529 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 9ccbe5ddb..c82eab488 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.921792 # Number of seconds simulated -sim_ticks 1921792488000 # Number of ticks simulated -final_tick 1921792488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920895 # Number of seconds simulated +sim_ticks 1920895294000 # Number of ticks simulated +final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1964765 # Simulator instruction rate (inst/s) -host_op_rate 1964764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67191639126 # Simulator tick rate (ticks/s) -host_mem_usage 295072 # Number of bytes of host memory used -host_seconds 28.60 # Real time elapsed on the host -sim_insts 56195476 # Number of instructions simulated -sim_ops 56195476 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory +host_inst_rate 1271848 # Simulator instruction rate (inst/s) +host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43474553061 # Simulator tick rate (ticks/s) +host_mem_usage 295012 # Number of bytes of host memory used +host_seconds 44.18 # Real time elapsed on the host +sim_insts 56195754 # Number of instructions simulated +sim_ops 56195754 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859968 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28361728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7403520 # Number of bytes written to this memory -system.physmem.bytes_written::total 7403520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28362816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404288 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388437 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443152 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115680 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115680 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12935191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1380145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14757955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3852403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3852403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3852403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12935191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1380145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18610359 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 336240 # number of replacements -system.l2c.tagsinuse 65308.066862 # Cycle average of tags in use -system.l2c.total_refs 2448422 # Total number of references to valid blocks. -system.l2c.sampled_refs 401402 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.099676 # Average number of references to valid blocks. +system.physmem.num_reads::total 443169 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115692 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115692 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12941865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1380789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14765415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 336257 # number of replacements +system.l2c.tagsinuse 65308.063316 # Cycle average of tags in use +system.l2c.total_refs 2448454 # Total number of references to valid blocks. +system.l2c.sampled_refs 401419 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.099497 # Average number of references to valid blocks. system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55651.693971 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4767.859045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4888.513847 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.849177 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.072752 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.074593 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 916493 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814973 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1731466 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835196 # number of Writeback hits -system.l2c.Writeback_hits::total 835196 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.355427 # Cycle average of tags in use +system.iocache.tagsinuse 1.347775 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.355427 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084714 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084714 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084236 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -227,12 +227,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7634106806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7634106806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7654779804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7654779804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7654779804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7654779804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11448538806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11448538806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11469211804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11469211804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11469211804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11469211804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -251,17 +251,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183724.172266 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183724.172266 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183457.874272 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183457.874272 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7454000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275523.171111 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275523.171111 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274876.256537 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274876.256537 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199147000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7097 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24626 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1050.302945 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8086.859417 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -277,12 +277,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5473252000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5473252000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5484928000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5484928000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5484928000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5484928000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287684000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9287684000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9299360000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9299360000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9299360000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9299360000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -293,12 +293,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131720.542934 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131720.542934 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223519.541779 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223519.541779 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066933 # DTB read hits +system.cpu.dtb.read_hits 9066995 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6357519 # DTB write hits +system.cpu.dtb.write_hits 6357563 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15424452 # DTB hits +system.cpu.dtb.data_hits 15424558 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4975863 # ITB hits +system.cpu.itb.fetch_hits 4975749 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980869 # ITB accesses +system.cpu.itb.fetch_accesses 4980755 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3843584976 # number of cpu cycles simulated +system.cpu.numCycles 3841790588 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195476 # Number of instructions committed -system.cpu.committedOps 56195476 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066692 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483822 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469666 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066692 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71339619 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530592 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15477059 # number of memory refs -system.cpu.num_load_insts 9103780 # Number of load instructions -system.cpu.num_store_insts 6373279 # Number of store instructions -system.cpu.num_idle_cycles 3588655153.998133 # Number of idle cycles -system.cpu.num_busy_cycles 254929822.001867 # Number of busy cycles -system.cpu.not_idle_fraction 0.066326 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933674 # Percentage of idle cycles +system.cpu.committedInsts 56195754 # Number of instructions committed +system.cpu.committedOps 56195754 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52066962 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1483816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469707 # number of instructions that are conditional controls +system.cpu.num_int_insts 52066962 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71340235 # number of times the integer registers were read +system.cpu.num_int_register_writes 38530699 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15477180 # number of memory refs +system.cpu.num_load_insts 9103852 # Number of load instructions +system.cpu.num_store_insts 6373328 # Number of store instructions +system.cpu.num_idle_cycles 3586858626.998133 # Number of idle cycles +system.cpu.num_busy_cycles 254931961.001867 # Number of busy cycles +system.cpu.not_idle_fraction 0.066358 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933642 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212119 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74932 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212106 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1937 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106298 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183298 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73565 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1937 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73565 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149198 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1861046523500 96.84% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 104284500 0.01% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 779455000 0.04% 96.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 59861392000 3.11% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1921791655000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981757 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106288 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183284 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860148981000 96.84% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 104328000 0.01% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 779009000 0.04% 96.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 59862143000 3.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920894461000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692064 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.813964 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692101 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.813988 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.16% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 176067 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6838 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 176055 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5162 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193021 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.callpal::total 193009 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323285 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323231 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080591 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46687559000 2.43% 2.43% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5260775000 0.27% 2.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869843314000 97.30% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_ticks::kernel 46683787000 2.43% 2.43% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5260006000 0.27% 2.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868950661000 97.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 929133 # number of replacements -system.cpu.icache.tagsinuse 508.706285 # Cycle average of tags in use -system.cpu.icache.total_refs 55277511 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929644 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.460945 # Average number of references to valid blocks. +system.cpu.icache.replacements 929101 # number of replacements +system.cpu.icache.tagsinuse 508.704776 # Cycle average of tags in use +system.cpu.icache.total_refs 55277821 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 929612 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.463326 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.706285 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993567 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993567 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55277511 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277511 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277511 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277511 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277511 # number of overall hits -system.cpu.icache.overall_hits::total 55277511 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929804 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929804 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929804 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929804 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929804 # number of overall misses -system.cpu.icache.overall_misses::total 929804 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13857748000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13857748000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13857748000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13857748000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13857748000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13857748000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56207315 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56207315 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56207315 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56207315 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56207315 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56207315 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 508.704776 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993564 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993564 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55277821 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55277821 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55277821 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55277821 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55277821 # number of overall hits +system.cpu.icache.overall_hits::total 55277821 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929772 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929772 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929772 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929772 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929772 # number of overall misses +system.cpu.icache.overall_misses::total 929772 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13856924500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13856924500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13856924500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13856924500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13856924500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13856924500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56207593 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56207593 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56207593 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56207593 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56207593 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56207593 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.945348 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14903.945348 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14903.945348 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14903.945348 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.572596 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14903.572596 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14903.572596 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14903.572596 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,104 +535,104 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929804 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929804 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929804 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929804 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929804 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929804 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11067649000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11067649000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11067649000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11067649000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11067649000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11067649000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929772 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929772 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929772 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929772 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929772 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929772 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11066921000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11066921000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11066921000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11066921000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11066921000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11066921000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.206482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.206482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.206482 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.206482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.206482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.206482 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11902.833168 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11902.833168 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11902.833168 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11902.833168 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11902.833168 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11902.833168 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1390802 # number of replacements -system.cpu.dcache.tagsinuse 511.979761 # Cycle average of tags in use -system.cpu.dcache.total_refs 14052158 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1391314 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.099918 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1390864 # number of replacements +system.cpu.dcache.tagsinuse 511.979749 # Cycle average of tags in use +system.cpu.dcache.total_refs 14052220 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1391376 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.099513 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 101905000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.979761 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.979749 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999960 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999960 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7816348 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816348 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853489 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853489 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199276 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199276 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669837 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669837 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669837 # number of overall hits -system.cpu.dcache.overall_hits::total 13669837 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069663 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069663 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304397 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304397 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7816402 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816402 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853491 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853491 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199280 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199280 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13669893 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669893 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669893 # number of overall hits +system.cpu.dcache.overall_hits::total 13669893 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069678 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069678 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304443 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304443 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17273 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17273 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374060 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374060 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374060 # number of overall misses -system.cpu.dcache.overall_misses::total 1374060 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26660030000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26660030000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9238691000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9238691000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247715000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 247715000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35898721000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35898721000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35898721000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35898721000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8886011 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8886011 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157886 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157886 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200300 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200300 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199276 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199276 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043897 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043897 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043897 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043897 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120376 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120376 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049432 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049432 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086236 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086236 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091337 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091337 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091337 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091337 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.765709 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.765709 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30350.795179 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30350.795179 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14341.168297 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14341.168297 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26126.021426 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26126.021426 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26126.021426 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26126.021426 # average overall miss latency +system.cpu.dcache.demand_misses::cpu.data 1374121 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374121 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374121 # number of overall misses +system.cpu.dcache.overall_misses::total 1374121 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26660570000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26660570000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9239957000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9239957000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247721000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 247721000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35900527000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35900527000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35900527000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35900527000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8886080 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8886080 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199280 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199280 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15044014 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15044014 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15044014 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15044014 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120377 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120377 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049439 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049439 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086234 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086234 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091340 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091340 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091340 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091340 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.921030 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.921030 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30350.367721 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30350.367721 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14341.515660 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14341.515660 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26126.175934 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26126.175934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26126.175934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26126.175934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,54 +641,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835196 # number of writebacks -system.cpu.dcache.writebacks::total 835196 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069663 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069663 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304397 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304397 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 835257 # number of writebacks +system.cpu.dcache.writebacks::total 835257 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069678 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069678 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304443 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304443 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17273 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 17273 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374060 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374060 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374060 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374060 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23450996000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23450996000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8325500000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8325500000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195896000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195896000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31776496000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31776496000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31776496000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31776496000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1374121 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374121 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374121 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374121 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23451491000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23451491000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8326628000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8326628000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195902000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195902000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31778119000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31778119000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31778119000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31778119000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1421708000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1421708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011005000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011005000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432713000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432713000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049432 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049432 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086236 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086236 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.723640 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.723640 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.795179 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.795179 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.168297 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.168297 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432514000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432514000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049439 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049439 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086234 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086234 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091340 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091340 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.878962 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.878962 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.367721 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.367721 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.515660 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.515660 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index a84f458bf..ef29d389c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.207291 # Nu sim_ticks 1207290627000 # Number of ticks simulated final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1000042 # Simulator instruction rate (inst/s) -host_op_rate 1274494 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19638848032 # Simulator tick rate (ticks/s) -host_mem_usage 383956 # Number of bytes of host memory used -host_seconds 61.47 # Real time elapsed on the host +host_inst_rate 965295 # Simulator instruction rate (inst/s) +host_op_rate 1230212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18956490102 # Simulator tick rate (ticks/s) +host_mem_usage 382720 # Number of bytes of host memory used +host_seconds 63.69 # Real time elapsed on the host sim_insts 61477134 # Number of instructions simulated sim_ops 78349023 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -89,20 +89,20 @@ system.physmem.bw_total::cpu1.inst 267624 # To system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 69267 # number of replacements -system.l2c.tagsinuse 52917.687187 # Cycle average of tags in use +system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use system.l2c.total_refs 1645693 # Total number of references to valid blocks. system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40124.661939 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3720.854168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4213.259552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2800.295642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2055.865658 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -189,40 +189,40 @@ system.l2c.overall_misses::cpu1.data 75979 # nu system.l2c.overall_misses::total 161841 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 298918500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 409688500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 263122000 # 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average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -586,8 +586,8 @@ system.cpu0.num_fp_register_writes 840 # nu system.cpu0.num_mem_refs 13404188 # number of memory refs system.cpu0.num_load_insts 7413537 # Number of load instructions system.cpu0.num_store_insts 5990651 # Number of store instructions -system.cpu0.num_idle_cycles 2267023722.330122 # Number of idle cycles -system.cpu0.num_busy_cycles 147557531.669878 # Number of busy cycles +system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles +system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -613,12 +613,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 408647 # system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses system.cpu0.icache.overall_misses::total 408647 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096214000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6096214000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6096214000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6096214000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6096214000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6096214000 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses @@ -631,12 +631,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.044180 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.044180 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14918.044180 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14918.044180 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -651,12 +651,12 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869428500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869428500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869428500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4869428500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869428500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4869428500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles @@ -667,24 +667,24 @@ system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11915.977604 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 330734 # number of replacements -system.cpu0.dcache.tagsinuse 459.649704 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 459.649704 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits @@ -711,18 +711,18 @@ system.cpu0.dcache.demand_misses::cpu0.data 369775 # system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses system.cpu0.dcache.overall_misses::total 369775 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443053000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3443053000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918745500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4918745500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100903000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 100903000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74598000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 74598000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8361798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8361798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8361798500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8361798500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443058000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8361785500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) @@ -747,18 +747,18 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.600119 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.600119 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34707.000325 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34707.000325 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.697051 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.697051 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9950.380152 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9950.380152 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22613.206680 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22613.206680 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,26 +781,26 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758299641 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758299641 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493384071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493384071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72902006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72902006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52119015 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52119015 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251683712 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7251683712 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251683712 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7251683712 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559859000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559859000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253198500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253198500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813057500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses @@ -813,20 +813,20 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12094.993887 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12094.993887 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.621364 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.621364 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.909491 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.909491 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6959.409133 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6959.409133 # average StoreCondReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -894,8 +894,8 @@ system.cpu1.num_fp_register_writes 2260 # nu system.cpu1.num_mem_refs 14689113 # number of memory refs system.cpu1.num_load_insts 8640454 # Number of load instructions system.cpu1.num_store_insts 6048659 # Number of store instructions -system.cpu1.num_idle_cycles 1863361909.381196 # Number of idle cycles -system.cpu1.num_busy_cycles 549721128.618804 # Number of busy cycles +system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles +system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -921,12 +921,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 455583 # system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses system.cpu1.icache.overall_misses::total 455583 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728267000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6728267000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6728267000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6728267000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6728267000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6728267000 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses @@ -939,12 +939,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.476875 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.476875 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14768.476875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.476875 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -959,12 +959,12 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360614000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360614000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360614000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5360614000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360614000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5360614000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles @@ -975,24 +975,24 @@ system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.492604 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 292605 # number of replacements -system.cpu1.dcache.tagsinuse 473.034253 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 473.034253 # Average occupied blocks per requestor +system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits @@ -1019,18 +1019,18 @@ system.cpu1.dcache.demand_misses::cpu1.data 321159 # system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses system.cpu1.dcache.overall_misses::total 321159 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374183000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2374183000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137653000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5137653000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106350500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 106350500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87844000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 87844000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7511836000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7511836000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7511836000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7511836000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) @@ -1055,18 +1055,18 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13885.085503 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13885.085503 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.018299 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.018299 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9563.033900 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9563.033900 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.411987 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.411987 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23389.772667 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23389.772667 # average overall miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1089,24 +1089,24 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860610613 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860610613 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686894192 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686894192 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72963005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72963005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57623011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57623011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547504805 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6547504805 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547504805 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6547504805 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686172000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686172000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618366000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses @@ -1119,18 +1119,18 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10881.527435 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10881.527435 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.381445 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.381445 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6560.831310 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6560.831310 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.245382 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.245382 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1152,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574301885796 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 574301885796 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574301885796 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 574301885796 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 5fafbec2b..1b5c0ec90 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196043 # Number of seconds simulated -sim_ticks 5196043137000 # Number of ticks simulated -final_tick 5196043137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196023 # Number of seconds simulated +sim_ticks 5196022575000 # Number of ticks simulated +final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 682761 # Simulator instruction rate (inst/s) -host_op_rate 1316197 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27664981075 # Simulator tick rate (ticks/s) -host_mem_usage 397336 # Number of bytes of host memory used -host_seconds 187.82 # Real time elapsed on the host -sim_insts 128236332 # Number of instructions simulated -sim_ops 247208442 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2881344 # Number of bytes read from this memory +host_inst_rate 1315892 # Simulator instruction rate (inst/s) +host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53344387183 # Simulator tick rate (ticks/s) +host_mem_usage 354072 # Number of bytes of host memory used +host_seconds 97.41 # Real time elapsed on the host +sim_insts 128174734 # Number of instructions simulated +sim_ops 247089109 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2880320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8950528 # Number of bytes read from this memory -system.physmem.bytes_read::total 12656512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8081152 # Number of bytes written to this memory -system.physmem.bytes_written::total 8081152 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45021 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 824192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8956288 # Number of bytes read from this memory +system.physmem.bytes_read::total 12661120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8085888 # Number of bytes written to this memory +system.physmem.bytes_written::total 8085888 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45005 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139852 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197758 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126268 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126268 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 554527 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12878 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139942 # Number of read requests responded to by this memory +system.physmem.num_reads::total 197830 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126342 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126342 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 554332 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1722566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2435798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158644 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158644 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1555251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1555251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1555251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 554527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1723682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2436695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1722566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3991049 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 86291 # number of replacements -system.l2c.tagsinuse 64759.780052 # Cycle average of tags in use -system.l2c.total_refs 3494113 # Total number of references to valid blocks. -system.l2c.sampled_refs 150981 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.142733 # Average number of references to valid blocks. +system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 86330 # number of replacements +system.l2c.tagsinuse 64759.737076 # Cycle average of tags in use +system.l2c.total_refs 3491284 # Total number of references to valid blocks. +system.l2c.sampled_refs 151054 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.112821 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50071.847750 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.141309 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3396.359734 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11291.431260 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.764036 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051824 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.172294 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.988156 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6458 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 779608 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1280721 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2069598 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1543757 # number of Writeback hits -system.l2c.Writeback_hits::total 1543757 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 305 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 200867 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 200867 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6458 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 779608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1481588 # number of demand (read+write) hits -system.l2c.demand_hits::total 2270465 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6458 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2811 # number of overall hits -system.l2c.overall_hits::cpu.inst 779608 # number of overall hits -system.l2c.overall_hits::cpu.data 1481588 # number of overall hits -system.l2c.overall_hits::total 2270465 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.988155 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2068208 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1543462 # number of Writeback hits +system.l2c.Writeback_hits::total 1543462 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 302 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 200678 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 778172 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1481001 # number of demand (read+write) hits +system.l2c.demand_hits::total 2268886 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 6719 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 2994 # number of overall hits +system.l2c.overall_hits::cpu.inst 778172 # number of overall hits +system.l2c.overall_hits::cpu.data 1481001 # number of overall hits +system.l2c.overall_hits::total 2268886 # number of overall hits system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12881 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 28319 # number of ReadReq misses -system.l2c.ReadReq_misses::total 41205 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1371 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063391 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063391 # mshr miss rate for overall accesses +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40032.683798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.786292 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40359.203980 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40283.734500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40283.734500 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40021.500596 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40021.500596 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -251,14 +251,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47503 # number of replacements -system.iocache.tagsinuse 0.108785 # Cycle average of tags in use +system.iocache.tagsinuse 0.108744 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.108785 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006799 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006799 # Average percentage of cache occupancy +system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006796 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses system.iocache.ReadReq_misses::total 838 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -267,14 +267,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128838932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 128838932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7147789160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7147789160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7276628092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7276628092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7276628092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7276628092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129993932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 129993932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10714208160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10714208160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10844202092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10844202092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10844202092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10844202092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -291,19 +291,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153745.742243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 153745.742243 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 152992.062500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 152992.062500 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 153005.342781 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 153005.342781 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 372008 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155124.023866 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155124.023866 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229328.085616 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229328.085616 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228020.566298 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228020.566298 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 89624012 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 38 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10977 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9789.684211 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8164.709119 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -317,14 +317,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85232000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 85232000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4718093984 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4718093984 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4803325984 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4803325984 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86387000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86387000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8284511992 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8284511992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8370898992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8370898992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -333,14 +333,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101708.830549 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 101708.830549 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 100986.600685 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 100986.600685 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103087.112172 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103087.112172 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177322.602568 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177322.602568 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -354,75 +354,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10392086274 # number of cpu cycles simulated +system.cpu.numCycles 10392045150 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128236332 # Number of instructions committed -system.cpu.committedOps 247208442 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231946757 # Number of integer alu accesses +system.cpu.committedInsts 128174734 # Number of instructions committed +system.cpu.committedOps 247089109 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231827885 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23151326 # number of instructions that are conditional controls -system.cpu.num_int_insts 231946757 # number of integer instructions +system.cpu.num_conditional_control_insts 23138722 # number of instructions that are conditional controls +system.cpu.num_int_insts 231827885 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566912178 # number of times the integer registers were read -system.cpu.num_int_register_writes 293147449 # number of times the integer registers were written +system.cpu.num_int_register_reads 566609561 # number of times the integer registers were read +system.cpu.num_int_register_writes 292994515 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22230275 # number of memory refs -system.cpu.num_load_insts 13869948 # Number of load instructions -system.cpu.num_store_insts 8360327 # Number of store instructions -system.cpu.num_idle_cycles 9776409858.670118 # Number of idle cycles -system.cpu.num_busy_cycles 615676415.329882 # Number of busy cycles -system.cpu.not_idle_fraction 0.059245 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940755 # Percentage of idle cycles +system.cpu.num_mem_refs 22210252 # number of memory refs +system.cpu.num_load_insts 13855140 # Number of load instructions +system.cpu.num_store_insts 8355112 # Number of store instructions +system.cpu.num_idle_cycles 9776628704.958118 # Number of idle cycles +system.cpu.num_busy_cycles 615416445.041882 # Number of busy cycles +system.cpu.not_idle_fraction 0.059220 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940780 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791983 # number of replacements -system.cpu.icache.tagsinuse 510.339207 # Cycle average of tags in use -system.cpu.icache.total_refs 144447737 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 792495 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.269588 # Average number of references to valid blocks. +system.cpu.icache.replacements 790545 # number of replacements +system.cpu.icache.tagsinuse 510.338891 # Cycle average of tags in use +system.cpu.icache.total_refs 144363546 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791057 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.494493 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.339207 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.338891 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144447737 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144447737 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144447737 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144447737 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144447737 # number of overall hits -system.cpu.icache.overall_hits::total 144447737 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792502 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792502 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792502 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792502 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792502 # number of overall misses -system.cpu.icache.overall_misses::total 792502 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11813272500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11813272500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11813272500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11813272500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11813272500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11813272500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145240239 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145240239 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145240239 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145240239 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145240239 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145240239 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005456 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005456 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005456 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005456 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005456 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005456 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14906.299921 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14906.299921 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14906.299921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14906.299921 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 144363546 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144363546 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144363546 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144363546 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144363546 # number of overall hits +system.cpu.icache.overall_hits::total 144363546 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791064 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791064 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791064 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791064 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791064 # number of overall misses +system.cpu.icache.overall_misses::total 791064 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11792673000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11792673000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11792673000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11792673000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11792673000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11792673000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145154610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145154610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145154610 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145154610 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145154610 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145154610 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14907.356421 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14907.356421 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14907.356421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14907.356421 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,80 +431,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792502 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 792502 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 792502 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 792502 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 792502 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 792502 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9434751000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9434751000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9434751000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9434751000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9434751000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9434751000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005456 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005456 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005456 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11905.018536 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11905.018536 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791064 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791064 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791064 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791064 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791064 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791064 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9418462000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9418462000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9418462000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9418462000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9418462000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9418462000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11906.068283 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11906.068283 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3538 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.068811 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7893 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3550 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.223380 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5169410055000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.068811 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191801 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191801 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7916 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7916 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3550 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.065778 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7809 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3562 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.192308 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5171078849000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.065778 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191611 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191611 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7809 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7809 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7918 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7918 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7918 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7918 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4398 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4398 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4398 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4398 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4398 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4398 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51351000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51351000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51351000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 51351000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51351000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 51351000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12314 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12314 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7811 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7811 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7811 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7811 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4415 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4415 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4415 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4415 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4415 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4415 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 53239000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 53239000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 53239000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 53239000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 53239000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 53239000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12316 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12316 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12316 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12316 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.357154 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.357154 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.357096 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.357096 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.357096 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.357096 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11675.989086 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11675.989086 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11675.989086 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11675.989086 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361175 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361175 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361116 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.361116 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361116 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.361116 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12058.663647 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12058.663647 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12058.663647 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,78 +513,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 656 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 656 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4398 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4398 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4398 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4398 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4398 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4398 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38157000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38157000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38157000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38157000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38157000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38157000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.357154 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.357154 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.357096 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.357096 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8675.989086 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 830 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 830 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4415 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4415 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4415 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4415 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4415 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4415 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39994000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39994000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39994000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39994000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39994000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39994000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361175 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361175 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361116 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361116 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9058.663647 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7615 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.050606 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13416 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7630 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.758322 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5165509990000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050606 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315663 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315663 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13416 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13416 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13416 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13416 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13416 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13416 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8830 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8830 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8830 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8830 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8830 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8830 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 114790500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 114790500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 114790500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 114790500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 114790500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 114790500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22246 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22246 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22246 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22246 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22246 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22246 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.396925 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.396925 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.396925 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.396925 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.396925 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.396925 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13000.056625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13000.056625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13000.056625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13000.056625 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7810 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.052392 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12921 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7826 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.651035 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5166488673000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052392 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315774 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315774 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12921 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12921 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12921 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12921 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12921 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12921 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9010 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9010 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9010 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9010 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9010 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9010 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 118862500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 118862500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 118862500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 118862500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 118862500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 118862500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21931 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21931 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21931 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21931 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21931 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21931 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.410834 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.410834 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.410834 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.410834 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.410834 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.410834 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13192.286349 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13192.286349 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13192.286349 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,90 +593,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3005 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3005 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8830 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8830 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8830 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8830 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8830 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8830 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88300000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88300000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88300000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88300000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88300000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88300000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.396925 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.396925 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.396925 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10000 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3142 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3142 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9010 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9010 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9010 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9010 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9010 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9010 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 91832000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 91832000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 91832000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 91832000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 91832000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 91832000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.410834 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.410834 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.410834 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10192.230855 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1622589 # number of replacements -system.cpu.dcache.tagsinuse 511.997330 # Cycle average of tags in use -system.cpu.dcache.total_refs 20023565 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1623101 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.336611 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1622132 # number of replacements +system.cpu.dcache.tagsinuse 511.997396 # Cycle average of tags in use +system.cpu.dcache.total_refs 20004026 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622644 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.328044 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997330 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997396 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11986605 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11986605 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8034775 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8034775 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20021380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20021380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20021380 # number of overall hits -system.cpu.dcache.overall_hits::total 20021380 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1309816 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1309816 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315519 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315519 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1625335 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1625335 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1625335 # number of overall misses -system.cpu.dcache.overall_misses::total 1625335 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19889195500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19889195500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9348149500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9348149500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29237345000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29237345000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29237345000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29237345000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13296421 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13296421 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21646715 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21646715 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21646715 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21646715 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098509 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098509 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037785 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037785 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075085 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075085 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075085 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075085 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15184.724801 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15184.724801 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29627.849670 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29627.849670 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17988.503908 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17988.503908 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11972131 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11972131 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8029723 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8029723 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20001854 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20001854 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20001854 # number of overall hits +system.cpu.dcache.overall_hits::total 20001854 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1309489 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1309489 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315369 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315369 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624858 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624858 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624858 # number of overall misses +system.cpu.dcache.overall_misses::total 1624858 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19885711500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19885711500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9346101000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9346101000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29231812500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29231812500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29231812500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29231812500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13281620 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13281620 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8345092 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8345092 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21626712 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21626712 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21626712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21626712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098594 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098594 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037791 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037791 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075132 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075132 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075132 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075132 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15185.856086 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15185.856086 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29635.446096 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29635.446096 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17990.379775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17990.379775 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,46 +685,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540096 # number of writebacks -system.cpu.dcache.writebacks::total 1540096 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309816 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315519 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315519 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1625335 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1625335 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625335 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625335 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15959698500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15959698500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401590001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401590001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24361288501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24361288501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24361288501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24361288501 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1539490 # number of writebacks +system.cpu.dcache.writebacks::total 1539490 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309489 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1309489 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315369 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315369 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1624858 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1624858 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1624858 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1624858 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15957199501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15957199501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8399992000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8399992000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24357191501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24357191501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24357191501 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24357191501 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 93628676500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 93628676500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467826500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467826500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096503000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096503000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098509 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098509 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037785 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037785 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075085 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075085 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12184.687391 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12184.687391 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26627.841750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26627.841750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467841500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467841500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096518000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096518000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098594 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098594 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.075132 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.075132 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12185.821722 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12185.821722 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26635.439755 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26635.439755 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 076c105ad..9e326e98d 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.019665 # Number of seconds simulated -sim_ticks 19665440 # Number of ticks simulated -final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.006104 # Number of seconds simulated +sim_ticks 6103915 # Number of ticks simulated +final_tick 6103915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 178903 # Simulator tick rate (ticks/s) -host_mem_usage 378856 # Number of bytes of host memory used -host_seconds 109.92 # Real time elapsed on the host +host_tick_rate 78453 # Simulator tick rate (ticks/s) +host_mem_usage 374396 # Number of bytes of host memory used +host_seconds 77.80 # Real time elapsed on the host system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 99534 # number of read accesses completed -system.cpu0.num_writes 53920 # number of write accesses completed +system.cpu0.num_reads 99027 # number of read accesses completed +system.cpu0.num_writes 53493 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99604 # number of read accesses completed -system.cpu1.num_writes 53779 # number of write accesses completed +system.cpu1.num_reads 98254 # number of read accesses completed +system.cpu1.num_writes 52787 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99103 # number of read accesses completed -system.cpu2.num_writes 53314 # number of write accesses completed +system.cpu2.num_reads 99047 # number of read accesses completed +system.cpu2.num_writes 53306 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99223 # number of read accesses completed -system.cpu3.num_writes 53188 # number of write accesses completed +system.cpu3.num_reads 98414 # number of read accesses completed +system.cpu3.num_writes 53420 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53373 # number of write accesses completed +system.cpu4.num_writes 53741 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99316 # number of read accesses completed -system.cpu5.num_writes 53693 # number of write accesses completed +system.cpu5.num_reads 98111 # number of read accesses completed +system.cpu5.num_writes 53002 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99832 # number of read accesses completed -system.cpu6.num_writes 53341 # number of write accesses completed +system.cpu6.num_reads 99154 # number of read accesses completed +system.cpu6.num_writes 52587 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99257 # number of read accesses completed -system.cpu7.num_writes 53656 # number of write accesses completed +system.cpu7.num_reads 99215 # number of read accesses completed +system.cpu7.num_writes 53364 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 1fe48d0c8..0a33e618b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,640 +1,634 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000224 # Number of seconds simulated -sim_ticks 223713460 # Number of ticks simulated -final_tick 223713460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000247 # Number of seconds simulated +sim_ticks 246648467 # Number of ticks simulated +final_tick 246648467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1721618 # Simulator tick rate (ticks/s) -host_mem_usage 347508 # Number of bytes of host memory used -host_seconds 129.94 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 81065 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82807 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 84800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 80115 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 83878 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 83050 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 84723 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 83101 # Number of bytes read from this memory -system.physmem.bytes_read::total 663539 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 423360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5290 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5393 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5404 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5324 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5344 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5398 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5445 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5412 # Number of bytes written to this memory -system.physmem.bytes_written::total 466370 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11135 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11041 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11139 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11029 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88727 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6615 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5290 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5393 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5404 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5324 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5344 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5398 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5445 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5412 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49625 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 362360852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 370147599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 379056316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 358114349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 374934973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 371233810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 378712126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 371461780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2966021803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1892420778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 23646320 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 24106730 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 24155900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 23798300 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 23887700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 24129080 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 24339170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 24191660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2084675638 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1892420778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 386007172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 394254329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 403212216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 381912648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 398822673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 395362890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 403051296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 395653440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5050697441 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 13635 # number of replacements -system.l2c.tagsinuse 790.382632 # Cycle average of tags in use -system.l2c.total_refs 148986 # Total number of references to valid blocks. -system.l2c.sampled_refs 14447 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.312591 # Average number of references to valid blocks. +host_tick_rate 1526116 # Simulator tick rate (ticks/s) +host_mem_usage 347672 # Number of bytes of host memory used +host_seconds 161.62 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 85584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 85024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 83876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80921 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79699 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 87892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 84658 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 85643 # Number of bytes read from this memory +system.physmem.bytes_read::total 673297 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 432320 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5346 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5458 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5415 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5191 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5426 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5272 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5284 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5390 # Number of bytes written to this memory +system.physmem.bytes_written::total 475102 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11251 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10988 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88405 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6755 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5346 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5415 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5191 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5272 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5284 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5390 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49537 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 346987764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 344717326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 340062929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 328082315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 323127895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 356345211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 343233433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 347226971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2729783843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1752777973 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 21674572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 22128660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 21954323 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 21046147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 21998920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 21374550 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 21423202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 21852964 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1926231311 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1752777973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 368662336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 366845986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 362017251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 349128462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 345126816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 377719761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 364656635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 369079934 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4656015154 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 13761 # number of replacements +system.l2c.tagsinuse 783.393170 # Cycle average of tags in use +system.l2c.total_refs 148641 # Total number of references to valid blocks. +system.l2c.sampled_refs 14595 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.184378 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 735.582494 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 6.455373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 6.652747 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 6.865494 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 6.639169 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.152690 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.266868 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.044725 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 6.723074 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.718342 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.006304 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.006497 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.006705 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.006484 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.006985 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007097 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.006880 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.006566 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.771858 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10736 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10598 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10639 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10768 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85297 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 74602 # number of Writeback hits -system.l2c.Writeback_hits::total 74602 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 364 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 337 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 366 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 372 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 359 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 320 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2793 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1921 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1802 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1826 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1884 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1935 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1883 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1847 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15016 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12416 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12424 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12523 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12437 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12615 # number of demand (read+write) hits -system.l2c.demand_hits::total 100313 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12657 # number of overall hits -system.l2c.overall_hits::cpu1 12416 # number of overall hits -system.l2c.overall_hits::cpu2 12424 # number of overall hits -system.l2c.overall_hits::cpu3 12574 # number of overall hits -system.l2c.overall_hits::cpu4 12523 # number of overall hits -system.l2c.overall_hits::cpu5 12437 # number of overall hits -system.l2c.overall_hits::cpu6 12667 # number of overall hits -system.l2c.overall_hits::cpu7 12615 # number of overall hits -system.l2c.overall_hits::total 100313 # number of overall hits -system.l2c.ReadReq_misses::cpu0 732 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 746 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 787 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 736 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 779 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 768 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 802 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 756 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6106 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1954 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1934 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2007 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1961 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1921 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2008 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1917 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1898 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15600 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4348 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4389 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4257 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4320 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4350 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4337 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4234 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4290 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34525 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5080 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5135 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5056 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5129 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5105 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5036 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5046 # number of demand (read+write) misses -system.l2c.demand_misses::total 40631 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5080 # number of overall misses -system.l2c.overall_misses::cpu1 5135 # number of overall misses -system.l2c.overall_misses::cpu2 5044 # number of overall misses -system.l2c.overall_misses::cpu3 5056 # number of overall misses -system.l2c.overall_misses::cpu4 5129 # number of overall misses -system.l2c.overall_misses::cpu5 5105 # number of overall misses -system.l2c.overall_misses::cpu6 5036 # number of overall misses -system.l2c.overall_misses::cpu7 5046 # number of overall misses -system.l2c.overall_misses::total 40631 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 36182301 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 37095182 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 38839912 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 36320452 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 38654457 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 37981477 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 39913673 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 37420167 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 302407621 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 51570624 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 52824724 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 55089368 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 54044648 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 51434616 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 55447032 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 51075446 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 51050152 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 422536610 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 217343370 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 219324999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 212745239 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 215838098 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 217293309 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 216702467 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 211504918 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 214216755 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1724969155 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 253525671 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 256420181 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 251585151 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 252158550 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 255947766 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 254683944 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 251418591 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 251636922 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2027376776 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 253525671 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 256420181 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 251585151 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 252158550 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 255947766 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 254683944 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 251418591 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 251636922 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2027376776 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11468 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11360 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11385 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11392 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11418 # 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number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1902 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15079 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4399 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4186 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4344 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4286 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4382 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4394 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4423 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34643 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5175 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 4974 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5108 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 4963 # 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number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 54472253 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 52324574 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 51552168 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 422857100 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 245296624 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 234887322 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 237706545 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 232669020 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 238760287 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 246249803 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 240187312 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 245760610 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11599 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11449 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91345 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 74327 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 74327 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2165 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2222 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2184 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2268 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2229 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2221 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2217 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17792 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6318 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6062 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6256 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6098 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6213 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6254 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6254 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6215 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 49670 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17644 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17486 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17622 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17663 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17400 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17853 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu6 17703 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17661 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 140944 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17737 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17551 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17468 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17630 # 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number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.063830 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.065669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.069126 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.064607 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.068226 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.068146 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.069221 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.065602 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.842968 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.853486 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.856229 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.851128 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.839965 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.843697 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.842267 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.855726 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.848149 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.693572 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.708932 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.699819 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.692530 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.697786 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.691486 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692169 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.699039 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.696898 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.286407 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.292576 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.288757 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.286784 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.290562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291016 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.284472 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.285714 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.288278 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.286407 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.292576 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.288757 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.286784 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.290562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291016 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.284472 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.285714 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.288278 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 49429.372951 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 49725.445040 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 49351.857687 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 49348.440217 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 49620.612323 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 49455.048177 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 49767.672070 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 49497.575397 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 49526.305437 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 26392.335722 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 27313.714581 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 27448.613852 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27559.738909 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 26774.917231 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 27613.063745 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 26643.425143 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 26896.813488 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 27085.680128 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 49986.975621 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 49971.519481 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 49975.390886 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 49962.522685 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 49952.484828 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 49965.982707 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 49953.924894 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 49933.975524 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 49962.900941 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 49906.628150 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 49935.770399 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 49878.102895 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 49873.130934 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 49902.079548 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 49889.117336 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 49924.263503 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 49868.593341 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 49897.289656 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 49906.628150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 49935.770399 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 49878.102895 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 49873.130934 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 49902.079548 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 49889.117336 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 49924.263503 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 49868.593341 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 49897.289656 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 96627 # number of cycles access was blocked +system.l2c.overall_accesses::cpu7 17644 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141015 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.068515 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.068978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.067218 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.063467 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.061947 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.069834 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.068827 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.068510 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.067174 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.835566 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.842034 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.847985 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.843034 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.844707 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.856886 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.851869 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.857916 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.847516 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.696265 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.690531 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.694373 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.693506 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.689844 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.700672 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.702590 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.711665 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.697463 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.293301 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.284456 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.289865 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.280983 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.286149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.290819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.292719 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.295058 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.289182 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.293301 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.284456 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.289865 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.280983 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.286149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.290819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.292719 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.295058 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.289182 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 86231.025773 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 85145.951777 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 94192.870419 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 92374.168937 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 90191.591631 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 86165.683951 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 91335.139594 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 91126.856960 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 89536.778846 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28982.305141 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 27889.094602 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 27838.458963 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27944.695607 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28436.838426 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28519.504188 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 27655.694503 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 27104.189274 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28042.781352 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55761.905888 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 56112.594840 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54720.659530 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55017.502956 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55707.019832 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 56195.756047 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54662.565316 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 55564.234682 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55466.256473 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 60330.801932 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 60712.169682 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 60624.490603 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 60542.345356 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 60506.740309 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 60871.341872 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 60239.174450 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 60912.973300 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 60592.834498 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 60330.801932 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 60712.169682 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 60624.490603 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 60542.345356 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 60506.740309 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 60871.341872 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 60239.174450 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 60912.973300 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 60592.834498 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 751039 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 19 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 217 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 5085.631579 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 3461.009217 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6616 # number of writebacks -system.l2c.writebacks::total 6616 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 23 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 19 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6755 # number of writebacks +system.l2c.writebacks::total 6755 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 14 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 16 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 25 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu0 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 4 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 12 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 13 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 9 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 12 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 11 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 10 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 15 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 85 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 24 # number of demand (read+write) MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 14 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 17 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 12 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 14 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 11 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 91 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 27 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 33 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 32 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 34 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 30 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 27 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 39 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 242 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 24 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu2 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 29 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 34 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 31 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 234 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 27 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 33 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 32 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 34 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 30 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 27 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 242 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 714 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 736 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 763 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 713 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 757 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 749 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 785 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 732 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5949 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1952 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1933 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2006 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1960 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1920 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2007 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1916 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1894 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15588 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4342 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4376 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4248 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4311 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4338 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4326 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4224 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4275 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34440 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5112 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5011 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5024 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5095 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5075 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5009 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5007 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40389 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5056 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5112 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5011 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5024 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5095 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5075 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5009 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5007 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40389 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 28564754 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 29444935 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 30526423 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 28524830 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 30284517 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 29963728 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 31404851 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 29284664 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 237998702 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78081132 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 77281042 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80241204 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78401138 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 76801198 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 80241160 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76640992 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75761030 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 623448896 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 173685720 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 175005460 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 169924253 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 172445652 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 173444745 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 173045540 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 168925276 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 170965174 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1377441820 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 202250474 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 204450395 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 200450676 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 200970482 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 203729262 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 203009268 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 200330127 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 200249838 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1615440522 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 202250474 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 204450395 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 200450676 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 200970482 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 203729262 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 203009268 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 200330127 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 200249838 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1615440522 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 400927744 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 396406972 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396807484 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 398767759 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 400808423 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 395927220 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 398767355 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 395367613 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3183780570 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 211603917 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215684252 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 216163665 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 212923402 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213723846 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 215924115 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217803639 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216444289 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1720271125 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 612531661 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 612091224 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 612971149 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 611691161 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 614532269 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 611851335 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 616570994 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 611811902 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4904051695 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.062260 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064789 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.067018 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.062588 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.066299 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066460 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.067754 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063520 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.065085 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842105 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.853045 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.855802 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850694 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.839528 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.843277 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841828 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853922 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.847496 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.692614 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.706832 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.698340 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.691087 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695861 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689732 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.690535 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696594 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.695182 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.286561 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.286561 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40006.658263 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40006.705163 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40008.418087 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40006.774194 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40005.966975 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40004.977303 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40006.179618 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 40006.371585 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.505631 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.579918 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39979.845835 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.600199 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.580612 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40000.623958 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39980.647733 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40000.517745 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.543823 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39995.438542 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40001.317365 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39992.106947 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 40001.001177 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40001.311065 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 39982.652144 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40001.280629 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 39991.779356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.853567 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39995.407085 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu2 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 29 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 34 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 31 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 234 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 763 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 774 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 751 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 717 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 677 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 785 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 768 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 758 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5993 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1807 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1871 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1852 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1911 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1931 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1910 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1892 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1902 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15076 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4385 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4177 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4327 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4217 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4272 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4373 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4383 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4418 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34552 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5148 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 4951 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5078 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 4934 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 4949 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5151 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5176 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40545 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5148 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 4951 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5078 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 4934 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 4949 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5151 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5176 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40545 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 58870730 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 58585309 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 63480686 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 59975234 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 54977009 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 60150971 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 63201488 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 61933736 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 481175163 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 75210107 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78015248 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77004240 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 79811462 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 80566647 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 79563303 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78963808 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 79283534 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 628418349 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 200402415 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 192724360 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 193590833 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189833874 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 195179728 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 201870094 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 195807052 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 201165400 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1570573756 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 259273145 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 251309669 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 257071519 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 249809108 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 250156737 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 262021065 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 259008540 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 263099136 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2051748919 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 259273145 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 251309669 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 257071519 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 249809108 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 250156737 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 262021065 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 259008540 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 263099136 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2051748919 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 422219130 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 432042675 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 419593939 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 421722054 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 422767760 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 422714984 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 423711086 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 417921325 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3382692953 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 236377012 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 240741589 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 239322336 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229099860 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 239042372 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 232239121 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 232671200 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 242872940 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1892366430 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 658596142 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 672784264 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 658916275 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 650821914 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 661810132 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 654954105 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 656382286 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 660794265 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5275059383 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.067367 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.067752 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.066074 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061997 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060517 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.067678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.067080 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.066323 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.065608 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.834642 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.842034 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.847985 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.842593 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.844707 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.856886 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.851869 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.857916 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847347 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.694049 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689047 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.691656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.691538 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687591 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.699232 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.700831 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.710861 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.695631 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.291771 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.283141 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.288163 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.279341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284425 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.288915 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.290968 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.293358 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.287523 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.291771 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.283141 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.288163 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.279341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284425 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.288915 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.290968 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.293358 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.287523 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 77156.920052 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 75691.613695 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 84528.210386 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 83647.467225 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 81206.807976 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 76625.440764 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 82293.604167 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 81706.775726 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 80289.531620 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41621.531267 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41697.086050 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41578.963283 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41764.239665 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41722.758674 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41656.179581 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41735.627907 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41684.297581 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41683.360905 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45701.805017 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46139.420637 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44740.197134 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45016.332464 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45688.138577 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46162.838783 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44674.207620 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45533.137166 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 45455.364552 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 50363.858780 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 50759.375682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 50624.560654 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 50630.139441 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 50546.926046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 50798.965684 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 50283.156669 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 50830.590417 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 50604.240202 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 50363.858780 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 50759.375682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 50624.560654 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 50630.139441 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 50546.926046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 50798.965684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 50283.156669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 50830.590417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 50604.240202 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -663,114 +657,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 99016 # number of read accesses completed -system.cpu0.num_writes 53340 # number of write accesses completed +system.cpu0.num_reads 98266 # number of read accesses completed +system.cpu0.num_writes 53265 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 21906 # number of replacements -system.cpu0.l1c.tagsinuse 396.590239 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13140 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22312 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.588921 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 21972 # number of replacements +system.cpu0.l1c.tagsinuse 389.500163 # Cycle average of tags in use +system.cpu0.l1c.total_refs 12866 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22378 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.574940 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 396.590239 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.774590 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.774590 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8561 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8561 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1051 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1051 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9612 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9612 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9612 # number of overall hits -system.cpu0.l1c.overall_hits::total 9612 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35875 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35875 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23186 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23186 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 59061 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 59061 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 59061 # number of overall misses -system.cpu0.l1c.overall_misses::total 59061 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 894906998 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 894906998 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 820039819 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 820039819 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1714946817 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1714946817 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1714946817 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1714946817 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44436 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44436 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24237 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24237 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68673 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68673 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68673 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68673 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807341 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956637 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956637 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860032 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860032 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860032 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860032 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 24945.142801 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 24945.142801 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 35367.886613 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 35367.886613 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 29036.874029 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 29036.874029 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 29036.874029 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 29036.874029 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 154642800 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 389.500163 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.760743 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.760743 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8421 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8421 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1069 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1069 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9490 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9490 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9490 # number of overall hits +system.cpu0.l1c.overall_hits::total 9490 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35688 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35688 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23099 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23099 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58787 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58787 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58787 # number of overall misses +system.cpu0.l1c.overall_misses::total 58787 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1012085750 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1012085750 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 897172564 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 897172564 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1909258314 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1909258314 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1909258314 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1909258314 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44109 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44109 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24168 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24168 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68277 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68277 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68277 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68277 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809087 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809087 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955768 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955768 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861007 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861007 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861007 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861007 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 28359.273425 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 28359.273425 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38840.320533 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 38840.320533 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 32477.559903 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 32477.559903 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 32477.559903 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 32477.559903 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 171686674 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 52409 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 2910.978089 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3275.900590 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks -system.cpu0.l1c.writebacks::total 9551 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35875 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35875 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23186 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 59061 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 59061 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 59061 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 59061 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 858892486 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 858892486 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 796764078 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 796764078 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1655656564 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1655656564 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1655656564 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1655656564 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 681029068 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 681029068 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 670499371 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 670499371 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1351528439 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1351528439 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807341 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956637 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956637 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860032 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860032 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 23941.253965 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 23941.253965 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34364.016130 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34364.016130 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9624 # number of writebacks +system.cpu0.l1c.writebacks::total 9624 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35688 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35688 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23099 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23099 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58787 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58787 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58787 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58787 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 976260004 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 976260004 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 873984178 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 873984178 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1850244182 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1850244182 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1850244182 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1850244182 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 721713598 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 721713598 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 736436829 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 736436829 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1458150427 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1458150427 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809087 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809087 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955768 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955768 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861007 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861007 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861007 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861007 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 27355.413696 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 27355.413696 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37836.450842 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37836.450842 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 31473.696259 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 31473.696259 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 31473.696259 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 31473.696259 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -778,114 +772,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99689 # number of read accesses completed -system.cpu1.num_writes 53832 # number of write accesses completed +system.cpu1.num_reads 99239 # number of read accesses completed +system.cpu1.num_writes 53491 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21971 # number of replacements -system.cpu1.l1c.tagsinuse 397.434568 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13255 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22377 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.592349 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21775 # number of replacements +system.cpu1.l1c.tagsinuse 388.085808 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13330 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22170 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.601263 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 397.434568 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.776239 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.776239 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8630 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8630 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1103 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1103 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9733 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9733 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9733 # number of overall hits -system.cpu1.l1c.overall_hits::total 9733 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36139 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36139 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23155 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23155 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 59294 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 59294 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 59294 # number of overall misses -system.cpu1.l1c.overall_misses::total 59294 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 902705787 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 902705787 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 819450505 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 819450505 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1722156292 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1722156292 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1722156292 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1722156292 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44769 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44769 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24258 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24258 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 69027 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 69027 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 69027 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 69027 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807233 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807233 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954530 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954530 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858997 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858997 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858997 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858997 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 24978.715155 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 24978.715155 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 35389.786439 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 35389.786439 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 29044.360171 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 29044.360171 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 29044.360171 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 29044.360171 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 155390130 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 388.085808 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.757980 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.757980 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8854 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8854 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1044 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1044 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9898 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9898 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9898 # number of overall hits +system.cpu1.l1c.overall_hits::total 9898 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35763 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35763 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22917 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22917 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58680 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58680 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58680 # number of overall misses +system.cpu1.l1c.overall_misses::total 58680 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1015131417 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1015131417 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 886463982 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 886463982 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1901595399 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1901595399 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1901595399 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1901595399 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44617 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44617 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23961 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23961 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68578 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68578 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68578 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68578 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.801555 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.801555 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956429 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.956429 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.855668 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.855668 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.855668 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.855668 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 28384.962587 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 28384.962587 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38681.502029 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 38681.502029 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 32406.192894 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 32406.192894 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 32406.192894 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 32406.192894 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 173063141 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 53247 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 53052 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 2918.288918 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3262.141691 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks -system.cpu1.l1c.writebacks::total 9603 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36139 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36139 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23155 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23155 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 59294 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 59294 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 59294 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 59294 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 866427236 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 866427236 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 796207895 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 796207895 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1662635131 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1662635131 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1662635131 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1662635131 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 674093801 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 674093801 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 675943433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 675943433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1350037234 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1350037234 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807233 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807233 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954530 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954530 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858997 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858997 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23974.853648 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23974.853648 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34386.002807 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34386.002807 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9480 # number of writebacks +system.cpu1.l1c.writebacks::total 9480 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22917 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22917 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58680 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58680 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58680 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58680 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 979228369 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 979228369 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 863458324 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 863458324 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1842686693 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1842686693 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1842686693 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1842686693 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 740677115 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740677115 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 739780589 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 739780589 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1480457704 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1480457704 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.801555 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.801555 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956429 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956429 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.855668 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.855668 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.855668 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.855668 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 27381.046584 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 27381.046584 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37677.633373 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37677.633373 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 31402.295382 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 31402.295382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 31402.295382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 31402.295382 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -893,114 +887,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99864 # number of read accesses completed -system.cpu2.num_writes 53679 # number of write accesses completed +system.cpu2.num_reads 98639 # number of read accesses completed +system.cpu2.num_writes 53360 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22117 # number of replacements -system.cpu2.l1c.tagsinuse 397.846327 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13470 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22518 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.598188 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 21788 # number of replacements +system.cpu2.l1c.tagsinuse 389.777022 # Cycle average of tags in use +system.cpu2.l1c.total_refs 12892 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22192 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.580930 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 397.846327 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.777044 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.777044 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8720 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8720 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1090 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1090 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9810 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9810 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9810 # number of overall hits -system.cpu2.l1c.overall_hits::total 9810 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36026 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36026 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23186 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23186 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59212 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59212 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59212 # number of overall misses -system.cpu2.l1c.overall_misses::total 59212 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 899117648 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 899117648 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 813653609 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 813653609 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1712771257 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1712771257 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1712771257 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1712771257 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44746 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44746 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24276 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24276 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 69022 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 69022 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 69022 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 69022 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805122 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805122 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955100 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955100 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.857871 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.857871 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.857871 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.857871 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 24957.465386 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 24957.465386 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 35092.452730 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 35092.452730 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 28926.083513 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 28926.083513 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 28926.083513 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 28926.083513 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 153072251 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 389.777022 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.761283 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.761283 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8419 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8419 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1037 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1037 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9456 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9456 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9456 # number of overall hits +system.cpu2.l1c.overall_hits::total 9456 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35792 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35792 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22886 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22886 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58678 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58678 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58678 # number of overall misses +system.cpu2.l1c.overall_misses::total 58678 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1023256428 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1023256428 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 895299843 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 895299843 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1918556271 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1918556271 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1918556271 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1918556271 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44211 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44211 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23923 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23923 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68134 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68134 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68134 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68134 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.809572 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.809572 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.956653 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.956653 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.861215 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.861215 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.861215 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.861215 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 28588.970384 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 28588.970384 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 39119.979158 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 39119.979158 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 32696.347370 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 32696.347370 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 32696.347370 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 32696.347370 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 172516137 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 52648 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 52707 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 2907.465640 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3273.116227 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9600 # number of writebacks -system.cpu2.l1c.writebacks::total 9600 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36026 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36026 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23186 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59212 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59212 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59212 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59212 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 862954550 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 862954550 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 790376865 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 790376865 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1653331415 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1653331415 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1653331415 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1653331415 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 676110998 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 676110998 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 681557695 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 681557695 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1357668693 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1357668693 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805122 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805122 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955100 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955100 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.857871 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.857871 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 23953.659857 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 23953.659857 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34088.538989 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34088.538989 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9481 # number of writebacks +system.cpu2.l1c.writebacks::total 9481 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22886 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22886 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58678 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58678 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58678 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58678 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 987321254 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 987321254 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 872322294 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 872322294 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1859643548 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1859643548 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1859643548 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1859643548 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 722326579 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 722326579 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 745926521 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 745926521 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1468253100 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1468253100 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.809572 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.809572 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.956653 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.956653 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861215 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.861215 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861215 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.861215 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 27584.970217 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 27584.970217 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 38115.978939 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 38115.978939 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 31692.347183 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 31692.347183 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 31692.347183 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 31692.347183 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1008,114 +1002,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98954 # number of read accesses completed -system.cpu3.num_writes 53519 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53214 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 21866 # number of replacements -system.cpu3.l1c.tagsinuse 395.683419 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13218 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22277 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.593347 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 22201 # number of replacements +system.cpu3.l1c.tagsinuse 390.202631 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13426 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22601 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.594045 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.683419 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.772819 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.772819 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1098 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9660 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9660 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9660 # number of overall hits -system.cpu3.l1c.overall_hits::total 9660 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35996 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35996 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23029 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23029 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59025 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59025 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59025 # number of overall misses -system.cpu3.l1c.overall_misses::total 59025 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 899058428 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 899058428 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 817455350 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 817455350 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1716513778 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1716513778 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1716513778 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1716513778 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44558 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44558 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24127 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68685 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68685 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68685 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68685 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807846 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807846 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954491 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954491 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859358 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859358 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859358 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859358 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 24976.620402 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 24976.620402 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 35496.780147 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 35496.780147 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 29081.131351 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 29081.131351 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 29081.131351 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 29081.131351 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 155038956 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 390.202631 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.762115 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.762115 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8779 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8779 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1080 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1080 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9859 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9859 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9859 # number of overall hits +system.cpu3.l1c.overall_hits::total 9859 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36255 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36255 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22971 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22971 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59226 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59226 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59226 # number of overall misses +system.cpu3.l1c.overall_misses::total 59226 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1029467396 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1029467396 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 892890764 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 892890764 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1922358160 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1922358160 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1922358160 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1922358160 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45034 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45034 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24051 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24051 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 69085 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 69085 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 69085 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 69085 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805058 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805058 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955095 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955095 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.857292 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.857292 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.857292 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.857292 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 28395.184002 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 28395.184002 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38870.348004 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 38870.348004 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 32458.011009 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 32458.011009 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 32458.011009 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 32458.011009 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 173404945 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 53526 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 2918.435283 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3239.639521 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9442 # number of writebacks -system.cpu3.l1c.writebacks::total 9442 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35996 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35996 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23029 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23029 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59025 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59025 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59025 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59025 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 862924447 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 862924447 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 794336234 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 794336234 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1657260681 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1657260681 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1657260681 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1657260681 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 680106792 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 680106792 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 674669668 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 674669668 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1354776460 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1354776460 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807846 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807846 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954491 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954491 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859358 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859358 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23972.787171 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23972.787171 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34492.866994 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34492.866994 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9609 # number of writebacks +system.cpu3.l1c.writebacks::total 9609 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36255 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36255 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22971 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22971 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59226 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59226 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59226 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59226 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 993072387 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 993072387 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 869829882 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 869829882 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1862902269 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1862902269 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1862902269 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1862902269 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 723358193 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 723358193 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 722023340 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 722023340 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1445381533 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1445381533 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805058 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805058 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955095 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955095 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857292 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.857292 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857292 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.857292 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 27391.322218 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 27391.322218 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37866.435157 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37866.435157 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 31454.129420 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 31454.129420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 31454.129420 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 31454.129420 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1123,114 +1117,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99591 # number of read accesses completed -system.cpu4.num_writes 53646 # number of write accesses completed +system.cpu4.num_reads 98672 # number of read accesses completed +system.cpu4.num_writes 53449 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22293 # number of replacements -system.cpu4.l1c.tagsinuse 397.816545 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13327 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22684 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.587507 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 21899 # number of replacements +system.cpu4.l1c.tagsinuse 389.567143 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13162 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22307 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.590039 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 397.816545 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.776985 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.776985 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8743 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8743 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1036 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1036 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9779 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9779 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9779 # number of overall hits -system.cpu4.l1c.overall_hits::total 9779 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35998 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35998 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23232 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23232 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59230 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59230 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59230 # number of overall misses -system.cpu4.l1c.overall_misses::total 59230 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 899681935 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 899681935 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 816003996 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 816003996 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1715685931 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1715685931 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1715685931 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1715685931 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44741 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44741 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24268 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24268 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69009 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69009 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69009 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69009 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804586 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804586 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.957310 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.957310 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858294 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858294 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858294 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858294 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 24992.553336 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 24992.553336 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 35124.138946 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 35124.138946 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 28966.502296 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 28966.502296 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 28966.502296 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 28966.502296 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 154355931 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 389.567143 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.760873 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.760873 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8516 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8516 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1086 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1086 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9602 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9602 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9602 # number of overall hits +system.cpu4.l1c.overall_hits::total 9602 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 35797 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 35797 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23063 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23063 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 58860 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 58860 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 58860 # number of overall misses +system.cpu4.l1c.overall_misses::total 58860 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1014475710 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1014475710 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 905483061 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 905483061 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1919958771 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1919958771 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1919958771 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1919958771 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44313 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44313 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24149 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24149 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68462 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68462 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68462 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68462 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807822 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807822 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955029 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.955029 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859747 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859747 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859747 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859747 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 28339.685169 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 28339.685169 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 39261.286953 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 39261.286953 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 32619.075280 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 32619.075280 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 32619.075280 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 32619.075280 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 173090211 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 53171 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 52926 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 2903.009742 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3270.419284 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9702 # number of writebacks -system.cpu4.l1c.writebacks::total 9702 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35998 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35998 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23232 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23232 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59230 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59230 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59230 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59230 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 863541936 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 863541936 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 792684079 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 792684079 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1656226015 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1656226015 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1656226015 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1656226015 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 681350371 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 681350371 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 669996228 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 669996228 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1351346599 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1351346599 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804586 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804586 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.957310 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.957310 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858294 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858294 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 23988.608700 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 23988.608700 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34120.354640 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34120.354640 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9537 # number of writebacks +system.cpu4.l1c.writebacks::total 9537 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35797 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 35797 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23063 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23063 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 58860 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 58860 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 58860 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 58860 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 978543547 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 978543547 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 882330817 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 882330817 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1860874364 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1860874364 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1860874364 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1860874364 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 726225983 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 726225983 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 739406150 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 739406150 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1465632133 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1465632133 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807822 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807822 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955029 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859747 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859747 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859747 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859747 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 27335.909350 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 27335.909350 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 38257.417378 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 38257.417378 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 31615.262725 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 31615.262725 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 31615.262725 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 31615.262725 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1238,114 +1232,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99523 # number of read accesses completed -system.cpu5.num_writes 53948 # number of write accesses completed +system.cpu5.num_reads 98938 # number of read accesses completed +system.cpu5.num_writes 52979 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22088 # number of replacements -system.cpu5.l1c.tagsinuse 397.555659 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13442 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22486 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.597794 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22003 # number of replacements +system.cpu5.l1c.tagsinuse 389.145531 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13186 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22409 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.588424 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 397.555659 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.776476 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.776476 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8700 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8700 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1066 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1066 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9766 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9766 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9766 # number of overall hits -system.cpu5.l1c.overall_hits::total 9766 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36016 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36016 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23333 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23333 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59349 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59349 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59349 # number of overall misses -system.cpu5.l1c.overall_misses::total 59349 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 899040098 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 899040098 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 826704780 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 826704780 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1725744878 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1725744878 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1725744878 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1725744878 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44716 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44716 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24399 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24399 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69115 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69115 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69115 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69115 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805439 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.805439 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956310 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.956310 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858699 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858699 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858699 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858699 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 24962.241726 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 24962.241726 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 35430.711010 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 35430.711010 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 29077.909956 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 29077.909956 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 29077.909956 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 29077.909956 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 155795508 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 389.145531 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.760050 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.760050 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1030 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1030 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9667 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9667 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9667 # number of overall hits +system.cpu5.l1c.overall_hits::total 9667 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36114 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36114 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22950 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22950 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59064 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59064 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59064 # number of overall misses +system.cpu5.l1c.overall_misses::total 59064 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1023713867 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1023713867 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 899864913 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 899864913 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1923578780 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1923578780 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1923578780 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1923578780 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44751 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44751 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 23980 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 23980 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68731 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68731 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68731 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68731 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806999 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806999 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.957048 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.957048 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859350 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859350 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859350 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859350 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 28346.731655 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 28346.731655 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 39209.800131 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 39209.800131 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 32567.702492 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 32567.702492 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 32567.702492 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 32567.702492 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 172870705 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 53352 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 53593 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 2920.143725 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3225.620977 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9610 # number of writebacks -system.cpu5.l1c.writebacks::total 9610 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36016 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36016 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23333 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23333 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59349 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59349 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59349 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59349 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 862885041 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 862885041 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 803284460 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 803284460 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1666169501 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1666169501 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1666169501 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1666169501 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 674425818 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 674425818 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 675374924 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 675374924 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1349800742 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1349800742 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805439 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805439 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956310 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956310 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858699 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858699 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 23958.380747 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 23958.380747 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 34426.968671 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 34426.968671 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9578 # number of writebacks +system.cpu5.l1c.writebacks::total 9578 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36114 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36114 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22950 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22950 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59064 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59064 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59064 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59064 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 987460421 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 987460421 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 876826122 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 876826122 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1864286543 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1864286543 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1864286543 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1864286543 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 726267830 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 726267830 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 727074165 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 727074165 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1453341995 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1453341995 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806999 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806999 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.957048 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.957048 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859350 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859350 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859350 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859350 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 27342.870383 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 27342.870383 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 38205.931242 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 38205.931242 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 31563.838260 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 31563.838260 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 31563.838260 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 31563.838260 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1353,114 +1347,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 53510 # number of write accesses completed +system.cpu6.num_reads 98714 # number of read accesses completed +system.cpu6.num_writes 53264 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 22177 # number of replacements -system.cpu6.l1c.tagsinuse 397.660479 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13364 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22573 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.592035 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 21950 # number of replacements +system.cpu6.l1c.tagsinuse 389.196991 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13256 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22357 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.592924 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 397.660479 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.776681 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.776681 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8760 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8760 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1035 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1035 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9795 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9795 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9795 # number of overall hits -system.cpu6.l1c.overall_hits::total 9795 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36279 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36279 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23033 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23033 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 59312 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 59312 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 59312 # number of overall misses -system.cpu6.l1c.overall_misses::total 59312 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 908517794 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 908517794 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 809582336 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 809582336 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1718100130 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1718100130 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1718100130 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1718100130 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45039 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45039 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24068 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24068 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 69107 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 69107 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 69107 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 69107 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805502 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805502 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956997 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.956997 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858263 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858263 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858263 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858263 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 25042.525814 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 25042.525814 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 35148.801111 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 35148.801111 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 28967.158922 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 28967.158922 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 28967.158922 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 28967.158922 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 154185284 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 389.196991 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.760150 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.760150 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8708 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8708 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1082 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1082 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9790 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9790 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9790 # number of overall hits +system.cpu6.l1c.overall_hits::total 9790 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35839 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35839 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23075 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23075 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58914 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58914 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58914 # number of overall misses +system.cpu6.l1c.overall_misses::total 58914 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1020128042 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1020128042 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 903798683 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 903798683 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1923926725 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1923926725 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1923926725 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1923926725 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44547 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44547 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24157 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24157 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68704 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68704 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68704 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68704 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804521 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.804521 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955210 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.955210 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.857505 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.857505 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.857505 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.857505 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 28464.188231 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 28464.188231 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 39167.873586 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 39167.873586 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 32656.528584 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 32656.528584 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 32656.528584 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 32656.528584 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 174295545 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 52977 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 53485 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 2910.419314 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3258.774329 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9564 # number of writebacks -system.cpu6.l1c.writebacks::total 9564 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36279 # 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number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1658558882 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1658558882 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1658558882 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 680107967 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 680107967 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 681972539 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 681972539 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1362080506 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1362080506 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805502 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805502 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956997 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956997 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858263 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858263 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24038.635878 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24038.635878 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34144.975079 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34144.975079 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9548 # number of writebacks +system.cpu6.l1c.writebacks::total 9548 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35839 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35839 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23075 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23075 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58914 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58914 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 984150696 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 984150696 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 880635396 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 880635396 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1864786092 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1864786092 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1864786092 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1864786092 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 725723754 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 725723754 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 729548625 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 729548625 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1455272379 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1455272379 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804521 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804521 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955210 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955210 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857505 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.857505 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857505 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.857505 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 27460.328023 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 27460.328023 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 38164.047497 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 38164.047497 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 31652.681739 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 31652.681739 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 31652.681739 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 31652.681739 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1468,114 +1462,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99201 # number of read accesses completed -system.cpu7.num_writes 53497 # number of write accesses completed +system.cpu7.num_reads 98633 # number of read accesses completed +system.cpu7.num_writes 53420 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22218 # number of replacements -system.cpu7.l1c.tagsinuse 396.828031 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13271 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22622 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.586641 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 21845 # number of replacements +system.cpu7.l1c.tagsinuse 390.265182 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13266 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22252 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.596171 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 396.828031 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.775055 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.775055 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8703 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8703 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1096 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1096 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9799 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9799 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9799 # number of overall hits -system.cpu7.l1c.overall_hits::total 9799 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36453 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36453 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22910 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22910 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59363 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59363 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59363 # number of overall misses -system.cpu7.l1c.overall_misses::total 59363 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 908883238 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 908883238 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 808946616 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 808946616 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1717829854 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1717829854 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1717829854 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1717829854 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45156 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45156 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69162 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69162 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69162 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69162 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807268 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954345 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954345 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858318 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858318 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858318 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858318 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 24933.016158 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 24933.016158 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 35309.760629 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 35309.760629 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 28937.719691 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 28937.719691 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 28937.719691 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 28937.719691 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 153732048 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 390.265182 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.762237 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.762237 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8641 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8641 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1118 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1118 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9759 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9759 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9759 # number of overall hits +system.cpu7.l1c.overall_hits::total 9759 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35823 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35823 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22965 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22965 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 58788 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 58788 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 58788 # number of overall misses +system.cpu7.l1c.overall_misses::total 58788 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1021778024 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1021778024 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 908326044 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 908326044 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1930104068 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1930104068 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1930104068 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1930104068 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44464 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44464 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68547 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68547 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68547 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68547 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805663 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805663 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953577 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953577 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857631 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857631 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857631 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857631 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 28522.960779 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 28522.960779 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 39552.625474 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 39552.625474 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 32831.599442 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 32831.599442 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 32831.599442 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 32831.599442 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 173409503 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 53029 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 52851 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 2899.018424 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3281.101644 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9581 # number of writebacks -system.cpu7.l1c.writebacks::total 9581 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36453 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36453 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22910 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22910 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59363 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59363 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59363 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59363 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 872289420 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 872289420 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 785947981 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 785947981 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1658237401 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1658237401 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1658237401 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1658237401 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 674384984 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 674384984 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 681937361 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 681937361 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1356322345 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1356322345 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807268 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954345 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954345 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858318 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858318 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23929.153156 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23929.153156 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34305.891794 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34305.891794 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9467 # number of writebacks +system.cpu7.l1c.writebacks::total 9467 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35823 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35823 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22965 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 58788 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 58788 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 58788 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 58788 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 985813733 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 985813733 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 885270188 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 885270188 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1871083921 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1871083921 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1871083921 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1871083921 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 719750432 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 719750432 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 746183664 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 746183664 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1465934096 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1465934096 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805663 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805663 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953577 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953577 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857631 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857631 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857631 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857631 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 27519.016637 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 27519.016637 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 38548.669192 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 38548.669192 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 31827.650558 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 31827.650558 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 31827.650558 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 31827.650558 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |