diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
| commit | f125ef22b997d5ba6173d9d3f0d07ae741e279bd (patch) | |
| tree | d3d103939211116d7f8ed7e04db73fbac0b9e9be /tests/quick | |
| parent | d0e04859023702ec23c97683700c638949a1dad1 (diff) | |
| download | gem5-f125ef22b997d5ba6173d9d3f0d07ae741e279bd.tar.xz | |
O3: Update stats for LSQ changes.
Diffstat (limited to 'tests/quick')
18 files changed, 3458 insertions, 3459 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index f022a446d..fa9debdd1 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 15:20:58 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 20:03:54 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12002500 because target called exit() +Exiting @ tick 12003500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 50d6ec22a..a8b7869e5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12002500 # Number of ticks simulated +sim_ticks 12003500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25819 # Simulator instruction rate (inst/s) -host_tick_rate 48521023 # Simulator tick rate (ticks/s) -host_mem_usage 243716 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 47992 # Simulator instruction rate (inst/s) +host_tick_rate 90187460 # Simulator tick rate (ticks/s) +host_mem_usage 243780 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1863 # DTB read hits +system.cpu.dtb.read_hits 1860 # DTB read hits system.cpu.dtb.read_misses 45 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1908 # DTB read accesses -system.cpu.dtb.write_hits 1047 # DTB write hits +system.cpu.dtb.read_accesses 1905 # DTB read accesses +system.cpu.dtb.write_hits 1043 # DTB write hits system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1075 # DTB write accesses -system.cpu.dtb.data_hits 2910 # DTB hits +system.cpu.dtb.write_accesses 1071 # DTB write accesses +system.cpu.dtb.data_hits 2903 # DTB hits system.cpu.dtb.data_misses 73 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2983 # DTB accesses -system.cpu.itb.fetch_hits 2044 # ITB hits +system.cpu.dtb.data_accesses 2976 # DTB accesses +system.cpu.itb.fetch_hits 2041 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2073 # ITB accesses +system.cpu.itb.fetch_accesses 2070 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,102 +41,102 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24006 # number of cpu cycles simulated +system.cpu.numCycles 24008 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2516 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1462 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2505 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1456 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1947 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 723 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1935 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 719 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 372 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7155 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14481 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2516 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1095 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2626 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1554 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14447 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1092 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1555 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2044 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.149103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.531397 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2041 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.147407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.529389 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9976 79.16% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.17% 81.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 231 1.83% 83.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 220 1.75% 84.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 235 1.86% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 176 1.40% 88.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.04% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.12% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1092 8.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9972 79.20% 79.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 273 2.17% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 226 1.79% 83.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.76% 84.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 235 1.87% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 177 1.41% 88.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 258 2.05% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.12% 91.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1087 8.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.104807 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.603224 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7976 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 12591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.104340 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.601758 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7971 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2455 # Number of cycles decode is running +system.cpu.decode.RunCycles 2448 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 976 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 216 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 977 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13403 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13375 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8164 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 977 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2326 # Number of cycles rename is running +system.cpu.rename.RunCycles 2318 # Number of cycles rename is running system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12866 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12830 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9599 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16086 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 16069 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9571 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16046 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16029 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5016 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4988 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2397 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1265 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2392 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1263 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11550 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9768 # Number of instructions issued +system.cpu.iq.iqInstsIssued 9758 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4900 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2850 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4875 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2832 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12602 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.775115 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397410 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12591 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.774998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.396796 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8516 67.58% 67.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1470 11.66% 79.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1066 8.46% 87.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 684 5.43% 93.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 441 3.50% 96.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 254 2.02% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8508 67.57% 67.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1466 11.64% 79.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1070 8.50% 87.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 438 3.48% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 253 2.01% 98.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 129 1.02% 99.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 30 0.24% 99.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12591 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 13 12.38% 12.38% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 12.38% # attempts to use FU when none available @@ -172,114 +172,114 @@ system.cpu.iq.fu_full::MemWrite 38 36.19% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6583 67.39% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2078 21.27% 88.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1102 11.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6577 67.40% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2074 21.25% 88.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1102 11.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9768 # Type of FU issued -system.cpu.iq.rate 0.406898 # Inst issue rate +system.cpu.iq.FU_type_0::total 9758 # Type of FU issued +system.cpu.iq.rate 0.406448 # Inst issue rate system.cpu.iq.fu_busy_cnt 105 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010749 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32267 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16511 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8987 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010760 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32236 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16459 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8983 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9860 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9850 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1212 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1207 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 400 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 398 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 976 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 977 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11685 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2397 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1265 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11657 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2392 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1263 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 445 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9324 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1918 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 446 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9316 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1915 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 80 # number of nop insts executed -system.cpu.iew.exec_refs 2995 # number of memory reference insts executed -system.cpu.iew.exec_branches 1503 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.388403 # Inst execution rate -system.cpu.iew.wb_sent 9127 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8997 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4717 # num instructions producing a value -system.cpu.iew.wb_consumers 6401 # num instructions consuming a value +system.cpu.iew.exec_refs 2988 # number of memory reference insts executed +system.cpu.iew.exec_branches 1504 # Number of branches executed +system.cpu.iew.exec_stores 1073 # Number of stores executed +system.cpu.iew.exec_rate 0.388037 # Inst execution rate +system.cpu.iew.wb_sent 9122 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8993 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4720 # num instructions producing a value +system.cpu.iew.wb_consumers 6405 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374781 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736916 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374583 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736924 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5279 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5251 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11626 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.550748 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.411308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.413328 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8945 76.94% 76.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1414 12.16% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 463 3.98% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 244 2.10% 95.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 156 1.34% 96.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 87 0.75% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 110 0.95% 98.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.38% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 241 2.08% 95.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 158 1.36% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.39% 98.60% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 163 1.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle system.cpu.commit.count 6403 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2050 # Number of memory references committed @@ -291,48 +291,48 @@ system.cpu.commit.int_insts 6321 # Nu system.cpu.commit.function_calls 127 # Number of function calls committed. system.cpu.commit.bw_lim_events 163 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22794 # The number of ROB reads -system.cpu.rob.rob_writes 24351 # The number of ROB writes +system.cpu.rob.rob_reads 22754 # The number of ROB reads +system.cpu.rob.rob_writes 24296 # The number of ROB writes system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11417 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.759161 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.759161 # CPI: Total CPI of All Threads -system.cpu.ipc 0.266017 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.266017 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11850 # number of integer regfile reads -system.cpu.int_regfile_writes 6735 # number of integer regfile writes +system.cpu.cpi 3.759474 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.759474 # CPI: Total CPI of All Threads +system.cpu.ipc 0.265995 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.265995 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11838 # number of integer regfile reads +system.cpu.int_regfile_writes 6732 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.654959 # Cycle average of tags in use -system.cpu.icache.total_refs 1612 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 159.648657 # Cycle average of tags in use +system.cpu.icache.total_refs 1609 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.183280 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.173633 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 159.654959 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.077957 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1612 # number of ReadReq hits -system.cpu.icache.demand_hits 1612 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1612 # number of overall hits +system.cpu.icache.occ_blocks::0 159.648657 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.077953 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1609 # number of ReadReq hits +system.cpu.icache.demand_hits 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1609 # number of overall hits system.cpu.icache.ReadReq_misses 432 # number of ReadReq misses system.cpu.icache.demand_misses 432 # number of demand (read+write) misses system.cpu.icache.overall_misses 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15402000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15402000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15402000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2044 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2044 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2044 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.211350 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.211350 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.211350 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35652.777778 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35652.777778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35652.777778 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 15393500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15393500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15393500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2041 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2041 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.211661 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.211661 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.211661 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35633.101852 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35633.101852 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35633.101852 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,52 +349,52 @@ system.cpu.icache.ReadReq_mshr_misses 311 # nu system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10985500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10985500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10985500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10986500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10986500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10986500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.152153 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.152153 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.152153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.151125 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.152376 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.152376 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.152376 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35326.366559 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35326.366559 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35326.366559 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.289403 # Cycle average of tags in use -system.cpu.dcache.total_refs 2155 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.288630 # Cycle average of tags in use +system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.385057 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 109.289403 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 109.288630 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1646 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1645 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits -system.cpu.dcache.demand_hits 2155 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2155 # number of overall hits -system.cpu.dcache.ReadReq_misses 155 # number of ReadReq misses +system.cpu.dcache.demand_hits 2154 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2154 # number of overall hits +system.cpu.dcache.ReadReq_misses 154 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5502500 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5497000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 17970000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 17970000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1801 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 17964500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 17964500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1799 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2666 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2666 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.086063 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2664 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.085603 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.191673 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.191673 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate 0.191441 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191441 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35694.805195 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35166.340509 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35166.340509 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35224.509804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35224.509804 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -404,10 +404,10 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 336 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses @@ -418,10 +418,10 @@ system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 system.cpu.dcache.demand_mshr_miss_latency 6265500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 6265500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056080 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056142 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.065266 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.065266 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate 0.065315 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.065315 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency @@ -431,12 +431,12 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.186144 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.178797 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 411 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002433 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.186144 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 221.178797 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.006750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits @@ -445,10 +445,10 @@ system.cpu.l2cache.ReadReq_misses 411 # nu system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.demand_misses 484 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 484 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14128000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14129000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16641500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16641500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 16642500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16642500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 412 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses @@ -457,10 +457,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.997573 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.997938 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.997938 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34374.695864 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34377.128954 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34383.264463 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34383.264463 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34385.330579 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34385.330579 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 74424d63b..b62422ecd 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 15:21:09 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 20:04:15 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 6921000 because target called exit() +Exiting @ tick 6833000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 5e52ef944..886aae88f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6921000 # Number of ticks simulated +sim_ticks 6833000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33894 # Simulator instruction rate (inst/s) -host_tick_rate 98227338 # Simulator tick rate (ticks/s) -host_mem_usage 242788 # Number of bytes of host memory used +host_inst_rate 36521 # Simulator instruction rate (inst/s) +host_tick_rate 104491306 # Simulator tick rate (ticks/s) +host_mem_usage 242860 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 720 # DTB read hits -system.cpu.dtb.read_misses 34 # DTB read misses +system.cpu.dtb.read_hits 679 # DTB read hits +system.cpu.dtb.read_misses 26 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 754 # DTB read accesses -system.cpu.dtb.write_hits 354 # DTB write hits -system.cpu.dtb.write_misses 22 # DTB write misses +system.cpu.dtb.read_accesses 705 # DTB read accesses +system.cpu.dtb.write_hits 356 # DTB write hits +system.cpu.dtb.write_misses 18 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 376 # DTB write accesses -system.cpu.dtb.data_hits 1074 # DTB hits -system.cpu.dtb.data_misses 56 # DTB misses +system.cpu.dtb.write_accesses 374 # DTB write accesses +system.cpu.dtb.data_hits 1035 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1130 # DTB accesses -system.cpu.itb.fetch_hits 976 # ITB hits +system.cpu.dtb.data_accesses 1079 # DTB accesses +system.cpu.itb.fetch_hits 945 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1006 # ITB accesses +system.cpu.itb.fetch_accesses 975 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,245 +41,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13843 # number of cpu cycles simulated +system.cpu.numCycles 13667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1112 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 583 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 236 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 781 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 240 # Number of BTB hits +system.cpu.BPredUnit.lookups 1041 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 733 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 220 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3787 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6697 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1112 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 455 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1166 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 814 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 253 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 3751 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6413 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1041 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 430 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1115 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 754 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 781 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 976 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 159 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.021351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.437035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 945 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 157 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.004700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.420463 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5391 82.22% 82.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 67 1.02% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 123 1.88% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 97 1.48% 86.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 146 2.23% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 50 0.76% 89.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 61 0.93% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 83 1.27% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 539 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5268 82.53% 82.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 60 0.94% 83.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 118 1.85% 85.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 94 1.47% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 140 2.19% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 58 0.91% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 55 0.86% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 1.02% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080329 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.483782 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4673 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 269 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1132 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 476 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 152 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076169 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.469232 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1083 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 426 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6020 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 5734 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 476 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4772 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 89 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 426 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4737 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1039 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 34 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5743 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 11 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4153 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6495 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6483 # Number of integer rename lookups +system.cpu.rename.RunCycles 997 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5480 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 3945 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6160 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6148 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2385 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2177 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 961 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 458 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4907 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4659 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3996 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2355 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1385 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3882 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1179 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6557 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.609425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.316967 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608178 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.298400 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4952 75.52% 75.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 578 8.82% 84.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 360 5.49% 89.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 270 4.12% 93.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 209 3.19% 97.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 109 1.66% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 54 0.82% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17 0.26% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4812 75.39% 75.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 543 8.51% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6557 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.27% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20 45.45% 47.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2819 70.55% 70.55% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 794 19.87% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 382 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2767 71.28% 71.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 734 18.91% 90.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3996 # Type of FU issued -system.cpu.iq.rate 0.288666 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011011 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14670 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7267 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3636 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3882 # Type of FU issued +system.cpu.iq.rate 0.284042 # Inst issue rate +system.cpu.iq.fu_busy_cnt 41 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010562 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14224 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6793 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4033 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3916 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 546 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 164 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 476 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 79 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5242 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 961 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 458 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 426 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5003 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 137 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3843 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 133 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 329 # number of nop insts executed -system.cpu.iew.exec_refs 1131 # number of memory reference insts executed -system.cpu.iew.exec_branches 644 # Number of branches executed -system.cpu.iew.exec_stores 376 # Number of stores executed -system.cpu.iew.exec_rate 0.277613 # Inst execution rate -system.cpu.iew.wb_sent 3725 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3642 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1733 # num instructions producing a value -system.cpu.iew.wb_consumers 2231 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1080 # number of memory reference insts executed +system.cpu.iew.exec_branches 629 # Number of branches executed +system.cpu.iew.exec_stores 374 # Number of stores executed +system.cpu.iew.exec_rate 0.274310 # Inst execution rate +system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3579 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1702 # num instructions producing a value +system.cpu.iew.wb_consumers 2165 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.263093 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.776782 # average fanout of values written-back +system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2657 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2418 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 159 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6081 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.423615 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.271187 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 5957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.432432 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.291215 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5177 85.13% 85.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 230 3.78% 88.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 323 5.31% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 118 1.94% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 67 1.10% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 52 0.86% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 37 0.61% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.33% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 57 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5066 85.04% 85.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 221 3.71% 88.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 314 5.27% 94.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 118 1.98% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 71 1.19% 97.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 5957 # Number of insts commited each cycle system.cpu.commit.count 2576 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 709 # Number of memory references committed @@ -289,49 +288,49 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 57 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11010 # The number of ROB reads -system.cpu.rob.rob_writes 10947 # The number of ROB writes +system.cpu.rob.rob_reads 10644 # The number of ROB reads +system.cpu.rob.rob_writes 10417 # The number of ROB writes system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7286 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.799330 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.799330 # CPI: Total CPI of All Threads -system.cpu.ipc 0.172434 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.172434 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4649 # number of integer regfile reads -system.cpu.int_regfile_writes 2817 # number of integer regfile writes +system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads +system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4520 # number of integer regfile reads +system.cpu.int_regfile_writes 2768 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.452549 # Cycle average of tags in use -system.cpu.icache.total_refs 735 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use +system.cpu.icache.total_refs 704 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.972973 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.805405 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 92.452549 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.045143 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 735 # number of ReadReq hits -system.cpu.icache.demand_hits 735 # number of demand (read+write) hits -system.cpu.icache.overall_hits 735 # number of overall hits +system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 704 # number of ReadReq hits +system.cpu.icache.demand_hits 704 # number of demand (read+write) hits +system.cpu.icache.overall_hits 704 # number of overall hits system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses system.cpu.icache.demand_misses 241 # number of demand (read+write) misses system.cpu.icache.overall_misses 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8775500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8775500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8775500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 976 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 976 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 976 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.246926 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.246926 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.246926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36412.863071 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36412.863071 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36412.863071 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 945 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 945 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 945 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.255026 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.255026 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.255026 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -348,52 +347,52 @@ system.cpu.icache.ReadReq_mshr_misses 185 # nu system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6554000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6554000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6554000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.189549 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.189549 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.189549 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35427.027027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.195767 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.195767 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.195767 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.779373 # Cycle average of tags in use -system.cpu.dcache.total_refs 794 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use +system.cpu.dcache.total_refs 765 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.341176 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 45.779373 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011177 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 572 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 45.439198 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 543 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.demand_hits 794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 794 # number of overall hits -system.cpu.dcache.ReadReq_misses 116 # number of ReadReq misses +system.cpu.dcache.demand_hits 765 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 765 # number of overall hits +system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 188 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3872000 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 173 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3605000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 6688500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 6688500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 6421500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 6421500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 644 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 982 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 982 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.168605 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 938 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 938 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.156832 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.191446 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.191446 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33379.310345 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate 0.184435 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.184435 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35577.127660 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35577.127660 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 37118.497110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 37118.497110 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -403,50 +402,50 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 103 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 88 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2169000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3037500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3037500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3041000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3041000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.088663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.094720 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.086558 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.086558 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35500 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.090618 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.090618 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35557.377049 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 121.331762 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 121.331762 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003703 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 120.203882 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003668 # Average percentage of cache occupancy system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 8443500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 8447500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9274500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9274500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 9278500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 9278500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses @@ -455,10 +454,10 @@ system.cpu.l2cache.ReadReq_miss_rate 1 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34323.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34339.430894 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34350 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34350 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34364.814815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34364.814815 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,19 +474,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 24 # nu system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 7661500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 8415500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 8415500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8417500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8417500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.178862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.308943 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31175.925926 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 357a5d59d..57d02de26 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:18:43 -gem5 started Jul 8 2011 15:23:20 +gem5 compiled Jul 15 2011 18:02:03 +gem5 started Jul 16 2011 04:26:12 gem5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 9834500 because target called exit() +Exiting @ tick 9807000 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index d884999d2..6012e4873 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 9834500 # Number of ticks simulated +sim_ticks 9807000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38040 # Simulator instruction rate (inst/s) -host_tick_rate 65174027 # Simulator tick rate (ticks/s) -host_mem_usage 253652 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 35563 # Simulator instruction rate (inst/s) +host_tick_rate 60757564 # Simulator tick rate (ticks/s) +host_mem_usage 253712 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,244 +51,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 19670 # number of cpu cycles simulated +system.cpu.numCycles 19615 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2538 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1884 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2511 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1859 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1886 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 760 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1876 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 752 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6290 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12764 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2538 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1028 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2852 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1670 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1030 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6264 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12675 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2511 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1020 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2829 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1652 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1029 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2054 # Number of cache lines fetched +system.cpu.fetch.CacheLines 2035 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.423857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.772019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 11271 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.423476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.772468 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8482 74.84% 74.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 284 2.51% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 192 1.69% 79.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 246 2.17% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 242 2.14% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 324 2.86% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 124 1.09% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 120 1.06% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1320 11.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8442 74.90% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.43% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 191 1.69% 79.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 247 2.19% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 241 2.14% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 319 2.83% 86.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 123 1.09% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 122 1.08% 88.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1312 11.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129029 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.648907 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6573 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1079 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2654 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 60 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 11271 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.128014 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.646189 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6547 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1078 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2630 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 955 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14169 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 14078 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6862 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 955 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6833 # Number of cycles rename is idle system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2422 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13321 # Number of instructions processed by rename +system.cpu.rename.RunCycles 2402 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 182 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13232 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12898 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 60750 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 59430 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12797 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 60391 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 59071 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7209 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 7108 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2701 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1759 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11506 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 440 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2692 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1760 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11421 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9339 # Number of instructions issued +system.cpu.iq.iqInstsIssued 9287 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14048 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 5147 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13929 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11334 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.823981 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.484525 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11271 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.823973 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.485474 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7613 67.17% 67.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1341 11.83% 79.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 855 7.54% 86.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 564 4.98% 91.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 476 4.20% 95.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 284 2.51% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 147 1.30% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 42 0.37% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7571 67.17% 67.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1335 11.84% 79.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 851 7.55% 86.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 557 4.94% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 476 4.22% 95.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.47% 98.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 148 1.31% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 43 0.38% 99.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11271 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.79% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 138 64.19% 66.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.75% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 141 64.68% 67.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71 32.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5727 61.32% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.07% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2324 24.88% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1278 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5675 61.11% 61.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2324 25.02% 86.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1278 13.76% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9339 # Type of FU issued -system.cpu.iq.rate 0.474784 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023022 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30256 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16705 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8361 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9287 # Type of FU issued +system.cpu.iq.rate 0.473464 # Inst issue rate +system.cpu.iq.fu_busy_cnt 218 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023474 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30092 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16563 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8319 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9514 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9465 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1500 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1491 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 955 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11534 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 218 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2701 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1759 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11449 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 210 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2692 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1760 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 95 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8897 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 301 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 397 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8853 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2124 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 434 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 3 # number of nop insts executed -system.cpu.iew.exec_refs 3351 # number of memory reference insts executed -system.cpu.iew.exec_branches 1479 # Number of branches executed +system.cpu.iew.exec_refs 3346 # number of memory reference insts executed +system.cpu.iew.exec_branches 1462 # Number of branches executed system.cpu.iew.exec_stores 1222 # Number of stores executed -system.cpu.iew.exec_rate 0.452313 # Inst execution rate -system.cpu.iew.wb_sent 8556 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8377 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3980 # num instructions producing a value -system.cpu.iew.wb_consumers 7830 # num instructions consuming a value +system.cpu.iew.exec_rate 0.451338 # Inst execution rate +system.cpu.iew.wb_sent 8511 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8335 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3964 # num instructions producing a value +system.cpu.iew.wb_consumers 7808 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.425877 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.508301 # average fanout of values written-back +system.cpu.iew.wb_rate 0.424930 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.507684 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5640 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5552 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 351 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10367 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.553583 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.355703 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.556266 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.365268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8010 77.26% 77.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1098 10.59% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 433 4.18% 92.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 284 2.74% 94.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 184 1.77% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.62% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.65% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.38% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 84 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7976 77.31% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1088 10.55% 87.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 426 4.13% 91.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 280 2.71% 94.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.77% 96.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 171 1.66% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.65% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 38 0.37% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 88 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10317 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed @@ -298,49 +298,49 @@ system.cpu.commit.branches 945 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 88 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21505 # The number of ROB reads -system.cpu.rob.rob_writes 23748 # The number of ROB writes +system.cpu.rob.rob_reads 21363 # The number of ROB reads +system.cpu.rob.rob_writes 23555 # The number of ROB writes system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8336 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 8344 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.427426 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.427426 # CPI: Total CPI of All Threads -system.cpu.ipc 0.291764 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.291764 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 40468 # number of integer regfile reads -system.cpu.int_regfile_writes 8226 # number of integer regfile writes +system.cpu.cpi 3.417843 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.417843 # CPI: Total CPI of All Threads +system.cpu.ipc 0.292582 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.292582 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40304 # number of integer regfile reads +system.cpu.int_regfile_writes 8184 # number of integer regfile writes system.cpu.fp_regfile_reads 29 # number of floating regfile reads -system.cpu.misc_regfile_reads 15801 # number of misc regfile reads +system.cpu.misc_regfile_reads 15709 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 150.859133 # Cycle average of tags in use -system.cpu.icache.total_refs 1688 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 150.950866 # Cycle average of tags in use +system.cpu.icache.total_refs 1669 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.702703 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.638514 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 150.859133 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.073662 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1688 # number of ReadReq hits -system.cpu.icache.demand_hits 1688 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1688 # number of overall hits +system.cpu.icache.occ_blocks::0 150.950866 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.073706 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1669 # number of ReadReq hits +system.cpu.icache.demand_hits 1669 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1669 # number of overall hits system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses system.cpu.icache.demand_misses 366 # number of demand (read+write) misses system.cpu.icache.overall_misses 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12656500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12656500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12656500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.178189 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.178189 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.178189 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34580.601093 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34580.601093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34580.601093 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 12661500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 12661500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 12661500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2035 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2035 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2035 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.179853 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.179853 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.179853 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34594.262295 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34594.262295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34594.262295 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -357,60 +357,60 @@ system.cpu.icache.ReadReq_mshr_misses 296 # nu system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9940500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9940500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9940500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 9939500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9939500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9939500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.144109 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.144109 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.144109 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33582.770270 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.145455 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.145455 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.145455 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33579.391892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33579.391892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33579.391892 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.281770 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 92.326406 # Cycle average of tags in use system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.512821 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.281770 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022530 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 92.326406 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022541 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1791 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits system.cpu.dcache.demand_hits 2400 # number of demand (read+write) hits system.cpu.dcache.overall_hits 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses 178 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses 177 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5526000 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 481 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5493000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 16231500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16231500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 16198500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16198500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1968 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2882 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2882 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.090401 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2881 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2881 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.089939 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.167245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.167245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31044.943820 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate 0.166956 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.166956 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31033.898305 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33675.311203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33675.311203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33676.715177 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33676.715177 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,41 +420,41 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 326 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 326 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 325 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 114 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3236000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4741000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4741000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.057897 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.057927 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.054129 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.054129 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.054148 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.054148 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28385.964912 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30391.025641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30391.025641 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 190.940380 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 191.048860 # Cycle average of tags in use system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 190.940380 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005827 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 191.048860 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005830 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 43 # number of overall hits @@ -462,10 +462,10 @@ system.cpu.l2cache.ReadReq_misses 367 # nu system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12612500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 12610500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 14063000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 14063000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 14061000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 14061000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses @@ -474,10 +474,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.895122 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34366.485014 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34361.035422 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34383.863081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34383.863081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34378.973105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34378.973105 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index d2612b5d7..cfd15d7a7 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:04:50 -gem5 started Jul 8 2011 15:22:25 +gem5 compiled Jul 15 2011 17:48:05 +gem5 started Jul 15 2011 20:13:48 gem5 executing on u200439-lin.austin.arm.com command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12285500 because target called exit() +Exiting @ tick 12273500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 39498f791..d9d305c59 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12285500 # Number of ticks simulated +sim_ticks 12273500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28817 # Simulator instruction rate (inst/s) -host_tick_rate 68479139 # Simulator tick rate (ticks/s) -host_mem_usage 244744 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 33014 # Simulator instruction rate (inst/s) +host_tick_rate 78373339 # Simulator tick rate (ticks/s) +host_mem_usage 244788 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,199 +27,199 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24572 # number of cpu cycles simulated +system.cpu.numCycles 24548 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1982 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1348 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 1977 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1345 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1584 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 496 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1580 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7946 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12305 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1982 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3034 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1194 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7914 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12271 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1977 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1189 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1787 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.971422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.277830 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1783 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 230 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12623 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.972114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.277844 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9633 76.05% 76.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1253 9.89% 85.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 111 0.88% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 138 1.09% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 289 2.28% 90.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 132 1.04% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 144 1.14% 93.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 875 6.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9597 76.03% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1250 9.90% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 93 0.74% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 870 6.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080661 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.500773 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8135 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 12623 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080536 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.499878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8103 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2867 # Number of cycles decode is running +system.cpu.decode.RunCycles 2859 # Number of cycles decode is running system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 743 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 739 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11438 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 743 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8306 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 739 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8274 # Number of cycles rename is idle system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2750 # Number of cycles rename is running +system.cpu.rename.RunCycles 2742 # Number of cycles rename is running system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11058 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11017 # Number of instructions processed by rename system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6730 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13185 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13180 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 6705 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13120 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3320 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3295 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 18 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2359 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2349 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1175 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8691 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8651 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7857 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3019 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7822 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1815 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12667 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.620273 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.285525 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.619663 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.285161 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9298 73.40% 73.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1326 10.47% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 831 6.56% 90.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 513 4.05% 94.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 361 2.85% 97.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 205 1.62% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 85 0.67% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33 0.26% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9267 73.41% 73.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1321 10.47% 83.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 831 6.58% 90.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 511 4.05% 94.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 357 2.83% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 203 1.61% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 83 0.66% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12667 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12623 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 2.07% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 90 62.07% 64.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 35.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 91 62.33% 64.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4616 58.75% 58.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2141 27.25% 86.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1092 13.90% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4598 58.78% 58.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2131 27.24% 86.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1085 13.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7857 # Type of FU issued -system.cpu.iq.rate 0.319754 # Inst issue rate -system.cpu.iq.fu_busy_cnt 145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018455 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28573 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11730 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7154 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7822 # Type of FU issued +system.cpu.iq.rate 0.318641 # Inst issue rate +system.cpu.iq.fu_busy_cnt 146 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018665 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 28459 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11666 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7121 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8000 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 7966 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1195 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1185 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 250 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 743 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 739 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10089 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10044 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2359 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2349 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1175 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -227,44 +227,44 @@ system.cpu.iew.memOrderViolationEvents 9 # Nu system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7573 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2041 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7537 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2031 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 285 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1385 # number of nop insts executed -system.cpu.iew.exec_refs 3109 # number of memory reference insts executed -system.cpu.iew.exec_branches 1276 # Number of branches executed -system.cpu.iew.exec_stores 1068 # Number of stores executed -system.cpu.iew.exec_rate 0.308196 # Inst execution rate -system.cpu.iew.wb_sent 7250 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7156 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2771 # num instructions producing a value -system.cpu.iew.wb_consumers 3964 # num instructions consuming a value +system.cpu.iew.exec_nop 1380 # number of nop insts executed +system.cpu.iew.exec_refs 3091 # number of memory reference insts executed +system.cpu.iew.exec_branches 1271 # Number of branches executed +system.cpu.iew.exec_stores 1060 # Number of stores executed +system.cpu.iew.exec_rate 0.307031 # Inst execution rate +system.cpu.iew.wb_sent 7215 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7123 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2761 # num instructions producing a value +system.cpu.iew.wb_consumers 3949 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.291226 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.699041 # average fanout of values written-back +system.cpu.iew.wb_rate 0.290166 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.699164 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4255 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4210 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11924 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.488594 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.274116 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11884 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.490239 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.276602 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9523 79.86% 79.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 968 8.12% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 656 5.50% 93.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 322 2.70% 96.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 146 1.22% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9485 79.81% 79.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 966 8.13% 87.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 656 5.52% 93.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.35% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.35% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11884 # Number of insts commited each cycle system.cpu.commit.count 5826 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2089 # Number of memory references committed @@ -274,49 +274,49 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21891 # The number of ROB reads -system.cpu.rob.rob_writes 20916 # The number of ROB writes +system.cpu.rob.rob_reads 21805 # The number of ROB reads +system.cpu.rob.rob_writes 20822 # The number of ROB writes system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11905 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11925 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.753724 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.753724 # CPI: Total CPI of All Threads -system.cpu.ipc 0.210361 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.210361 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10347 # number of integer regfile reads -system.cpu.int_regfile_writes 5013 # number of integer regfile writes +system.cpu.cpi 4.749081 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.749081 # CPI: Total CPI of All Threads +system.cpu.ipc 0.210567 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.210567 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10287 # number of integer regfile reads +system.cpu.int_regfile_writes 4991 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 154 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.262110 # Cycle average of tags in use -system.cpu.icache.total_refs 1367 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.223747 # Cycle average of tags in use +system.cpu.icache.total_refs 1364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.068452 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.059524 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 161.262110 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.078741 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits -system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1367 # number of overall hits -system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses -system.cpu.icache.demand_misses 420 # number of demand (read+write) misses -system.cpu.icache.overall_misses 420 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15216000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15216000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15216000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1787 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1787 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1787 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.235031 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.235031 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.235031 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36228.571429 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36228.571429 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36228.571429 # average overall miss latency +system.cpu.icache.occ_blocks::0 161.223747 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1364 # number of ReadReq hits +system.cpu.icache.demand_hits 1364 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1364 # number of overall hits +system.cpu.icache.ReadReq_misses 419 # number of ReadReq misses +system.cpu.icache.demand_misses 419 # number of demand (read+write) misses +system.cpu.icache.overall_misses 419 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15179500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15179500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15179500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1783 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1783 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1783 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.234997 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.234997 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.234997 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36227.923628 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36227.923628 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36227.923628 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -326,59 +326,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 84 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 84 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 84 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11782000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11782000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11782000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11784000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11784000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11784000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.188025 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.188025 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.188025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35065.476190 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35065.476190 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35065.476190 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.188446 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.188446 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.188446 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.136669 # Cycle average of tags in use -system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.122056 # Cycle average of tags in use +system.cpu.dcache.total_refs 2382 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.838028 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.774648 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.136669 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022494 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1813 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 92.122056 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022491 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1804 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits -system.cpu.dcache.demand_hits 2391 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2391 # number of overall hits -system.cpu.dcache.ReadReq_misses 135 # number of ReadReq misses +system.cpu.dcache.demand_hits 2382 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2382 # number of overall hits +system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses -system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4832000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 11507500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 16339500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16339500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1948 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 481 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 481 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4801000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11505500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 16306500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16306500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1938 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2873 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2873 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.069302 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.069143 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.167769 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.167769 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35792.592593 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33162.824207 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33899.377593 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33899.377593 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.168006 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.168006 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35828.358209 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33157.060519 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33901.247401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33901.247401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,40 +388,40 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 340 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 340 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 339 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1836500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5108500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5108500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1835500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5107500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5107500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.046715 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.046956 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.049426 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.049426 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate 0.049598 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.049598 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36009.803922 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35975.352113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35975.352113 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35990.196078 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35968.309859 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.568003 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.520650 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.568003 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 221.520650 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006760 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 3 # number of overall hits @@ -429,10 +429,10 @@ system.cpu.l2cache.ReadReq_misses 424 # nu system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.demand_misses 475 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1761000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16322000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16322000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14561500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1760000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16321500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16321500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 427 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses @@ -441,10 +441,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.992974 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.993724 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.993724 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34529.411765 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34362.105263 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34362.105263 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34343.160377 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34509.803922 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34361.052632 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34361.052632 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,19 +461,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 51 # nu system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13198500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1599500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14798000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14798000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 13198000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1598500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14796500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14796500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.537736 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31362.745098 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31153.684211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31153.684211 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index 3b8650bce..d1cb3e246 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:06:16 -gem5 started Jul 8 2011 15:22:37 +gem5 compiled Jul 15 2011 17:49:29 +gem5 started Jul 15 2011 20:14:11 gem5 executing on u200439-lin.austin.arm.com command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11010500 because target called exit() +Exiting @ tick 10910500 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index d012d707f..bac6ac3e3 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11010500 # Number of ticks simulated +sim_ticks 10910500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36368 # Simulator instruction rate (inst/s) -host_tick_rate 69032646 # Simulator tick rate (ticks/s) -host_mem_usage 241332 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 31106 # Simulator instruction rate (inst/s) +host_tick_rate 58503850 # Simulator tick rate (ticks/s) +host_mem_usage 241340 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,244 +27,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22022 # number of cpu cycles simulated +system.cpu.numCycles 21822 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2367 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1975 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2297 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1905 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 402 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1913 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 666 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6529 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13348 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2367 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 869 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2278 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1276 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 941 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 6507 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2297 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 855 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2210 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1212 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 909 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1754 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 10610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.258058 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.653017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 10433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.243746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.642546 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8332 78.53% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 151 1.42% 79.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 185 1.74% 81.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 141 1.33% 83.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 226 2.13% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 137 1.29% 86.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 283 2.67% 89.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 123 1.16% 90.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1032 9.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8223 78.82% 78.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 152 1.46% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 173 1.66% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 127 1.22% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 217 2.08% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 137 1.31% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 283 2.71% 89.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 122 1.17% 90.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 999 9.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 10610 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.107483 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.606121 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6699 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1011 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2107 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 711 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 10433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.105261 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.594629 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6670 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 983 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2045 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 656 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 304 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 152 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11818 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11459 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 428 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 711 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6902 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 656 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6866 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 379 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1977 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 278 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11283 # Number of instructions processed by rename +system.cpu.rename.RunCycles 1920 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 262 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 10928 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 220 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9842 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18439 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18368 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 207 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9549 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17852 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17781 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 71 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4835 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4542 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 566 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1897 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1627 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. +system.cpu.rename.skidInsts 544 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1864 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1573 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 44 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9933 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8750 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8536 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4202 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3778 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 3878 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3544 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 10610 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.824694 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535023 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 10433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.818173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.531685 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7338 69.16% 69.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1037 9.77% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 771 7.27% 86.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 497 4.68% 90.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 457 4.31% 95.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 303 2.86% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 135 1.27% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 49 0.46% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7234 69.34% 69.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1021 9.79% 79.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 7.30% 86.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 472 4.52% 90.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 448 4.29% 95.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 290 2.78% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 132 1.27% 99.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 51 0.49% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 23 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 10610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 10433 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 6.45% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 68 43.87% 50.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 49.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.84% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 68 44.16% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5520 63.09% 63.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1751 20.01% 83.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1477 16.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5388 63.12% 63.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1717 20.11% 83.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1429 16.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8750 # Type of FU issued -system.cpu.iq.rate 0.397330 # Inst issue rate -system.cpu.iq.fu_busy_cnt 155 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017714 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28255 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14489 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8028 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8536 # Type of FU issued +system.cpu.iq.rate 0.391165 # Inst issue rate +system.cpu.iq.fu_busy_cnt 154 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018041 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 27649 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13831 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7849 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 74 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 30 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8867 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8652 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 38 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 935 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 902 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 581 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 527 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 711 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 656 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10327 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10002 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1897 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1627 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1864 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1573 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 60 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 239 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 301 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8358 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1644 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 392 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 238 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 300 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8170 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1611 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3035 # number of memory reference insts executed -system.cpu.iew.exec_branches 1315 # Number of branches executed -system.cpu.iew.exec_stores 1391 # Number of stores executed -system.cpu.iew.exec_rate 0.379530 # Inst execution rate -system.cpu.iew.wb_sent 8174 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4233 # num instructions producing a value -system.cpu.iew.wb_consumers 6765 # num instructions consuming a value +system.cpu.iew.exec_refs 2952 # number of memory reference insts executed +system.cpu.iew.exec_branches 1313 # Number of branches executed +system.cpu.iew.exec_stores 1341 # Number of stores executed +system.cpu.iew.exec_rate 0.374393 # Inst execution rate +system.cpu.iew.wb_sent 7993 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7879 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4173 # num instructions producing a value +system.cpu.iew.wb_consumers 6691 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.365907 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.625721 # average fanout of values written-back +system.cpu.iew.wb_rate 0.361058 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.623674 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4533 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4208 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 9899 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.585918 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.365203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 9777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.593229 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.375317 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7502 75.79% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 985 9.95% 85.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 645 6.52% 92.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.65% 94.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 188 1.90% 96.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 118 1.19% 97.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 77 0.78% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.41% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 81 0.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7386 75.54% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 981 10.03% 85.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 642 6.57% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 262 2.68% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 190 1.94% 96.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 116 1.19% 97.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 75 0.77% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.42% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 84 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 9899 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 9777 # Number of insts commited each cycle system.cpu.commit.count 5800 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2008 # Number of memory references committed @@ -274,45 +274,45 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 81 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 20151 # The number of ROB reads -system.cpu.rob.rob_writes 21378 # The number of ROB writes -system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11412 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 19701 # The number of ROB reads +system.cpu.rob.rob_writes 20673 # The number of ROB writes +system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11389 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.796897 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.796897 # CPI: Total CPI of All Threads -system.cpu.ipc 0.263373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.263373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13256 # number of integer regfile reads -system.cpu.int_regfile_writes 7085 # number of integer regfile writes +system.cpu.cpi 3.762414 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.762414 # CPI: Total CPI of All Threads +system.cpu.ipc 0.265787 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.265787 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12979 # number of integer regfile reads +system.cpu.int_regfile_writes 6957 # number of integer regfile writes system.cpu.fp_regfile_reads 28 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 169.489368 # Cycle average of tags in use -system.cpu.icache.total_refs 1334 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 169.539680 # Cycle average of tags in use +system.cpu.icache.total_refs 1291 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.800570 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.678063 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 169.489368 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.082758 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1334 # number of ReadReq hits -system.cpu.icache.demand_hits 1334 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1334 # number of overall hits +system.cpu.icache.occ_blocks::0 169.539680 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.082783 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1291 # number of ReadReq hits +system.cpu.icache.demand_hits 1291 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1291 # number of overall hits system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses system.cpu.icache.demand_misses 420 # number of demand (read+write) misses system.cpu.icache.overall_misses 420 # number of overall misses system.cpu.icache.ReadReq_miss_latency 15114500 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency 15114500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency 15114500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.239453 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.239453 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.239453 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.245470 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.245470 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.245470 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency 35986.904762 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency 35986.904762 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 35986.904762 # average overall miss latency @@ -336,9 +336,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency 12207500 # system.cpu.icache.demand_mshr_miss_latency 12207500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 12207500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.200114 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.200114 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.200114 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.205143 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.205143 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.205143 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency @@ -347,37 +347,37 @@ system.cpu.icache.mshr_cap_events 0 # nu system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 66.389041 # Cycle average of tags in use -system.cpu.dcache.total_refs 2180 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 66.296919 # Cycle average of tags in use +system.cpu.dcache.total_refs 2156 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 105 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 20.761905 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.533333 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 66.389041 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.016208 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1445 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 735 # number of WriteReq hits -system.cpu.dcache.demand_hits 2180 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2180 # number of overall hits -system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu.dcache.demand_misses 401 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 401 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3011000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10558500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13569500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13569500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 66.296919 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.016186 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1428 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 728 # number of WriteReq hits +system.cpu.dcache.demand_hits 2156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2156 # number of overall hits +system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 318 # number of WriteReq misses +system.cpu.dcache.demand_misses 406 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 406 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2947000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10802500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 13749500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 13749500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2581 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2581 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.058632 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.297323 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.155366 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.155366 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33455.555556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33950.160772 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33839.152120 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33839.152120 # average overall miss latency +system.cpu.dcache.demand_accesses 2562 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.058047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.304015 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.158470 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.158470 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33488.636364 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33970.125786 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33865.763547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33865.763547 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,39 +387,39 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 296 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 57 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 105 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 105 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 1963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3714000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3714000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1751000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3714500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.037134 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.037599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.040682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.040682 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate 0.040984 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.040984 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34447.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36468.750000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35371.428571 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35371.428571 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36479.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35376.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35376.190476 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 200.598447 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 200.613051 # Cycle average of tags in use system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.022556 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 200.598447 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 200.613051 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.006122 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 9 # number of ReadReq hits system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits @@ -429,9 +429,9 @@ system.cpu.l2cache.ReadExReq_misses 48 # nu system.cpu.l2cache.demand_misses 447 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 447 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency 13714000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1678000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 15392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 15392000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1678500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 15392500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 15392500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 456 # number of demand (read+write) accesses @@ -441,9 +441,9 @@ system.cpu.l2cache.ReadExReq_miss_rate 1 # mi system.cpu.l2cache.demand_miss_rate 0.980263 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.980263 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency 34370.927318 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34958.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34434.004474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34434.004474 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34968.750000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34435.123043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34435.123043 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -460,19 +460,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 48 # nu system.cpu.l2cache.demand_mshr_misses 447 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 447 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12433500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12434000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13959500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13959500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13960000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977941 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.980263 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.980263 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.654135 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31162.907268 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.306488 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.306488 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index e361952bb..66b7170d9 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:18:15 -gem5 started Jul 8 2011 15:23:04 +gem5 compiled Jul 15 2011 18:01:24 +gem5 started Jul 16 2011 00:22:08 gem5 executing on u200439-lin.austin.arm.com command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 11102000 because target called exit() +Exiting @ tick 11087000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index a1f123e22..f6f7897f3 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11102000 # Number of ticks simulated +sim_ticks 11087000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58378 # Simulator instruction rate (inst/s) -host_tick_rate 66066423 # Simulator tick rate (ticks/s) -host_mem_usage 248304 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 48237 # Simulator instruction rate (inst/s) +host_tick_rate 54512378 # Simulator tick rate (ticks/s) +host_mem_usage 248340 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 9809 # Number of instructions simulated system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 22205 # number of cpu cycles simulated +system.cpu.numCycles 22175 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3070 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3070 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 3057 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3057 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2745 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 1002 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 2732 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 995 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 5900 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14062 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3070 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2234 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 5894 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14000 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3057 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 995 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3968 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2223 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1500 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1900 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.933552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.219407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1891 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13088 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.930776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.218766 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9243 70.43% 70.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 169 1.29% 71.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.34% 73.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 241 1.84% 74.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 234 1.78% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 195 1.49% 78.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 280 2.13% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.07% 81.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2444 18.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9227 70.50% 70.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 167 1.28% 71.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 175 1.34% 73.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 239 1.83% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 232 1.77% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 193 1.47% 78.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 279 2.13% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 139 1.06% 81.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2437 18.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.138257 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.633281 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6251 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1454 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3582 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 112 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1724 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24194 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1724 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6540 # Number of cycles rename is idle +system.cpu.fetch.rateDist::total 13088 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137858 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.631342 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6247 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1453 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3564 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1713 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24084 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1713 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6535 # Number of cycles rename is idle system.cpu.rename.BlockCycles 523 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 524 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3382 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 430 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22801 # Number of instructions processed by rename +system.cpu.rename.RunCycles 3364 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 429 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22708 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 271 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21341 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 47863 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 47847 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 21249 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 47660 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 47644 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11973 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 11881 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1611 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2253 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1786 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 1609 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2239 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1783 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20643 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17013 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10307 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13151 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13123 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.296426 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.004622 # Number of insts issued each cycle +system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 20542 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 16959 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10220 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13000 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.295767 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.003323 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8026 61.16% 61.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1107 8.44% 69.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1007 7.67% 77.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 730 5.56% 82.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 676 5.15% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 728 5.55% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 620 4.72% 98.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 194 1.48% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 35 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8001 61.13% 61.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1107 8.46% 69.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1007 7.69% 77.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 733 5.60% 82.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 670 5.12% 88.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 725 5.54% 93.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 615 4.70% 98.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 196 1.50% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 34 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13088 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 95 66.90% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 16.90% 83.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 16.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 94 66.67% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24 17.02% 83.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 16.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13681 80.41% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1854 10.90% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1474 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13641 80.44% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1844 10.87% 91.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1470 8.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17013 # Type of FU issued -system.cpu.iq.rate 0.766179 # Inst issue rate -system.cpu.iq.fu_busy_cnt 142 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008347 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 47348 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30994 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15803 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 16959 # Type of FU issued +system.cpu.iq.rate 0.764780 # Inst issue rate +system.cpu.iq.fu_busy_cnt 141 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008314 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 47202 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30805 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15753 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17147 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17092 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1197 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1183 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 852 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1724 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1713 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20678 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 15 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2253 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1786 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 20576 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 23 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2239 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1783 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16148 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1748 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 865 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 523 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 588 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16098 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1742 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 861 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3114 # number of memory reference insts executed -system.cpu.iew.exec_branches 1606 # Number of branches executed -system.cpu.iew.exec_stores 1366 # Number of stores executed -system.cpu.iew.exec_rate 0.727224 # Inst execution rate -system.cpu.iew.wb_sent 15964 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15807 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10570 # num instructions producing a value -system.cpu.iew.wb_consumers 15744 # num instructions consuming a value +system.cpu.iew.exec_refs 3105 # number of memory reference insts executed +system.cpu.iew.exec_branches 1601 # Number of branches executed +system.cpu.iew.exec_stores 1363 # Number of stores executed +system.cpu.iew.exec_rate 0.725953 # Inst execution rate +system.cpu.iew.wb_sent 15916 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15757 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10536 # num instructions producing a value +system.cpu.iew.wb_consumers 15696 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.711867 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.671367 # average fanout of values written-back +system.cpu.iew.wb_rate 0.710575 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.671254 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 10868 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10766 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 497 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11399 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.860514 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.681683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.862330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.686905 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7958 69.81% 69.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1091 9.57% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 577 5.06% 84.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 889 7.80% 92.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 346 3.04% 95.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 149 1.31% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 139 1.22% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 66 0.58% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 184 1.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7943 69.83% 69.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1088 9.56% 79.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 574 5.05% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 883 7.76% 92.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 343 3.02% 95.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 152 1.34% 96.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 139 1.22% 97.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.58% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 187 1.64% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11399 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11375 # Number of insts commited each cycle system.cpu.commit.count 9809 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1990 # Number of memory references committed @@ -255,48 +255,48 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 187 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 31892 # The number of ROB reads -system.cpu.rob.rob_writes 43113 # The number of ROB writes +system.cpu.rob.rob_reads 31763 # The number of ROB reads +system.cpu.rob.rob_writes 42898 # The number of ROB writes system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9082 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 9087 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.263737 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.263737 # CPI: Total CPI of All Threads -system.cpu.ipc 0.441747 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.441747 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23720 # number of integer regfile reads -system.cpu.int_regfile_writes 14686 # number of integer regfile writes +system.cpu.cpi 2.260679 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.260679 # CPI: Total CPI of All Threads +system.cpu.ipc 0.442345 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.442345 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23665 # number of integer regfile reads +system.cpu.int_regfile_writes 14643 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7234 # number of misc regfile reads +system.cpu.misc_regfile_reads 7210 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.121253 # Cycle average of tags in use -system.cpu.icache.total_refs 1536 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 145.144237 # Cycle average of tags in use +system.cpu.icache.total_refs 1527 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.154362 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.124161 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 145.121253 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.070860 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1536 # number of ReadReq hits -system.cpu.icache.demand_hits 1536 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1536 # number of overall hits +system.cpu.icache.occ_blocks::0 145.144237 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.070871 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1527 # number of ReadReq hits +system.cpu.icache.demand_hits 1527 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1527 # number of overall hits system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses system.cpu.icache.demand_misses 364 # number of demand (read+write) misses system.cpu.icache.overall_misses 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 13311000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 13311000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 13311000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1900 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1900 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.191579 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.191579 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.191579 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36568.681319 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36568.681319 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36568.681319 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 13314500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 13314500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 13314500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1891 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1891 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1891 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.192491 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.192491 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.192491 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36578.296703 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36578.296703 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36578.296703 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -313,52 +313,52 @@ system.cpu.icache.ReadReq_mshr_misses 298 # nu system.cpu.icache.demand_mshr_misses 298 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 298 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10465000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10465000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10465000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10466500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10466500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10466500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.156842 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.156842 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.156842 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35117.449664 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35117.449664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35117.449664 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.157589 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.157589 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.157589 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35122.483221 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35122.483221 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35122.483221 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.500276 # Cycle average of tags in use -system.cpu.dcache.total_refs 2118 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.499149 # Cycle average of tags in use +system.cpu.dcache.total_refs 2112 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 14.606897 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.565517 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 85.500276 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 85.499149 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.020874 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1500 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1494 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 618 # number of WriteReq hits -system.cpu.dcache.demand_hits 2118 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2118 # number of overall hits +system.cpu.dcache.demand_hits 2112 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2112 # number of overall hits system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 316 # number of WriteReq misses system.cpu.dcache.demand_misses 429 # number of demand (read+write) misses system.cpu.dcache.overall_misses 429 # number of overall misses system.cpu.dcache.ReadReq_miss_latency 3938500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10704500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 14643000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 14643000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_latency 10708500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 14647000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 14647000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1607 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2547 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2547 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.070056 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2541 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2541 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.070317 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.338330 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.168433 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.168433 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate 0.168831 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.168831 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 34853.982301 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33875 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34132.867133 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34132.867133 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33887.658228 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 34142.191142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 34142.191142 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,17 +377,17 @@ system.cpu.dcache.WriteReq_mshr_misses 77 # nu system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2421500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2762000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2422500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2761000 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 5183500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 5183500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.042777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.042937 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.057322 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.057322 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35094.202899 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35870.129870 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.057458 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.057458 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35108.695652 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35857.142857 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency @@ -395,13 +395,13 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.583785 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.614114 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005495 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 178.583785 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005450 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 178.614114 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005451 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits @@ -409,10 +409,10 @@ system.cpu.l2cache.ReadReq_misses 365 # nu system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses system.cpu.l2cache.demand_misses 442 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12493000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2653500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 15146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 15146500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 12494500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2654000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 15148500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 15148500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 367 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses @@ -421,10 +421,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.994550 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.995495 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.995495 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34227.397260 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34461.038961 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34268.099548 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34268.099548 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34231.506849 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34467.532468 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34272.624434 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34272.624434 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -441,19 +441,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 77 # nu system.cpu.l2cache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 442 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11330000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 2409500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13737500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13737500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13739500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13739500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994550 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.995495 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.995495 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.616438 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.095890 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31292.207792 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31084.841629 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31084.841629 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index f562f208e..ece91e6a2 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 15:21:20 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 20:04:28 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 13218000 because target called exit() +Exiting @ tick 13202000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index ba1ddb358..85f082537 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13218000 # Number of ticks simulated +sim_ticks 13202000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47211 # Simulator instruction rate (inst/s) -host_tick_rate 48851159 # Simulator tick rate (ticks/s) -host_mem_usage 244284 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 45146 # Simulator instruction rate (inst/s) +host_tick_rate 46657266 # Simulator tick rate (ticks/s) +host_mem_usage 244348 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 3714 # DTB read hits -system.cpu.dtb.read_misses 89 # DTB read misses +system.cpu.dtb.read_hits 3722 # DTB read hits +system.cpu.dtb.read_misses 94 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 3803 # DTB read accesses -system.cpu.dtb.write_hits 1992 # DTB write hits -system.cpu.dtb.write_misses 59 # DTB write misses +system.cpu.dtb.read_accesses 3816 # DTB read accesses +system.cpu.dtb.write_hits 1984 # DTB write hits +system.cpu.dtb.write_misses 61 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2051 # DTB write accesses +system.cpu.dtb.write_accesses 2045 # DTB write accesses system.cpu.dtb.data_hits 5706 # DTB hits -system.cpu.dtb.data_misses 148 # DTB misses +system.cpu.dtb.data_misses 155 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 5854 # DTB accesses -system.cpu.itb.fetch_hits 4085 # ITB hits +system.cpu.dtb.data_accesses 5861 # DTB accesses +system.cpu.itb.fetch_hits 4091 # ITB hits system.cpu.itb.fetch_misses 56 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 4141 # ITB accesses +system.cpu.itb.fetch_accesses 4147 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -42,175 +42,175 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 26437 # number of cpu cycles simulated +system.cpu.numCycles 26405 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 5187 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2958 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1247 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 3609 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 1000 # Number of BTB hits +system.cpu.BPredUnit.lookups 5174 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2964 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1252 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 3548 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 1004 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 740 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 156 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1108 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 29051 # Number of instructions fetch has processed -system.cpu.fetch.Branches 5187 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1740 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5000 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1319 # Number of cycles fetch has spent squashing +system.cpu.BPredUnit.usedRAS 734 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 158 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1115 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 28962 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5174 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1738 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4987 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 4085 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 640 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 20361 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.426796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.797497 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 4091 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 637 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 20201 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.433691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.801868 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 15361 75.44% 75.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 451 2.22% 77.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 362 1.78% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 388 1.91% 81.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 391 1.92% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 325 1.60% 84.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 409 2.01% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 323 1.59% 88.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2351 11.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 15214 75.31% 75.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 449 2.22% 77.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 365 1.81% 79.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 384 1.90% 81.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 390 1.93% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 328 1.62% 84.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 404 2.00% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 329 1.63% 88.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2338 11.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 20361 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.196202 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.098877 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 28250 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5561 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 4330 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 453 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 20201 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.195948 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.096838 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27985 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5533 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4328 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 445 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1869 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 485 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 311 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 25978 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 552 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 28803 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2995 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 772 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4141 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1883 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24541 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 1746 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 18357 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 30569 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 30535 # Number of integer rename lookups +system.cpu.decode.BranchMispred 315 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 25962 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 512 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1869 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 28534 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2990 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 752 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4136 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1879 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24542 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 1739 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 18358 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 30575 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 30541 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9191 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 9192 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 52 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 40 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4665 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2306 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1192 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 4646 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2308 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1190 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2327 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1184 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 2319 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1181 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22275 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22288 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 19420 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8699 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4701 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 19435 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8694 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4709 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 20361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.953784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.476295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 20201 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.962081 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.481018 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12146 59.65% 59.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2930 14.39% 74.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2237 10.99% 85.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1382 6.79% 91.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 875 4.30% 96.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 479 2.35% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 226 1.11% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 69 0.34% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 17 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11990 59.35% 59.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2928 14.49% 73.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2232 11.05% 84.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1366 6.76% 91.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 891 4.41% 96.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 479 2.37% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 237 1.17% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 60 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 20361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 20201 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.44% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 103 57.22% 61.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69 38.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 4.92% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 106 57.92% 62.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 68 37.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6596 67.90% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2046 21.06% 89.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1068 10.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6617 67.89% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2056 21.09% 89.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1069 10.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9715 # Type of FU issued +system.cpu.iq.FU_type_0::total 9747 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6577 67.77% 67.79% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6565 67.76% 67.78% # Type of FU issued system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued @@ -239,13 +239,13 @@ system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Ty system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2049 21.11% 88.93% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1074 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2046 21.12% 88.93% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1072 11.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 9705 # Type of FU issued +system.cpu.iq.FU_type_1::total 9688 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13173 67.83% 67.85% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 13182 67.83% 67.85% # Type of FU issued system.cpu.iq.FU_type::IntMult 2 0.01% 67.86% # Type of FU issued system.cpu.iq.FU_type::IntDiv 0 0.00% 67.86% # Type of FU issued system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.88% # Type of FU issued @@ -274,127 +274,127 @@ system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.88% # Ty system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.88% # Type of FU issued system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.88% # Type of FU issued system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4095 21.09% 88.97% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2142 11.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4102 21.11% 88.98% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2141 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 19420 # Type of FU issued -system.cpu.iq.rate 0.734577 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 90 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 90 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 180 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004634 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004634 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.009269 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 59410 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31025 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17735 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 19435 # Type of FU issued +system.cpu.iq.rate 0.736035 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 183 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004837 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004579 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.009416 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 59279 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31036 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17747 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 19574 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 19592 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 48 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1121 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1123 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 327 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 325 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1142 # Number of loads squashed +system.cpu.iew.lsq.thread1.squashedLoads 1134 # Number of loads squashed system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 319 # Number of stores squashed +system.cpu.iew.lsq.thread1.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 316 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1869 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1204 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 22464 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 427 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4633 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2376 # Number of dispatched store instructions +system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 22477 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4627 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2371 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 214 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 883 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1097 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 18405 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 1891 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 1918 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 3809 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1015 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 882 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1100 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 18425 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 1901 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 1921 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 3822 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed system.cpu.iew.exec_nop::0 75 # number of nop insts executed system.cpu.iew.exec_nop::1 65 # number of nop insts executed system.cpu.iew.exec_nop::total 140 # number of nop insts executed -system.cpu.iew.exec_refs::0 2925 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 2953 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 5878 # number of memory reference insts executed +system.cpu.iew.exec_refs::0 2932 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 2948 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 5880 # number of memory reference insts executed system.cpu.iew.exec_branches::0 1521 # Number of branches executed -system.cpu.iew.exec_branches::1 1527 # Number of branches executed -system.cpu.iew.exec_branches::total 3048 # Number of branches executed -system.cpu.iew.exec_stores::0 1034 # Number of stores executed -system.cpu.iew.exec_stores::1 1035 # Number of stores executed -system.cpu.iew.exec_stores::total 2069 # Number of stores executed -system.cpu.iew.exec_rate 0.696183 # Inst execution rate -system.cpu.iew.wb_sent::0 9003 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9003 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18006 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 8892 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 8863 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 17755 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4543 # num instructions producing a value -system.cpu.iew.wb_producers::1 4543 # num instructions producing a value -system.cpu.iew.wb_producers::total 9086 # num instructions producing a value -system.cpu.iew.wb_consumers::0 5945 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 5949 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 11894 # num instructions consuming a value +system.cpu.iew.exec_branches::1 1526 # Number of branches executed +system.cpu.iew.exec_branches::total 3047 # Number of branches executed +system.cpu.iew.exec_stores::0 1031 # Number of stores executed +system.cpu.iew.exec_stores::1 1027 # Number of stores executed +system.cpu.iew.exec_stores::total 2058 # Number of stores executed +system.cpu.iew.exec_rate 0.697785 # Inst execution rate +system.cpu.iew.wb_sent::0 9024 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 8991 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 18015 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 8913 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 8854 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 17767 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4555 # num instructions producing a value +system.cpu.iew.wb_producers::1 4549 # num instructions producing a value +system.cpu.iew.wb_producers::total 9104 # num instructions producing a value +system.cpu.iew.wb_consumers::0 5963 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 5961 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 11924 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.336347 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.335250 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.671597 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.764172 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.763658 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 1.527829 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.337550 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.335315 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.672865 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.763877 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.763127 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 1.527004 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9583 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9596 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 951 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20336 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.629770 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.428976 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 953 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.634764 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.436773 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14766 72.61% 72.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2895 14.24% 86.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1050 5.16% 92.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 514 2.53% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 350 1.72% 96.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 235 1.16% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 212 1.04% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 89 0.44% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 225 1.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14631 72.52% 72.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2865 14.20% 86.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1050 5.20% 91.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 518 2.57% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 346 1.71% 96.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 239 1.18% 97.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 208 1.03% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 91 0.45% 98.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 228 1.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20336 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20176 # Number of insts commited each cycle system.cpu.commit.count::0 6403 # Number of instructions committed system.cpu.commit.count::1 6404 # Number of instructions committed system.cpu.commit.count::total 12807 # Number of instructions committed @@ -422,25 +422,25 @@ system.cpu.commit.int_insts::total 12642 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 225 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 101662 # The number of ROB reads -system.cpu.rob.rob_writes 46661 # The number of ROB writes -system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6076 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 101307 # The number of ROB reads +system.cpu.rob.rob_writes 46689 # The number of ROB writes +system.cpu.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6204 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6386 # Number of Instructions Simulated system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.139837 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.139189 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.069757 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.241555 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.241593 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.483149 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23349 # number of integer regfile reads -system.cpu.int_regfile_writes 13299 # number of integer regfile writes +system.cpu.cpi::0 4.134826 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.134179 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.067251 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.241848 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.241886 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.483734 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23374 # number of integer regfile reads +system.cpu.int_regfile_writes 13316 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -448,41 +448,41 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 314.403866 # Cycle average of tags in use -system.cpu.icache.total_refs 3230 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 314.165301 # Cycle average of tags in use +system.cpu.icache.total_refs 3236 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.159744 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.169329 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 314.403866 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.153518 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 3230 # number of ReadReq hits -system.cpu.icache.demand_hits 3230 # number of demand (read+write) hits -system.cpu.icache.overall_hits 3230 # number of overall hits +system.cpu.icache.occ_blocks::0 314.165301 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.153401 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 3236 # number of ReadReq hits +system.cpu.icache.demand_hits 3236 # number of demand (read+write) hits +system.cpu.icache.overall_hits 3236 # number of overall hits system.cpu.icache.ReadReq_misses 855 # number of ReadReq misses system.cpu.icache.demand_misses 855 # number of demand (read+write) misses system.cpu.icache.overall_misses 855 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::0 30717000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30717000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::0 30717000 # number of demand (read+write) miss cycles +system.cpu.icache.ReadReq_miss_latency::0 30710500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30710500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::0 30710500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30717000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::0 30717000 # number of overall miss cycles +system.cpu.icache.demand_miss_latency::total 30710500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::0 30710500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30717000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4085 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4085 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4085 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.209302 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.209302 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.209302 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 35926.315789 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35926.315789 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 35926.315789 # average overall miss latency +system.cpu.icache.overall_miss_latency::total 30710500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.208995 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.208995 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.208995 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::0 35918.713450 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35918.713450 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::0 35918.713450 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35926.315789 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 35926.315789 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35918.713450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 35918.713450 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35926.315789 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35918.713450 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,30 +513,30 @@ system.cpu.icache.overall_mshr_misses::total 626 system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::0 22275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::0 22275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::0 22267000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22267000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::0 22267000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::0 22275500 # number of overall MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22267000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::0 22267000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22267000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.153244 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153244 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.153244 # mshr miss rate for demand accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.153019 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153019 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.153019 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153244 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.153244 # mshr miss rate for overall accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153019 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.153019 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153244 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35583.865815 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::0 35583.865815 # average overall mshr miss latency +system.cpu.icache.overall_mshr_miss_rate::total 0.153019 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35570.287540 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35570.287540 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::0 35583.865815 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35570.287540 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency @@ -552,49 +552,49 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 216.203520 # Cycle average of tags in use -system.cpu.dcache.total_refs 4314 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 216.133399 # Cycle average of tags in use +system.cpu.dcache.total_refs 4323 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.432277 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.458213 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 216.203520 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.052784 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 3294 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 216.133399 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.052767 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 3303 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 1020 # number of WriteReq hits -system.cpu.dcache.demand_hits 4314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 4314 # number of overall hits -system.cpu.dcache.ReadReq_misses 306 # number of ReadReq misses +system.cpu.dcache.demand_hits 4323 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 4323 # number of overall hits +system.cpu.dcache.ReadReq_misses 308 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 710 # number of WriteReq misses -system.cpu.dcache.demand_misses 1016 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1016 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::0 11205000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11205000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::0 24076500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24076500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::0 35281500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_misses 1018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::0 11179500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11179500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::0 24106500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24106500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::0 35286000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35281500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::0 35281500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::total 35286000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::0 35286000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35281500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 3600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.overall_miss_latency::total 35286000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 3611 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 5330 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 5330 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.085000 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 5341 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 5341 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.085295 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.410405 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.190619 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.190619 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 36617.647059 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36617.647059 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33910.563380 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33910.563380 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 34725.885827 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.190601 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.190601 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::0 36297.077922 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36297.077922 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33952.816901 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33952.816901 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 34662.082515 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34725.885827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 34725.885827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34662.082515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 34662.082515 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34725.885827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34662.082515 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,16 +606,16 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::0 0 # number of writebacks system.cpu.dcache.writebacks::1 0 # number of writebacks system.cpu.dcache.writebacks::total 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::0 105 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::0 107 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::0 564 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::0 669 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::0 671 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 669 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::0 669 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::0 671 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 669 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::0 201 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses @@ -629,35 +629,35 @@ system.cpu.dcache.overall_mshr_misses::total 347 system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::0 7390000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7390000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::0 5293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::0 12683000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::0 5298000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5298000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::0 12674000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12683000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::0 12683000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12674000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::0 12674000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12683000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12674000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.055833 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055833 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.055663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055663 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.065103 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.064969 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.065103 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.065103 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064969 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.064969 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.065103 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36766.169154 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36253.424658 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36550.432277 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::total 0.064969 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36696.517413 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36287.671233 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36524.495677 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36550.432277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36524.495677 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency @@ -673,13 +673,13 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 435.485428 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 435.235373 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 435.485428 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.013290 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 435.235373 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.013282 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits @@ -687,16 +687,16 @@ system.cpu.l2cache.ReadReq_misses 825 # nu system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses system.cpu.l2cache.demand_misses 971 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 971 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::0 28485000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28485000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::0 5065500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5065500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::0 33550500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::0 28470000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28470000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::0 5066000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5066000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::0 33536000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33550500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::0 33550500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 33536000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::0 33536000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33550500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33536000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 827 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses @@ -705,16 +705,16 @@ system.cpu.l2cache.ReadReq_miss_rate 0.997582 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.997945 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.997945 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34527.272727 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34527.272727 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34695.205479 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34695.205479 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::0 34552.523172 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34509.090909 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34509.090909 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34698.630137 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34698.630137 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::0 34537.590113 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34552.523172 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::0 34552.523172 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34537.590113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::0 34537.590113 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34552.523172 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34537.590113 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -745,16 +745,16 @@ system.cpu.l2cache.overall_mshr_misses::total 971 system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25905000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25905000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::0 30518500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25887000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25887000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4614000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4614000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::0 30501000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30518500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::0 30518500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::0 30501000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30518500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -768,12 +768,12 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997945 system.cpu.l2cache.overall_mshr_miss_rate::0 0.997945 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997945 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31599.315068 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31429.969104 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31378.181818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31602.739726 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31429.969104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 636722350..8de42a2d1 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:08:13 -gem5 started Jul 8 2011 15:22:48 +gem5 compiled Jul 15 2011 17:51:42 +gem5 started Jul 15 2011 20:49:40 gem5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 18121000 because target called exit() +Exiting @ tick 18114000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 34c9dc344..44f3bc0f0 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18121000 # Number of ticks simulated +sim_ticks 18114000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 13353 # Simulator instruction rate (inst/s) -host_tick_rate 16745708 # Simulator tick rate (ticks/s) -host_mem_usage 246680 # Number of bytes of host memory used -host_seconds 1.08 # Real time elapsed on the host +host_inst_rate 40525 # Simulator instruction rate (inst/s) +host_tick_rate 50798832 # Simulator tick rate (ticks/s) +host_mem_usage 250076 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 36243 # number of cpu cycles simulated +system.cpu.numCycles 36229 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 5652 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3765 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 848 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5024 # Number of BTB lookups +system.cpu.BPredUnit.lookups 5641 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3757 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 847 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5015 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 10750 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 25938 # Number of instructions fetch has processed -system.cpu.fetch.Branches 5652 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 10704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 25822 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5641 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8192 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2326 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6715 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 8176 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2307 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6717 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 4621 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 374 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 27680 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.937066 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.038861 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 4608 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.935376 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.035144 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19488 70.40% 70.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4056 14.65% 85.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 538 1.94% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 473 1.71% 88.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 725 2.62% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 641 2.32% 93.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 275 0.99% 94.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 240 0.87% 95.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1244 4.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19430 70.38% 70.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4056 14.69% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 538 1.95% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 472 1.71% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 725 2.63% 91.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 639 2.31% 93.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 274 0.99% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 241 0.87% 95.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1231 4.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 27680 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.155947 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715669 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11171 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7401 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7541 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1378 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24386 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1378 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11668 # Number of cycles rename is idle +system.cpu.fetch.rateDist::total 27606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155704 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.712744 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11125 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7403 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7524 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1364 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24270 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1364 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11622 # Number of cycles rename is idle system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6686 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7269 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 454 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22625 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 6687 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7253 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 455 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22509 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 20272 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41976 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 41976 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 20189 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41765 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 41765 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6440 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6357 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 639 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 632 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2436 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3146 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2001 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.rename.tempSerializingInsts 633 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2443 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3114 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1976 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 19436 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18669 # Number of instructions issued +system.cpu.iq.iqInstsIssued 18581 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4953 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4052 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4856 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3975 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 27680 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674458 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.255150 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 27606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.673078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.254278 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19155 69.20% 69.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3456 12.49% 81.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2226 8.04% 89.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1550 5.60% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 660 2.38% 97.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 386 1.39% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19117 69.25% 69.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3446 12.48% 81.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2219 8.04% 89.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1536 5.56% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 657 2.38% 97.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 384 1.39% 99.11% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 27680 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27606 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available @@ -136,114 +136,114 @@ system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13814 73.99% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2983 15.98% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1872 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13779 74.16% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2952 15.89% 90.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1850 9.96% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18669 # Type of FU issued -system.cpu.iq.rate 0.515106 # Inst issue rate +system.cpu.iq.FU_type_0::total 18581 # Type of FU issued +system.cpu.iq.rate 0.512876 # Inst issue rate system.cpu.iq.fu_busy_cnt 139 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007445 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 65238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 25029 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17501 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.007481 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 64988 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 24825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17429 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18808 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18720 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 920 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 888 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 553 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 528 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1378 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21162 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 21045 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3146 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2001 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 3114 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1976 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 577 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 948 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17934 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2892 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 735 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 944 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17855 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2862 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 726 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1111 # number of nop insts executed -system.cpu.iew.exec_refs 4666 # number of memory reference insts executed -system.cpu.iew.exec_branches 3968 # Number of branches executed -system.cpu.iew.exec_stores 1774 # Number of stores executed -system.cpu.iew.exec_rate 0.494827 # Inst execution rate -system.cpu.iew.wb_sent 17667 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 17501 # cumulative count of insts written-back -system.cpu.iew.wb_producers 8169 # num instructions producing a value -system.cpu.iew.wb_consumers 9773 # num instructions consuming a value +system.cpu.iew.exec_nop 1102 # number of nop insts executed +system.cpu.iew.exec_refs 4620 # number of memory reference insts executed +system.cpu.iew.exec_branches 3963 # Number of branches executed +system.cpu.iew.exec_stores 1758 # Number of stores executed +system.cpu.iew.exec_rate 0.492837 # Inst execution rate +system.cpu.iew.wb_sent 17592 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 17429 # cumulative count of insts written-back +system.cpu.iew.wb_producers 8123 # num instructions producing a value +system.cpu.iew.wb_consumers 9726 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.482879 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.835874 # average fanout of values written-back +system.cpu.iew.wb_rate 0.481079 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5911 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 848 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26319 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.576580 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.276701 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 26259 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.577897 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.280480 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19114 72.62% 72.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4004 15.21% 87.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1216 4.62% 92.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 789 3.00% 95.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 371 1.41% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 322 1.22% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 345 1.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 56 0.21% 99.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19069 72.62% 72.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3994 15.21% 87.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1208 4.60% 92.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 790 3.01% 95.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 369 1.41% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 322 1.23% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 345 1.31% 99.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 57 0.22% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 105 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26319 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle system.cpu.commit.count 15175 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 3674 # Number of memory references committed @@ -253,48 +253,48 @@ system.cpu.commit.branches 3359 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12186 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 46480 # The number of ROB reads -system.cpu.rob.rob_writes 43556 # The number of ROB writes -system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8563 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 46300 # The number of ROB reads +system.cpu.rob.rob_writes 43308 # The number of ROB writes +system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.508340 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.508340 # CPI: Total CPI of All Threads -system.cpu.ipc 0.398670 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.398670 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28668 # number of integer regfile reads -system.cpu.int_regfile_writes 15998 # number of integer regfile writes -system.cpu.misc_regfile_reads 6298 # number of misc regfile reads +system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads +system.cpu.ipc 0.398824 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.398824 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28557 # number of integer regfile reads +system.cpu.int_regfile_writes 15938 # number of integer regfile writes +system.cpu.misc_regfile_reads 6251 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 193.254298 # Cycle average of tags in use -system.cpu.icache.total_refs 4159 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 193.216525 # Cycle average of tags in use +system.cpu.icache.total_refs 4151 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.527108 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 193.254298 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.094362 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 4159 # number of ReadReq hits -system.cpu.icache.demand_hits 4159 # number of demand (read+write) hits -system.cpu.icache.overall_hits 4159 # number of overall hits -system.cpu.icache.ReadReq_misses 462 # number of ReadReq misses -system.cpu.icache.demand_misses 462 # number of demand (read+write) misses -system.cpu.icache.overall_misses 462 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16041500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16041500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16041500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4621 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4621 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.099978 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.099978 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.099978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34721.861472 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34721.861472 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34721.861472 # average overall miss latency +system.cpu.icache.occ_blocks::0 193.216525 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.094344 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 4151 # number of ReadReq hits +system.cpu.icache.demand_hits 4151 # number of demand (read+write) hits +system.cpu.icache.overall_hits 4151 # number of overall hits +system.cpu.icache.ReadReq_misses 457 # number of ReadReq misses +system.cpu.icache.demand_misses 457 # number of demand (read+write) misses +system.cpu.icache.overall_misses 457 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15956000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15956000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15956000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.099175 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.099175 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.099175 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34914.660832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34914.660832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34914.660832 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,9 +304,9 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 130 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 130 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 125 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 125 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 125 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses @@ -315,9 +315,9 @@ system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.071846 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.071846 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.071846 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.072049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.072049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.072049 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency @@ -326,18 +326,18 @@ system.cpu.icache.mshr_cap_events 0 # nu system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.161362 # Cycle average of tags in use -system.cpu.dcache.total_refs 3736 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use +system.cpu.dcache.total_refs 3712 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.589041 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.161362 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.024942 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 2696 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 102.149831 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.024939 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 2672 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.demand_hits 3730 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 3730 # number of overall hits +system.cpu.dcache.demand_hits 3706 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 3706 # number of overall hits system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses system.cpu.dcache.demand_misses 522 # number of demand (read+write) misses @@ -346,15 +346,15 @@ system.cpu.dcache.ReadReq_miss_latency 3994500 # nu system.cpu.dcache.WriteReq_miss_latency 14649500 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency 18644000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency 18644000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 2810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses 2786 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 4252 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 4252 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.040569 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 4228 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 4228 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.040919 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.122766 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.122766 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate 0.123463 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.123463 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency 35716.475096 # average overall miss latency @@ -382,10 +382,10 @@ system.cpu.dcache.WriteReq_mshr_miss_latency 2985000 system.cpu.dcache.demand_mshr_miss_latency 5226500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 5226500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.022420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.022613 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.034337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.034337 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate 0.034532 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.034532 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency @@ -395,13 +395,13 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 228.417094 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 228.417094 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006971 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 228.374360 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006969 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index c3cdcc73a..67f90c44c 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:08:13 -gem5 started Jul 8 2011 15:22:59 +gem5 compiled Jul 18 2011 17:36:58 +gem5 started Jul 18 2011 17:37:01 gem5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -15,19 +15,19 @@ Init done [Iteration 1, Thread 3] Got lock [Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 Iteration 1 completed +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 2, Thread 2] Got lock [Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 Iteration 3 completed [Iteration 4, Thread 1] Got lock [Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 @@ -36,19 +36,19 @@ Iteration 3 completed [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 Iteration 4 completed -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 @@ -57,26 +57,26 @@ Iteration 6 completed [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 Iteration 8 completed +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 9, Thread 2] Got lock [Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 Iteration 9 completed +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 10, Thread 1] Got lock [Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 104204500 because target called exit() +Exiting @ tick 104314500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 80611aaa5..30cbeea1f 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000104 # Number of seconds simulated -sim_ticks 104204500 # Number of ticks simulated +sim_ticks 104314500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98850 # Simulator instruction rate (inst/s) -host_tick_rate 10137150 # Simulator tick rate (ticks/s) -host_mem_usage 260004 # Number of bytes of host memory used -host_seconds 10.28 # Real time elapsed on the host -sim_insts 1016120 # Number of instructions simulated +host_inst_rate 102986 # Simulator instruction rate (inst/s) +host_tick_rate 10543012 # Simulator tick rate (ticks/s) +host_mem_usage 263248 # Number of bytes of host memory used +host_seconds 9.89 # Real time elapsed on the host +sim_insts 1018958 # Number of instructions simulated system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 208410 # number of cpu cycles simulated +system.cpu0.numCycles 208630 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 80590 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 78618 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1041 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 79686 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 77242 # Number of BTB hits +system.cpu0.BPredUnit.lookups 80647 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 78658 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1043 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 79786 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 77333 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 414 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 410 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16537 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 478571 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 80590 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77656 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 158025 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3261 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12770 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 16573 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 478963 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 80647 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 158144 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3218 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 12869 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1227 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5521 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 190625 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.510536 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.192774 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 447 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 190842 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.509736 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.192738 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 32600 17.10% 17.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78462 41.16% 58.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 548 0.29% 58.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1030 0.54% 59.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 642 0.34% 59.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 74529 39.10% 98.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 776 0.41% 98.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 250 0.13% 99.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 1788 0.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32698 17.13% 17.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78519 41.14% 58.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 548 0.29% 58.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 993 0.52% 59.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 666 0.35% 59.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 74596 39.09% 98.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 803 0.42% 98.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 245 0.13% 99.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 1774 0.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 190625 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.386690 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.296296 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16909 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14231 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 157125 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 299 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2061 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 476395 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2061 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17525 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1226 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12360 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 156835 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 618 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 473886 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 190842 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.386555 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.295753 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16953 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14325 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 157237 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 303 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2024 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 476777 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2024 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17557 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1397 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 156961 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 623 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 474190 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 214 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 323802 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 945058 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 945058 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 313352 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10450 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 798 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 821 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3525 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 151968 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 76679 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 74216 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 74111 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 396475 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.LSQFullEvents 220 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 324005 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 945716 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 945716 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 313636 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10369 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 805 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 826 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3607 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 152098 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 76745 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 74317 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 74189 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 396736 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 848 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 394743 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8405 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 7242 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqInstsIssued 395043 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8301 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 7145 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 289 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 190625 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.070783 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.085610 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 190842 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.070000 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.087097 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 31655 16.61% 16.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5136 2.69% 19.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 75959 39.85% 59.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 75246 39.47% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1565 0.82% 99.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 775 0.41% 99.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 215 0.11% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 66 0.03% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 31780 16.65% 16.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5153 2.70% 19.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 75954 39.80% 59.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 75299 39.46% 98.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1583 0.83% 99.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 772 0.40% 99.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 222 0.12% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 71 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 8 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 190625 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 190842 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 35 15.42% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 74 32.60% 48.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 118 51.98% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 35 14.96% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 14.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 80 34.19% 49.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 119 50.85% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 166789 42.25% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 166899 42.25% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.25% # Type of FU issued @@ -165,137 +165,137 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.25% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 151686 38.43% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 76268 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 151806 38.43% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 76338 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 394743 # Type of FU issued -system.cpu0.iq.rate 1.894069 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 227 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000575 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 980437 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405782 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 393268 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 395043 # Type of FU issued +system.cpu0.iq.rate 1.893510 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 234 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000592 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 981260 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405931 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 393580 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 394970 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 395277 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 73850 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 73924 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1708 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1696 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1043 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1038 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2061 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 862 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 472051 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 355 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 151968 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 76679 # Number of dispatched store instructions +system.cpu0.iew.iewSquashCycles 2024 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1027 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 472386 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 357 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 152098 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 76745 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 747 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 747 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1203 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 393858 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 151382 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 885 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 734 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1201 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 394160 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 151501 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 883 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 74728 # number of nop insts executed -system.cpu0.iew.exec_refs 227540 # number of memory reference insts executed -system.cpu0.iew.exec_branches 78360 # Number of branches executed -system.cpu0.iew.exec_stores 76158 # Number of stores executed -system.cpu0.iew.exec_rate 1.889823 # Inst execution rate -system.cpu0.iew.wb_sent 393529 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 393268 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 233079 # num instructions producing a value -system.cpu0.iew.wb_consumers 235200 # num instructions consuming a value +system.cpu0.iew.exec_nop 74802 # number of nop insts executed +system.cpu0.iew.exec_refs 227729 # number of memory reference insts executed +system.cpu0.iew.exec_branches 78433 # Number of branches executed +system.cpu0.iew.exec_stores 76228 # Number of stores executed +system.cpu0.iew.exec_rate 1.889278 # Inst execution rate +system.cpu0.iew.wb_sent 393840 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 393580 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 233254 # num instructions producing a value +system.cpu0.iew.wb_consumers 235363 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.886992 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990982 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.886498 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.991039 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 462373 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 9639 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 462799 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 9548 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1041 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 188581 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.451854 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.134496 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1043 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 188835 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.450812 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.134995 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32178 17.06% 17.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 78251 41.49% 58.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2149 1.14% 59.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 733 0.39% 60.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 648 0.34% 60.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 73572 39.01% 99.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 474 0.25% 99.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 279 0.15% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 297 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32324 17.12% 17.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 78261 41.44% 58.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2190 1.16% 59.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 719 0.38% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 660 0.35% 60.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 73613 38.98% 99.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 484 0.26% 99.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 280 0.15% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 304 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 188581 # Number of insts commited each cycle -system.cpu0.commit.count 462373 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 188835 # Number of insts commited each cycle +system.cpu0.commit.count 462799 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 225896 # Number of memory references committed -system.cpu0.commit.loads 150260 # Number of loads committed +system.cpu0.commit.refs 226109 # Number of memory references committed +system.cpu0.commit.loads 150402 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 77524 # Number of branches committed +system.cpu0.commit.branches 77595 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 311682 # Number of committed integer instructions. +system.cpu0.commit.int_insts 311966 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 297 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 304 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 659135 # The number of ROB reads -system.cpu0.rob.rob_writes 946098 # The number of ROB writes +system.cpu0.rob.rob_reads 659717 # The number of ROB reads +system.cpu0.rob.rob_writes 946730 # The number of ROB writes system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 17785 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 388034 # Number of Instructions Simulated -system.cpu0.committedInsts_total 388034 # Number of Instructions Simulated -system.cpu0.cpi 0.537092 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.537092 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.861878 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.861878 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 704687 # number of integer regfile reads -system.cpu0.int_regfile_writes 317694 # number of integer regfile writes +system.cpu0.idleCycles 17788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 388389 # Number of Instructions Simulated +system.cpu0.committedInsts_total 388389 # Number of Instructions Simulated +system.cpu0.cpi 0.537168 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.537168 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.861616 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.861616 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 705237 # number of integer regfile reads +system.cpu0.int_regfile_writes 317939 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 229306 # number of misc regfile reads +system.cpu0.misc_regfile_reads 229506 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.replacements 294 # number of replacements -system.cpu0.icache.tagsinuse 244.310261 # Cycle average of tags in use -system.cpu0.icache.total_refs 4819 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 244.353542 # Cycle average of tags in use +system.cpu0.icache.total_refs 4816 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.294320 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 8.289157 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 244.310261 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.477168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 4819 # number of ReadReq hits -system.cpu0.icache.demand_hits 4819 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 4819 # number of overall hits -system.cpu0.icache.ReadReq_misses 702 # number of ReadReq misses -system.cpu0.icache.demand_misses 702 # number of demand (read+write) misses -system.cpu0.icache.overall_misses 702 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 27601000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 27601000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 27601000 # number of overall miss cycles +system.cpu0.icache.occ_blocks::0 244.353542 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.477253 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits 4816 # number of ReadReq hits +system.cpu0.icache.demand_hits 4816 # number of demand (read+write) hits +system.cpu0.icache.overall_hits 4816 # number of overall hits +system.cpu0.icache.ReadReq_misses 705 # number of ReadReq misses +system.cpu0.icache.demand_misses 705 # number of demand (read+write) misses +system.cpu0.icache.overall_misses 705 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 27621000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 27621000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 27621000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses 5521 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses 5521 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses 5521 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.127151 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.127151 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.127151 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency 39317.663818 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency 39317.663818 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 39317.663818 # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate 0.127694 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate 0.127694 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate 0.127694 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency 39178.723404 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency 39178.723404 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency 39178.723404 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -305,67 +305,67 @@ system.cpu0.icache.avg_blocked_cycles::no_targets no_value system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 120 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 123 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses 582 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses 582 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses 582 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 21371000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 21371000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 21371000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 21370500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 21370500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 21370500 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.105416 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate 0.105416 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate 0.105416 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36719.931271 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 36719.931271 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 36719.931271 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36719.072165 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 36719.072165 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 36719.072165 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 139.593674 # Cycle average of tags in use -system.cpu0.dcache.total_refs 95831 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 139.605252 # Cycle average of tags in use +system.cpu0.dcache.total_refs 97332 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 550.752874 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 559.379310 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 140.420812 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -0.827138 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.274259 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 140.432639 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -0.827387 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.274282 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::1 -0.001616 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 76983 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits 75054 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits 77006 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits 75125 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits 23 # number of SwapReq hits -system.cpu0.dcache.demand_hits 152037 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 152037 # number of overall hits -system.cpu0.dcache.ReadReq_misses 495 # number of ReadReq misses +system.cpu0.dcache.demand_hits 152131 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits 152131 # number of overall hits +system.cpu0.dcache.ReadReq_misses 517 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses 19 # number of SwapReq misses -system.cpu0.dcache.demand_misses 1035 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses 1035 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 13943500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 24690984 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency 375000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency 38634484 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 38634484 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 77478 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses 75594 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses 1057 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses 1057 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 14689500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 24684984 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency 371000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency 39374484 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 39374484 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses 77523 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses 75665 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 153072 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 153072 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate 0.006389 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate 0.007143 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses 153188 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses 153188 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate 0.006669 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate 0.007137 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate 0.452381 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate 0.006762 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate 0.006762 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency 28168.686869 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency 45724.044444 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency 19736.842105 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency 37328.003865 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 37328.003865 # average overall miss latency +system.cpu0.dcache.demand_miss_rate 0.006900 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate 0.006900 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency 28412.959381 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency 45712.933333 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency 19526.315789 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency 37251.167455 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency 37251.167455 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -375,324 +375,324 @@ system.cpu0.dcache.avg_blocked_cycles::no_targets no_value system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 308 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 369 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 677 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 677 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 187 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 171 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits 327 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 368 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 695 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 695 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 190 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 172 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses 19 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses +system.cpu0.dcache.demand_mshr_misses 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 362 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 5126500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency 5221000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency 6255000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency 318000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 11381500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 11381500 # number of overall MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency 314000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 11476000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 11476000 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002414 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002262 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002273 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate 0.452381 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate 0.002339 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate 0.002339 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27414.438503 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36578.947368 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16736.842105 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 31791.899441 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 31791.899441 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate 0.002363 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate 0.002363 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27478.947368 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36366.279070 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16526.315789 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 31701.657459 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 31701.657459 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 174065 # number of cpu cycles simulated +system.cpu1.numCycles 174299 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 53680 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 51050 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1082 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 49680 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 47696 # Number of BTB hits +system.cpu1.BPredUnit.lookups 52109 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 49472 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1085 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 48061 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 46077 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 674 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 697 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 25860 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 302062 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53680 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 48370 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 105407 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3162 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 31070 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 26834 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 291727 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52109 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46774 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 102734 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3160 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 32953 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6439 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 670 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 17358 # Number of cache lines fetched +system.cpu1.fetch.CacheLines 18341 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 181 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 171455 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.761757 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.155300 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::samples 171592 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.700120 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.136214 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66048 38.52% 38.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 53266 31.07% 69.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5206 3.04% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3414 1.99% 74.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 592 0.35% 74.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 38163 22.26% 97.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1383 0.81% 98.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 403 0.24% 98.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 2980 1.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 68858 40.13% 40.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52174 30.41% 70.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5705 3.32% 73.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3354 1.95% 75.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 589 0.34% 76.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 36150 21.07% 97.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1352 0.79% 98.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 417 0.24% 98.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 2993 1.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 171455 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.308391 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.735340 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 30212 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 28102 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 100316 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4382 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2004 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 299336 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2004 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 30858 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 13502 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13779 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 96392 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 8481 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 297385 # Number of instructions processed by rename +system.cpu1.fetch.rateDist::total 171592 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.298963 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.673716 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 31662 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 29517 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 97188 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4829 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1999 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 288965 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1999 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 32299 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 14957 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13738 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 92828 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 9374 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 287067 # Number of instructions processed by rename system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 208391 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 574206 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 574206 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 198747 # Number of HB maps that are committed +system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 200824 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 551922 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 551922 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 191180 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 9644 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1073 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1204 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 11164 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 85765 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 40966 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 40880 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 36423 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 247992 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5619 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 250090 # Number of instructions issued +system.cpu1.rename.serializingInsts 1080 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 11997 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 82177 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38952 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 39303 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 34405 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 238842 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6064 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 241475 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 8378 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 7678 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 171455 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.458633 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.309488 # Number of insts issued each cycle +system.cpu1.iq.iqSquashedInstsExamined 8361 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 7490 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 171592 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.407263 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.310082 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 63066 36.78% 36.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 20362 11.88% 48.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 40913 23.86% 72.52% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 42366 24.71% 97.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3338 1.95% 99.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1156 0.67% 99.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 160 0.09% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 65840 38.37% 38.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 21732 12.66% 51.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 38889 22.66% 73.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 40378 23.53% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3339 1.95% 99.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1157 0.67% 99.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 163 0.09% 99.95% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 40 0.02% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 171455 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 171592 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 12 4.58% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 60 22.90% 27.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 190 72.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 62 23.48% 28.03% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 190 71.97% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 120097 48.02% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.02% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 89434 35.76% 83.78% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 40559 16.22% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 116586 48.28% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 86332 35.75% 84.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 38557 15.97% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 250090 # Type of FU issued -system.cpu1.iq.rate 1.436762 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 262 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001048 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 671900 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 262020 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 248980 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 241475 # Type of FU issued +system.cpu1.iq.rate 1.385407 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001093 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 654809 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 253298 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 240376 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 250352 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 241739 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 36283 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 34273 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1818 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1784 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 31 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 869 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 861 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2004 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1662 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 295488 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 85765 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 40966 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1999 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1765 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 285192 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 302 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 82177 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38952 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1043 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 31 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 608 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1239 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 249342 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 84980 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 748 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 599 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 655 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1254 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 240736 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 81423 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 739 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41877 # number of nop insts executed -system.cpu1.iew.exec_refs 125494 # number of memory reference insts executed -system.cpu1.iew.exec_branches 50909 # Number of branches executed -system.cpu1.iew.exec_stores 40514 # Number of stores executed -system.cpu1.iew.exec_rate 1.432465 # Inst execution rate -system.cpu1.iew.wb_sent 249148 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 248980 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 142220 # num instructions producing a value -system.cpu1.iew.wb_consumers 146685 # num instructions consuming a value +system.cpu1.iew.exec_nop 40286 # number of nop insts executed +system.cpu1.iew.exec_refs 119940 # number of memory reference insts executed +system.cpu1.iew.exec_branches 49359 # Number of branches executed +system.cpu1.iew.exec_stores 38517 # Number of stores executed +system.cpu1.iew.exec_rate 1.381167 # Inst execution rate +system.cpu1.iew.wb_sent 240543 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 240376 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 136693 # num instructions producing a value +system.cpu1.iew.wb_consumers 141184 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.430385 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.969561 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.379101 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.968190 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 285859 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 9624 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4971 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1082 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 163013 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.753596 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.061352 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 275649 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 9533 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5427 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1085 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 163197 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.689057 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.043019 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61328 37.62% 37.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 49151 30.15% 67.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5963 3.66% 71.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5859 3.59% 75.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1587 0.97% 76.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 36625 22.47% 98.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 608 0.37% 98.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1052 0.65% 99.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 840 0.52% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 64641 39.61% 39.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 47584 29.16% 68.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5957 3.65% 72.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6309 3.87% 76.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.96% 77.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 34599 21.20% 98.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 646 0.40% 98.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1051 0.64% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 839 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 163013 # Number of insts commited each cycle -system.cpu1.commit.count 285859 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 163197 # Number of insts commited each cycle +system.cpu1.commit.count 275649 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 124044 # Number of memory references committed -system.cpu1.commit.loads 83947 # Number of loads committed -system.cpu1.commit.membars 4259 # Number of memory barriers committed -system.cpu1.commit.branches 50321 # Number of branches committed +system.cpu1.commit.refs 118484 # Number of memory references committed +system.cpu1.commit.loads 80393 # Number of loads committed +system.cpu1.commit.membars 4716 # Number of memory barriers committed +system.cpu1.commit.branches 48770 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 196488 # Number of committed integer instructions. +system.cpu1.commit.int_insts 189379 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 840 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 839 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 457069 # The number of ROB reads -system.cpu1.rob.rob_writes 592971 # The number of ROB writes -system.cpu1.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2610 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 240487 # Number of Instructions Simulated -system.cpu1.committedInsts_total 240487 # Number of Instructions Simulated -system.cpu1.cpi 0.723802 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.723802 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.381593 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.381593 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 434614 # number of integer regfile reads -system.cpu1.int_regfile_writes 202365 # number of integer regfile writes +system.cpu1.rob.rob_reads 446953 # The number of ROB reads +system.cpu1.rob.rob_writes 572364 # The number of ROB writes +system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2707 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 231370 # Number of Instructions Simulated +system.cpu1.committedInsts_total 231370 # Number of Instructions Simulated +system.cpu1.cpi 0.753334 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.753334 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.327432 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.327432 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 418038 # number of integer regfile reads +system.cpu1.int_regfile_writes 194832 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 127051 # number of misc regfile reads +system.cpu1.misc_regfile_reads 121491 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 84.485339 # Cycle average of tags in use -system.cpu1.icache.total_refs 16887 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 84.540462 # Cycle average of tags in use +system.cpu1.icache.total_refs 17870 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 39.548009 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 41.850117 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 84.485339 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.165010 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits 16887 # number of ReadReq hits -system.cpu1.icache.demand_hits 16887 # number of demand (read+write) hits -system.cpu1.icache.overall_hits 16887 # number of overall hits +system.cpu1.icache.occ_blocks::0 84.540462 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.165118 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits 17870 # number of ReadReq hits +system.cpu1.icache.demand_hits 17870 # number of demand (read+write) hits +system.cpu1.icache.overall_hits 17870 # number of overall hits system.cpu1.icache.ReadReq_misses 471 # number of ReadReq misses system.cpu1.icache.demand_misses 471 # number of demand (read+write) misses system.cpu1.icache.overall_misses 471 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7156000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7156000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7156000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses 17358 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses 17358 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses 17358 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate 0.027134 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate 0.027134 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate 0.027134 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency 15193.205945 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency 15193.205945 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency 15193.205945 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency 7203000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7203000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7203000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses 18341 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses 18341 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses 18341 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate 0.025680 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate 0.025680 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate 0.025680 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency 15292.993631 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency 15292.993631 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency 15292.993631 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -709,60 +709,60 @@ system.cpu1.icache.ReadReq_mshr_misses 427 # nu system.cpu1.icache.demand_mshr_misses 427 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses 427 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5329000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5329000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5329000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5374000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5374000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5374000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.024600 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate 0.024600 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate 0.024600 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12480.093677 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12480.093677 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12480.093677 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate 0.023281 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate 0.023281 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate 0.023281 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12585.480094 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 12585.480094 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 12585.480094 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 18.326142 # Cycle average of tags in use -system.cpu1.dcache.total_refs 46034 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1587.379310 # Average number of references to valid blocks. +system.cpu1.dcache.tagsinuse 18.587934 # Cycle average of tags in use +system.cpu1.dcache.total_refs 44079 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1469.300000 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 24.418432 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -6.092290 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.047692 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::1 -0.011899 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 48212 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 39908 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits 88120 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 88120 # number of overall hits -system.cpu1.dcache.ReadReq_misses 470 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses 123 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses 54 # number of SwapReq misses -system.cpu1.dcache.demand_misses 593 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses 593 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 9944500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 2927000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency 1215000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency 12871500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 12871500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 48682 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 40031 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 88713 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 88713 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.009654 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate 0.003073 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate 0.818182 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.006684 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.006684 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency 21158.510638 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency 23796.747967 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency 22500 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency 21705.733558 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 21705.733558 # average overall miss latency +system.cpu1.dcache.occ_blocks::0 24.401402 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -5.813468 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.047659 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::1 -0.011354 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits 46657 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits 37902 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits 13 # number of SwapReq hits +system.cpu1.dcache.demand_hits 84559 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits 84559 # number of overall hits +system.cpu1.dcache.ReadReq_misses 478 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses 124 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses 52 # number of SwapReq misses +system.cpu1.dcache.demand_misses 602 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses 602 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 10263500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 2943000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency 1147500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency 13206500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 13206500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses 47135 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses 38026 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses 85161 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses 85161 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate 0.010141 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate 0.003261 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate 0.007069 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate 0.007069 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency 21471.757322 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency 23733.870968 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency 22067.307692 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency 21937.707641 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency 21937.707641 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,324 +772,324 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets no_value system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 318 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits 323 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 336 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 152 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 257 # number of overall MSHR misses +system.cpu1.dcache.demand_mshr_hits 341 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 341 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 261 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 261 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 1992500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1603000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency 1053000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 3595500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 3595500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency 2081000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 1617000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency 991500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 3698000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 3698000 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003122 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002623 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.818182 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate 0.002897 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate 0.002897 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13108.552632 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15266.666667 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19500 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 13990.272374 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 13990.272374 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003288 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002788 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate 0.003065 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate 0.003065 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13425.806452 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15254.716981 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19067.307692 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 14168.582375 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14168.582375 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 173778 # number of cpu cycles simulated +system.cpu2.numCycles 174012 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 50805 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 48180 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1153 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 47027 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 44960 # Number of BTB hits +system.cpu2.BPredUnit.lookups 49364 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 46732 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1149 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 45640 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 43565 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 640 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 657 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 27007 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 283163 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 50805 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 45600 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 99886 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3304 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 32566 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 27807 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 273927 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 49364 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 44222 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 97488 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3286 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 34436 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6449 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 18144 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 200 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 168765 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.677854 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.125811 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6393 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 776 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 19059 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 204 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 168964 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.621215 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.105359 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 68879 40.81% 40.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 50491 29.92% 70.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5634 3.34% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3757 2.23% 76.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 707 0.42% 76.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 34670 20.54% 97.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1324 0.78% 98.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 413 0.24% 98.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2890 1.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 71476 42.30% 42.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 49527 29.31% 71.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6067 3.59% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3620 2.14% 77.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 727 0.43% 77.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 32912 19.48% 97.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1356 0.80% 98.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 430 0.25% 98.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2849 1.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 168765 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.292356 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.629453 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 31662 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 29441 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 94497 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4642 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2074 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 280431 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2074 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 32376 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 14418 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 14186 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90338 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 8924 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278200 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 53 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 195247 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 534109 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 534109 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 184829 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10418 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1050 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1186 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11541 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 79019 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 37409 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 37644 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 32854 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 231381 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 5925 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 233568 # Number of instructions issued +system.cpu2.fetch.rateDist::total 168964 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.283682 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.574185 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 32851 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 30934 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 91695 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5032 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2059 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 271116 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2059 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 33552 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 15710 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 14408 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 87161 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 9681 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 268912 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 31 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 188421 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 514106 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 514106 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 178126 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10295 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1067 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1200 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12338 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 75825 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 35625 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 36244 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 31069 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 223185 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6329 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 225866 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8776 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 8266 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 641 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 168765 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.383984 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.307813 # Number of insts issued each cycle +system.cpu2.iq.iqSquashedInstsExamined 8708 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 8050 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 168964 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.336770 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.306398 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 66154 39.20% 39.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 21382 12.67% 51.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 37723 22.35% 74.22% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38911 23.06% 97.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3386 2.01% 99.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 949 0.56% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 160 0.09% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68732 40.68% 40.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22583 13.37% 54.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 35943 21.27% 75.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 37102 21.96% 97.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3355 1.99% 99.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 981 0.58% 99.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 168 0.10% 99.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 42 0.02% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 58 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 168765 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 168964 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19 7.28% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 52 19.92% 27.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 190 72.80% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19 7.04% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 61 22.59% 29.63% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 190 70.37% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 113638 48.65% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.65% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 82927 35.50% 84.16% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 37003 15.84% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 110492 48.92% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 80155 35.49% 84.41% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 35219 15.59% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 233568 # Type of FU issued -system.cpu2.iq.rate 1.344060 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 261 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001117 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 636165 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 246114 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 232313 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 225866 # Type of FU issued +system.cpu2.iq.rate 1.297991 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 270 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001195 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 620969 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 238254 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 224626 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 233829 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 226136 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 32721 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 30939 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1885 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1843 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 861 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedStores 851 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2074 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1817 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 62 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275982 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 400 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 79019 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 37409 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 998 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2059 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1941 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 266778 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 75825 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 35625 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1017 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 32 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 681 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 621 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1302 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 232725 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 78144 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 843 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedTakenIncorrect 683 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 611 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1294 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 225033 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 74984 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 833 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 38676 # number of nop insts executed -system.cpu2.iew.exec_refs 115111 # number of memory reference insts executed -system.cpu2.iew.exec_branches 47758 # Number of branches executed -system.cpu2.iew.exec_stores 36967 # Number of stores executed -system.cpu2.iew.exec_rate 1.339209 # Inst execution rate -system.cpu2.iew.wb_sent 232494 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 232313 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 131935 # num instructions producing a value -system.cpu2.iew.wb_consumers 136342 # num instructions consuming a value +system.cpu2.iew.exec_nop 37264 # number of nop insts executed +system.cpu2.iew.exec_refs 110168 # number of memory reference insts executed +system.cpu2.iew.exec_branches 46372 # Number of branches executed +system.cpu2.iew.exec_stores 35184 # Number of stores executed +system.cpu2.iew.exec_rate 1.293204 # Inst execution rate +system.cpu2.iew.wb_sent 224799 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 224626 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 127004 # num instructions producing a value +system.cpu2.iew.wb_consumers 131415 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.336838 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.967677 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.290865 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.966435 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 265754 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 10224 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5284 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1153 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 160243 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.658444 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.033027 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 256702 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 10072 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5686 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1149 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 160513 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.599260 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.012930 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 64923 40.52% 40.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46026 28.72% 69.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5970 3.73% 72.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6149 3.84% 76.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1628 1.02% 77.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 33154 20.69% 98.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 514 0.32% 98.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1057 0.66% 99.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 67920 42.31% 42.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 44667 27.83% 70.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6005 3.74% 73.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6542 4.08% 77.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1606 1.00% 78.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 31384 19.55% 98.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 504 0.31% 98.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1049 0.65% 99.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 836 0.52% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 160243 # Number of insts commited each cycle -system.cpu2.commit.count 265754 # Number of instructions committed +system.cpu2.commit.committed_per_cycle::total 160513 # Number of insts commited each cycle +system.cpu2.commit.count 256702 # Number of instructions committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 113682 # Number of memory references committed -system.cpu2.commit.loads 77134 # Number of loads committed -system.cpu2.commit.membars 4565 # Number of memory barriers committed -system.cpu2.commit.branches 47078 # Number of branches committed +system.cpu2.commit.refs 108756 # Number of memory references committed +system.cpu2.commit.loads 73982 # Number of loads committed +system.cpu2.commit.membars 4966 # Number of memory barriers committed +system.cpu2.commit.branches 45703 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 182876 # Number of committed integer instructions. +system.cpu2.commit.int_insts 176575 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 836 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 434812 # The number of ROB reads -system.cpu2.rob.rob_writes 554033 # The number of ROB writes -system.cpu2.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5013 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.committedInsts 223326 # Number of Instructions Simulated -system.cpu2.committedInsts_total 223326 # Number of Instructions Simulated -system.cpu2.cpi 0.778136 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.778136 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.285122 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.285122 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 403849 # number of integer regfile reads -system.cpu2.int_regfile_writes 188623 # number of integer regfile writes +system.cpu2.rob.rob_reads 425864 # The number of ROB reads +system.cpu2.rob.rob_writes 535611 # The number of ROB writes +system.cpu2.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5048 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.committedInsts 215249 # Number of Instructions Simulated +system.cpu2.committedInsts_total 215249 # Number of Instructions Simulated +system.cpu2.cpi 0.808422 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.808422 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.236978 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.236978 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 389041 # number of integer regfile reads +system.cpu2.int_regfile_writes 181914 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 116687 # number of misc regfile reads +system.cpu2.misc_regfile_reads 111743 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 323 # number of replacements -system.cpu2.icache.tagsinuse 85.152335 # Cycle average of tags in use -system.cpu2.icache.total_refs 17658 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 41.160839 # Average number of references to valid blocks. +system.cpu2.icache.replacements 321 # number of replacements +system.cpu2.icache.tagsinuse 85.226905 # Cycle average of tags in use +system.cpu2.icache.total_refs 18578 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 427 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 43.508197 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 85.152335 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.166313 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits 17658 # number of ReadReq hits -system.cpu2.icache.demand_hits 17658 # number of demand (read+write) hits -system.cpu2.icache.overall_hits 17658 # number of overall hits -system.cpu2.icache.ReadReq_misses 486 # number of ReadReq misses -system.cpu2.icache.demand_misses 486 # number of demand (read+write) misses -system.cpu2.icache.overall_misses 486 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency 10409000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency 10409000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency 10409000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses 18144 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses 18144 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses 18144 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate 0.026786 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate 0.026786 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate 0.026786 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency 21417.695473 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency 21417.695473 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency 21417.695473 # average overall miss latency +system.cpu2.icache.occ_blocks::0 85.226905 # Average occupied blocks per context +system.cpu2.icache.occ_percent::0 0.166459 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits 18578 # number of ReadReq hits +system.cpu2.icache.demand_hits 18578 # number of demand (read+write) hits +system.cpu2.icache.overall_hits 18578 # number of overall hits +system.cpu2.icache.ReadReq_misses 481 # number of ReadReq misses +system.cpu2.icache.demand_misses 481 # number of demand (read+write) misses +system.cpu2.icache.overall_misses 481 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency 10446500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency 10446500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency 10446500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses 19059 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses 19059 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses 19059 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate 0.025237 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate 0.025237 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate 0.025237 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency 21718.295218 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency 21718.295218 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency 21718.295218 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1099,67 +1099,67 @@ system.cpu2.icache.avg_blocked_cycles::no_targets no_value system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits 57 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits 57 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses 429 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses 429 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses 429 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses 427 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses 427 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.ReadReq_mshr_miss_latency 7965500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency 7965500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency 7965500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency 8026500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency 8026500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency 8026500 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.023644 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate 0.023644 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate 0.023644 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18567.599068 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 18567.599068 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 18567.599068 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_rate 0.022404 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate 0.022404 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate 0.022404 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18797.423888 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 18797.423888 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 18797.423888 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 18.333268 # Cycle average of tags in use -system.cpu2.dcache.total_refs 42495 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1370.806452 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 19.370562 # Cycle average of tags in use +system.cpu2.dcache.total_refs 40685 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1356.166667 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 26.478684 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -8.145416 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.051716 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::1 -0.015909 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 44951 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 36350 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits 81301 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 81301 # number of overall hits -system.cpu2.dcache.ReadReq_misses 454 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses 125 # number of WriteReq misses +system.cpu2.dcache.occ_blocks::0 26.582675 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -7.212113 # Average occupied blocks per context +system.cpu2.dcache.occ_percent::0 0.051919 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::1 -0.014086 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits 43568 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits 34580 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits 78148 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits 78148 # number of overall hits +system.cpu2.dcache.ReadReq_misses 459 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses 120 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses 61 # number of SwapReq misses system.cpu2.dcache.demand_misses 579 # number of demand (read+write) misses system.cpu2.dcache.overall_misses 579 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency 10292500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency 2895500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency 1389500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency 13188000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 13188000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 45405 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 36475 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 81880 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 81880 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate 0.009999 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate 0.003427 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate 0.835616 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.007071 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.007071 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency 22670.704846 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency 23164 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency 22778.688525 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency 22777.202073 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 22777.202073 # average overall miss latency +system.cpu2.dcache.ReadReq_miss_latency 10996500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency 2980500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency 1342500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency 13977000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency 13977000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses 44027 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses 34700 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses 74 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses 78727 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses 78727 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate 0.010425 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate 0.003458 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate 0.824324 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate 0.007355 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate 0.007355 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency 23957.516340 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency 24837.500000 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency 22008.196721 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency 24139.896373 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency 24139.896373 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1169,324 +1169,324 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets no_value system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits 289 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits 307 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits 307 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses +system.cpu2.dcache.demand_mshr_hits 315 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits 315 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses 61 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses 272 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses 272 # number of overall MSHR misses +system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 2342500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency 1563000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency 1206500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency 3905500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 3905500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency 2379000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency 1660000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency 1159500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency 4039000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency 4039000 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003634 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002934 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.835616 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate 0.003322 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate 0.003322 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14196.969697 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 14607.476636 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19778.688525 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 14358.455882 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 14358.455882 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003680 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002939 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate 0.824324 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate 0.003353 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate 0.003353 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14685.185185 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16274.509804 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19008.196721 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 15299.242424 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 15299.242424 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 173512 # number of cpu cycles simulated +system.cpu3.numCycles 173746 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 40530 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 37937 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1057 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 36753 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 34800 # Number of BTB hits +system.cpu3.BPredUnit.lookups 43971 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 41359 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1065 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 40215 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 38240 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.BPredUnit.usedRAS 627 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 33125 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 215867 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 40530 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 35427 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 83007 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3046 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 45401 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 31228 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 238324 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 43971 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 38867 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 88896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3085 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 41810 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6445 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.NoActiveThreadStallCycles 6387 # Number of stall cycles due to no active thread to fetch from system.cpu3.fetch.PendingTrapStallCycles 706 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24871 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 170604 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.265310 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 1.931210 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.CacheLines 22959 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 170976 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.393903 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.001998 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 87597 51.35% 51.35% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 43833 25.69% 77.04% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8987 5.27% 82.31% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3510 2.06% 84.36% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 653 0.38% 84.75% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 21422 12.56% 97.30% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1319 0.77% 98.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 370 0.22% 98.29% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2913 1.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 82080 48.01% 48.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 46270 27.06% 75.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8028 4.70% 79.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3581 2.09% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 661 0.39% 82.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 25731 15.05% 97.29% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1333 0.78% 98.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 378 0.22% 98.30% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2914 1.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 170604 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.233586 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.244104 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 41023 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 38920 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 74503 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7798 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1915 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 213126 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1915 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 41660 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 23650 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 14461 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 67213 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 15260 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 211303 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 145000 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 387654 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 387654 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 135623 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 9377 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1053 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1194 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 17810 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 55847 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 24229 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 27736 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 19680 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 171446 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 9173 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 177208 # Number of instructions issued +system.cpu3.fetch.rateDist::total 170976 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.253076 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.371680 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 38250 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 36210 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 81243 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 6942 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1944 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 235564 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1944 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 38898 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 21197 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 14171 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 74835 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 13544 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 233632 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 34 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 161364 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 435904 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 435904 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 151913 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 9451 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1060 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1201 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 16222 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 63587 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 28570 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 31149 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 24015 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 191265 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8270 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 196039 # Number of instructions issued system.cpu3.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 8093 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 7434 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 618 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 170604 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.038710 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.248224 # Number of insts issued each cycle +system.cpu3.iq.iqSquashedInstsExamined 8200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 7610 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 629 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 170976 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.146588 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.276389 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 84759 49.68% 49.68% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 31065 18.21% 67.89% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24373 14.29% 82.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 25865 15.16% 97.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3284 1.92% 99.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1031 0.60% 99.87% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 132 0.08% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 79237 46.34% 46.34% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 28336 16.57% 62.92% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 28714 16.79% 79.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 30132 17.62% 97.33% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3289 1.92% 99.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1034 0.60% 99.86% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 139 0.08% 99.94% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::7 41 0.02% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 170604 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 170976 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 4.47% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 45 18.29% 22.76% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 190 77.24% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 11 4.49% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 44 17.96% 22.45% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 190 77.55% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 90240 50.92% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.92% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 63111 35.61% 86.54% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 23857 13.46% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 97956 49.97% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 69913 35.66% 85.63% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 28170 14.37% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 177208 # Type of FU issued -system.cpu3.iq.rate 1.021301 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 246 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001388 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 525269 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 188741 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 176086 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 196039 # Type of FU issued +system.cpu3.iq.rate 1.128308 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 245 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001250 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 563302 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 207766 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 194919 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 177454 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 196284 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 19589 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 23896 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1676 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1728 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 799 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 31 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 841 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1915 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1524 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 209347 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 55847 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 24229 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 987 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1944 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 231697 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 63587 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 28570 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 992 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 624 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 548 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1172 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 176425 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 55052 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 783 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 631 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 549 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1180 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 195258 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 62772 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 781 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 28728 # number of nop insts executed -system.cpu3.iew.exec_refs 78879 # number of memory reference insts executed -system.cpu3.iew.exec_branches 37783 # Number of branches executed -system.cpu3.iew.exec_stores 23827 # Number of stores executed -system.cpu3.iew.exec_rate 1.016788 # Inst execution rate -system.cpu3.iew.wb_sent 176246 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 176086 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 95644 # num instructions producing a value -system.cpu3.iew.wb_consumers 99967 # num instructions consuming a value +system.cpu3.iew.exec_nop 32162 # number of nop insts executed +system.cpu3.iew.exec_refs 90911 # number of memory reference insts executed +system.cpu3.iew.exec_branches 41188 # Number of branches executed +system.cpu3.iew.exec_stores 28139 # Number of stores executed +system.cpu3.iew.exec_rate 1.123813 # Inst execution rate +system.cpu3.iew.wb_sent 195076 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 194919 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 107666 # num instructions producing a value +system.cpu3.iew.wb_consumers 111983 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.014835 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.956756 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.121862 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.961450 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 200126 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 9211 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 8555 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1057 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 162245 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.233480 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.839252 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 222278 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 9409 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7641 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1065 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 162646 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.366637 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.912094 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 86736 53.46% 53.46% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 36031 22.21% 75.67% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6002 3.70% 79.37% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 9421 5.81% 85.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1631 1.01% 86.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 19977 12.31% 98.49% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 548 0.34% 98.83% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 80351 49.40% 49.40% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 39427 24.24% 73.64% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6019 3.70% 77.34% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8502 5.23% 82.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1632 1.00% 83.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 24254 14.91% 98.49% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 559 0.34% 98.83% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::7 1061 0.65% 99.48% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 838 0.52% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 841 0.52% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 162245 # Number of insts commited each cycle -system.cpu3.commit.count 200126 # Number of instructions committed +system.cpu3.commit.committed_per_cycle::total 162646 # Number of insts commited each cycle +system.cpu3.commit.count 222278 # Number of instructions committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 77601 # Number of memory references committed -system.cpu3.commit.loads 54171 # Number of loads committed -system.cpu3.commit.membars 7839 # Number of memory barriers committed -system.cpu3.commit.branches 37226 # Number of branches committed +system.cpu3.commit.refs 89588 # Number of memory references committed +system.cpu3.commit.loads 61859 # Number of loads committed +system.cpu3.commit.membars 6925 # Number of memory barriers committed +system.cpu3.commit.branches 40615 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 136949 # Number of committed integer instructions. +system.cpu3.commit.int_insts 152323 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 838 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 841 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 370157 # The number of ROB reads -system.cpu3.rob.rob_writes 420591 # The number of ROB writes -system.cpu3.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2908 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.committedInsts 164273 # Number of Instructions Simulated -system.cpu3.committedInsts_total 164273 # Number of Instructions Simulated -system.cpu3.cpi 1.056242 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.056242 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.946753 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.946753 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 294835 # number of integer regfile reads -system.cpu3.int_regfile_writes 139001 # number of integer regfile writes +system.cpu3.rob.rob_reads 392905 # The number of ROB reads +system.cpu3.rob.rob_writes 465320 # The number of ROB writes +system.cpu3.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2770 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.committedInsts 183950 # Number of Instructions Simulated +system.cpu3.committedInsts_total 183950 # Number of Instructions Simulated +system.cpu3.cpi 0.944528 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.944528 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.058729 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.058729 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 330902 # number of integer regfile reads +system.cpu3.int_regfile_writes 155336 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 80433 # number of misc regfile reads +system.cpu3.misc_regfile_reads 92466 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 80.013522 # Cycle average of tags in use -system.cpu3.icache.total_refs 24405 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 80.005311 # Cycle average of tags in use +system.cpu3.icache.total_refs 22493 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 57.288732 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 52.800469 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 80.013522 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.156276 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits 24405 # number of ReadReq hits -system.cpu3.icache.demand_hits 24405 # number of demand (read+write) hits -system.cpu3.icache.overall_hits 24405 # number of overall hits +system.cpu3.icache.occ_blocks::0 80.005311 # Average occupied blocks per context +system.cpu3.icache.occ_percent::0 0.156260 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits 22493 # number of ReadReq hits +system.cpu3.icache.demand_hits 22493 # number of demand (read+write) hits +system.cpu3.icache.overall_hits 22493 # number of overall hits system.cpu3.icache.ReadReq_misses 466 # number of ReadReq misses system.cpu3.icache.demand_misses 466 # number of demand (read+write) misses system.cpu3.icache.overall_misses 466 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency 6656500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency 6656500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency 6656500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses 24871 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses 24871 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses 24871 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate 0.018737 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate 0.018737 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate 0.018737 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency 14284.334764 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency 14284.334764 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency 14284.334764 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency 6527000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency 6527000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency 6527000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses 22959 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses 22959 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses 22959 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate 0.020297 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate 0.020297 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate 0.020297 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency 14006.437768 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency 14006.437768 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency 14006.437768 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1503,60 +1503,60 @@ system.cpu3.icache.ReadReq_mshr_misses 426 # nu system.cpu3.icache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses 426 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.ReadReq_mshr_miss_latency 4959000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency 4959000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency 4959000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency 4833500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency 4833500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency 4833500 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.017128 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate 0.017128 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate 0.017128 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11640.845070 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11640.845070 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11640.845070 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_rate 0.018555 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate 0.018555 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate 0.018555 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11346.244131 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11346.244131 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11346.244131 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 15.701328 # Cycle average of tags in use -system.cpu3.dcache.total_refs 29297 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 13.455114 # Cycle average of tags in use +system.cpu3.dcache.total_refs 33581 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1010.241379 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1157.965517 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::0 23.466885 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -7.765557 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.045834 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::1 -0.015167 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 35023 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 23239 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu3.dcache.demand_hits 58262 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 58262 # number of overall hits -system.cpu3.dcache.ReadReq_misses 421 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses 121 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses 542 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses 542 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency 8723500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency 2943500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency 1375000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency 11667000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency 11667000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 35444 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 23360 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.occ_blocks::0 23.407144 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -9.952030 # Average occupied blocks per context +system.cpu3.dcache.occ_percent::0 0.045717 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::1 -0.019438 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits 38409 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits 27534 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits 65943 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits 65943 # number of overall hits +system.cpu3.dcache.ReadReq_misses 448 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses 125 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses 573 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses 573 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency 9358000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency 2911000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency 1350500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency 12269000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency 12269000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses 38857 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses 27659 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 58804 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 58804 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate 0.011878 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate 0.005180 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate 0.771429 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate 0.009217 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate 0.009217 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency 20720.902613 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency 24326.446281 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency 25462.962963 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency 21525.830258 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency 21525.830258 # average overall miss latency +system.cpu3.dcache.demand_accesses 66516 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses 66516 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate 0.011529 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate 0.004519 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate 0.800000 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate 0.008614 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate 0.008614 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency 20888.392857 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency 23288 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency 24116.071429 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency 21411.867365 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency 21411.867365 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1566,80 +1566,80 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets no_value system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_hits 256 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits 275 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses 267 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_hits 279 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits 296 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses 169 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses 108 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses 56 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 2157000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency 1669000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency 1213000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency 3826000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency 3826000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency 2218000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency 1624500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency 1182500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency 3842500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency 3842500 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004655 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.004366 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.771429 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate 0.004541 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate 0.004541 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13072.727273 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16362.745098 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22462.962963 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 14329.588015 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 14329.588015 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004349 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003905 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.800000 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate 0.004164 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate 0.004164 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13124.260355 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15041.666667 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 21116.071429 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 13871.841155 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 13871.841155 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 428.144160 # Cycle average of tags in use -system.l2c.total_refs 1448 # Total number of references to valid blocks. +system.l2c.tagsinuse 428.230348 # Cycle average of tags in use +system.l2c.total_refs 1446 # Total number of references to valid blocks. system.l2c.sampled_refs 527 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.747628 # Average number of references to valid blocks. +system.l2c.avg_refs 2.743833 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 347.119372 # Average occupied blocks per context -system.l2c.occ_blocks::1 10.560700 # Average occupied blocks per context -system.l2c.occ_blocks::2 63.080596 # Average occupied blocks per context -system.l2c.occ_blocks::3 2.422702 # Average occupied blocks per context -system.l2c.occ_blocks::4 4.960789 # Average occupied blocks per context +system.l2c.occ_blocks::0 347.173687 # Average occupied blocks per context +system.l2c.occ_blocks::1 11.269498 # Average occupied blocks per context +system.l2c.occ_blocks::2 63.254207 # Average occupied blocks per context +system.l2c.occ_blocks::3 1.567246 # Average occupied blocks per context +system.l2c.occ_blocks::4 4.965709 # Average occupied blocks per context system.l2c.occ_percent::0 0.005297 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.000161 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000963 # Average percentage of cache occupancy -system.l2c.occ_percent::3 0.000037 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.000172 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.000965 # Average percentage of cache occupancy +system.l2c.occ_percent::3 0.000024 # Average percentage of cache occupancy system.l2c.occ_percent::4 0.000076 # Average percentage of cache occupancy system.l2c.ReadReq_hits::0 233 # number of ReadReq hits -system.l2c.ReadReq_hits::1 425 # number of ReadReq hits -system.l2c.ReadReq_hits::2 360 # number of ReadReq hits -system.l2c.ReadReq_hits::3 433 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1451 # number of ReadReq hits +system.l2c.ReadReq_hits::1 424 # number of ReadReq hits +system.l2c.ReadReq_hits::2 356 # number of ReadReq hits +system.l2c.ReadReq_hits::3 436 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1449 # number of ReadReq hits system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits system.l2c.demand_hits::0 233 # number of demand (read+write) hits -system.l2c.demand_hits::1 425 # number of demand (read+write) hits -system.l2c.demand_hits::2 360 # number of demand (read+write) hits -system.l2c.demand_hits::3 433 # number of demand (read+write) hits -system.l2c.demand_hits::total 1451 # number of demand (read+write) hits +system.l2c.demand_hits::1 424 # number of demand (read+write) hits +system.l2c.demand_hits::2 356 # number of demand (read+write) hits +system.l2c.demand_hits::3 436 # number of demand (read+write) hits +system.l2c.demand_hits::total 1449 # number of demand (read+write) hits system.l2c.overall_hits::0 233 # number of overall hits -system.l2c.overall_hits::1 425 # number of overall hits -system.l2c.overall_hits::2 360 # number of overall hits -system.l2c.overall_hits::3 433 # number of overall hits -system.l2c.overall_hits::total 1451 # number of overall hits +system.l2c.overall_hits::1 424 # number of overall hits +system.l2c.overall_hits::2 356 # number of overall hits +system.l2c.overall_hits::3 436 # number of overall hits +system.l2c.overall_hits::total 1449 # number of overall hits system.l2c.ReadReq_misses::0 429 # number of ReadReq misses -system.l2c.ReadReq_misses::1 15 # number of ReadReq misses -system.l2c.ReadReq_misses::2 83 # number of ReadReq misses -system.l2c.ReadReq_misses::3 6 # number of ReadReq misses +system.l2c.ReadReq_misses::1 16 # number of ReadReq misses +system.l2c.ReadReq_misses::2 85 # number of ReadReq misses +system.l2c.ReadReq_misses::3 3 # number of ReadReq misses system.l2c.ReadReq_misses::total 533 # number of ReadReq misses system.l2c.UpgradeReq_misses::0 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 24 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 22 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses @@ -1647,31 +1647,31 @@ system.l2c.ReadExReq_misses::2 13 # nu system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses system.l2c.demand_misses::0 523 # number of demand (read+write) misses -system.l2c.demand_misses::1 27 # number of demand (read+write) misses -system.l2c.demand_misses::2 96 # number of demand (read+write) misses -system.l2c.demand_misses::3 18 # number of demand (read+write) misses +system.l2c.demand_misses::1 28 # number of demand (read+write) misses +system.l2c.demand_misses::2 98 # number of demand (read+write) misses +system.l2c.demand_misses::3 15 # number of demand (read+write) misses system.l2c.demand_misses::total 664 # number of demand (read+write) misses system.l2c.overall_misses::0 523 # number of overall misses -system.l2c.overall_misses::1 27 # number of overall misses -system.l2c.overall_misses::2 96 # number of overall misses -system.l2c.overall_misses::3 18 # number of overall misses +system.l2c.overall_misses::1 28 # number of overall misses +system.l2c.overall_misses::2 98 # number of overall misses +system.l2c.overall_misses::3 15 # number of overall misses system.l2c.overall_misses::total 664 # number of overall misses -system.l2c.ReadReq_miss_latency 27698500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency 27701000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 157500 # number of UpgradeReq miss cycles system.l2c.ReadExReq_miss_latency 6878000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 34576500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 34576500 # number of overall miss cycles +system.l2c.demand_miss_latency 34579000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 34579000 # number of overall miss cycles system.l2c.ReadReq_accesses::0 662 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::1 440 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 443 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 441 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::3 439 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1984 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::0 24 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 22 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 22 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 22 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) @@ -1680,19 +1680,19 @@ system.l2c.ReadExReq_accesses::3 12 # nu system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::0 756 # number of demand (read+write) accesses system.l2c.demand_accesses::1 452 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 456 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 454 # number of demand (read+write) accesses system.l2c.demand_accesses::3 451 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2115 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2113 # number of demand (read+write) accesses system.l2c.overall_accesses::0 756 # number of overall (read+write) accesses system.l2c.overall_accesses::1 452 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 456 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 454 # number of overall (read+write) accesses system.l2c.overall_accesses::3 451 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2115 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2113 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::0 0.648036 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.034091 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.187359 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.013667 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.883154 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.036364 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.192744 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.006834 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.883977 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::0 0.875000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses @@ -1704,40 +1704,40 @@ system.l2c.ReadExReq_miss_rate::2 1 # mi system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::0 0.691799 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.059735 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.210526 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.039911 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 1.001971 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.061947 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.215859 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.033259 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 1.002864 # miss rate for demand accesses system.l2c.overall_miss_rate::0 0.691799 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.059735 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.210526 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.039911 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 1.001971 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 64565.268065 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 1846566.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 333716.867470 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 4616416.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 6861265.468868 # average ReadReq miss latency +system.l2c.overall_miss_rate::1 0.061947 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.215859 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.033259 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 1.002864 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 64571.095571 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1731312.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 325894.117647 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 9233666.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 11355444.379885 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::0 7500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 6847.826087 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 8289.473684 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 6562.500000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29199.799771 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7159.090909 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 7159.090909 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 7159.090909 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28977.272727 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::0 73170.212766 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 573166.666667 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 529076.923077 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::3 573166.666667 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 1748580.469176 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 66111.854685 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1280611.111111 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 360171.875000 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 1920916.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3627811.507462 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 66111.854685 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1280611.111111 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 360171.875000 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 1920916.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3627811.507462 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 66116.634799 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1234964.285714 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 352846.938776 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 2305266.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3959194.525956 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 66116.634799 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1234964.285714 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 352846.938776 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 2305266.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3959194.525956 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1764,14 +1764,14 @@ system.l2c.overall_mshr_miss_latency 26272500 # nu system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::0 0.793051 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 1.193182 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 1.185102 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 1.190476 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::3 1.195900 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 4.367235 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 4.372609 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::0 3.625000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 3.782609 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 4.578947 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 3.625000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 15.611556 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 3.954545 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 3.954545 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 3.954545 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 15.488636 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses @@ -1779,14 +1779,14 @@ system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # ms system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::0 0.867725 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 1.451327 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.438596 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.444934 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::3 1.454545 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 5.212194 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 5.218532 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::0 0.867725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 1.451327 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.438596 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.444934 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::3 1.454545 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 5.212194 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 5.218532 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency 39987.619048 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924 # average ReadExReq mshr miss latency |