diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-28 19:09:17 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-28 19:09:17 -0600 |
| commit | f19b3f30b4fdbf464334f6a8c5b86210d675c9ec (patch) | |
| tree | a39c3a31170866533531a00ecbe5624eb09fb786 /tests/quick | |
| parent | 5c2fc35e029d8cd8e69e983e1baef6b86e47d64d (diff) | |
| download | gem5-f19b3f30b4fdbf464334f6a8c5b86210d675c9ec.tar.xz | |
X86 Regressions: Update stats due to introduction of TSO
Diffstat (limited to 'tests/quick')
| -rw-r--r-- | tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini | 3 | ||||
| -rwxr-xr-x | tests/quick/00.hello/ref/x86/linux/o3-timing/simout | 11 | ||||
| -rw-r--r-- | tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt | 621 |
3 files changed, 318 insertions, 317 deletions
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini index 8582c91b4..8f8ece24e 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini @@ -80,6 +80,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=true numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -502,7 +503,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 4c371922e..b49f2b572 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -1,12 +1,13 @@ +Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 04:24:37 -gem5 executing on zizzer +gem5 compiled Jan 28 2012 12:11:40 +gem5 started Jan 28 2012 12:11:57 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Hello world! -Exiting @ tick 11087000 because target called exit() +Exiting @ tick 11989500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index e2df7b059..8477728c8 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11087000 # Number of ticks simulated -final_tick 11087000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11989500 # Number of ticks simulated +final_tick 11989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31087 # Simulator instruction rate (inst/s) -host_tick_rate 35135175 # Simulator tick rate (ticks/s) -host_mem_usage 212404 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 1330 # Simulator instruction rate (inst/s) +host_tick_rate 1625690 # Simulator tick rate (ticks/s) +host_mem_usage 239860 # Number of bytes of host memory used +host_seconds 7.38 # Real time elapsed on the host sim_insts 9809 # Number of instructions simulated system.physmem.bytes_read 28288 # Number of bytes read from this memory system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory @@ -15,247 +15,247 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 442 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2551456661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1708667809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2551456661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2359397806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1580049210 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2359397806 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 22175 # number of cpu cycles simulated +system.cpu.numCycles 23980 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3056 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3056 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2731 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 995 # Number of BTB hits +system.cpu.BPredUnit.lookups 3019 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3019 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2695 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 978 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 5895 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13997 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3056 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 995 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3968 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2221 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1500 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7194 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13831 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3019 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 978 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2194 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3367 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1891 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13088 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.930776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.218766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1866 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 16182 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.543567 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.980612 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9227 70.50% 70.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 167 1.28% 71.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 175 1.34% 73.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 239 1.83% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 232 1.77% 76.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 193 1.47% 78.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 279 2.13% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 139 1.06% 81.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2437 18.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12367 76.42% 76.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 166 1.03% 77.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 172 1.06% 78.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 238 1.47% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 224 1.38% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 191 1.18% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 276 1.71% 84.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 137 0.85% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2411 14.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13088 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137813 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.631206 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6247 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1453 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3565 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1712 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24090 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1712 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6535 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 523 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 524 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3365 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 429 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22712 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 16182 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.125897 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.576772 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7550 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3508 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 122 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1687 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 23802 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1687 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7843 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2077 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3329 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 693 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22457 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 272 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21246 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 47645 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 47629 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 553 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21026 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 47090 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 47074 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11878 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 11658 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1613 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2238 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1782 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 1820 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2219 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1751 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20539 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 16958 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12992 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 16792 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10001 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12754 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.295691 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.003315 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 16182 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.037696 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.845376 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8001 61.13% 61.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1108 8.47% 69.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1006 7.69% 77.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 733 5.60% 82.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 670 5.12% 88.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 725 5.54% 93.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 615 4.70% 98.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 196 1.50% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 34 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10903 67.38% 67.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1372 8.48% 75.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1062 6.56% 82.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 680 4.20% 86.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 659 4.07% 90.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 684 4.23% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 588 3.63% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 200 1.24% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 34 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16182 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 94 66.67% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 17.02% 83.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 16.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 86 64.66% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24 18.05% 82.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 17.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13641 80.44% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1843 10.87% 91.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1470 8.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13517 80.50% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1828 10.89% 91.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1443 8.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16958 # Type of FU issued -system.cpu.iq.rate 0.764735 # Inst issue rate -system.cpu.iq.fu_busy_cnt 141 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008315 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 47200 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30804 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15755 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 16792 # Type of FU issued +system.cpu.iq.rate 0.700250 # Inst issue rate +system.cpu.iq.fu_busy_cnt 133 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007920 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 49947 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30352 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15608 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17091 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 16917 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 142 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 848 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 817 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1712 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20576 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 23 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2238 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1782 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1687 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1417 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20343 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 26 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2219 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1751 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 523 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 588 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16100 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1742 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 858 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 525 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 15942 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 850 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3105 # number of memory reference insts executed -system.cpu.iew.exec_branches 1601 # Number of branches executed -system.cpu.iew.exec_stores 1363 # Number of stores executed -system.cpu.iew.exec_rate 0.726043 # Inst execution rate -system.cpu.iew.wb_sent 15918 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15759 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10538 # num instructions producing a value -system.cpu.iew.wb_consumers 15699 # num instructions consuming a value +system.cpu.iew.exec_refs 3065 # number of memory reference insts executed +system.cpu.iew.exec_branches 1589 # Number of branches executed +system.cpu.iew.exec_stores 1340 # Number of stores executed +system.cpu.iew.exec_rate 0.664804 # Inst execution rate +system.cpu.iew.wb_sent 15766 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15612 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10251 # num instructions producing a value +system.cpu.iew.wb_consumers 15131 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.710665 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.671253 # average fanout of values written-back +system.cpu.iew.wb_rate 0.651043 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.677483 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 10766 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10533 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 497 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11376 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.862254 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.686850 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 495 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.676716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510487 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7944 69.83% 69.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1088 9.56% 79.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 574 5.05% 84.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 883 7.76% 92.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 343 3.02% 95.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 152 1.34% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 139 1.22% 97.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 66 0.58% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 187 1.64% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10831 74.72% 74.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1349 9.31% 84.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 680 4.69% 88.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 780 5.38% 94.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 337 2.32% 96.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 129 0.89% 97.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 140 0.97% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 65 0.45% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 184 1.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11376 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14495 # Number of insts commited each cycle system.cpu.commit.count 9809 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1990 # Number of memory references committed @@ -265,48 +265,48 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 187 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 31764 # The number of ROB reads -system.cpu.rob.rob_writes 42896 # The number of ROB writes -system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9087 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 34653 # The number of ROB reads +system.cpu.rob.rob_writes 42403 # The number of ROB writes +system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7798 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.260679 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.260679 # CPI: Total CPI of All Threads -system.cpu.ipc 0.442345 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.442345 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23665 # number of integer regfile reads -system.cpu.int_regfile_writes 14645 # number of integer regfile writes +system.cpu.cpi 2.444694 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.444694 # CPI: Total CPI of All Threads +system.cpu.ipc 0.409049 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.409049 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23430 # number of integer regfile reads +system.cpu.int_regfile_writes 14518 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7211 # number of misc regfile reads +system.cpu.misc_regfile_reads 7136 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.144237 # Cycle average of tags in use -system.cpu.icache.total_refs 1527 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 140.870525 # Cycle average of tags in use +system.cpu.icache.total_refs 1498 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.124161 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.026846 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 145.144237 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.070871 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1527 # number of ReadReq hits -system.cpu.icache.demand_hits 1527 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1527 # number of overall hits -system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses -system.cpu.icache.demand_misses 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 13314500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 13314500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 13314500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1891 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1891 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1891 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.192491 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.192491 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.192491 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36578.296703 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36578.296703 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36578.296703 # average overall miss latency +system.cpu.icache.occ_blocks::0 140.870525 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.068784 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1498 # number of ReadReq hits +system.cpu.icache.demand_hits 1498 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1498 # number of overall hits +system.cpu.icache.ReadReq_misses 368 # number of ReadReq misses +system.cpu.icache.demand_misses 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 13394000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 13394000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 13394000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1866 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1866 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.197213 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.197213 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.197213 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36396.739130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36396.739130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36396.739130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,59 +316,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 298 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 298 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 298 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10466500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10466500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10466500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10471500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.157589 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.157589 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.157589 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35122.483221 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35122.483221 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35122.483221 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.159700 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.159700 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.159700 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35139.261745 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35139.261745 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35139.261745 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.499149 # Cycle average of tags in use -system.cpu.dcache.total_refs 2112 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.526549 # Cycle average of tags in use +system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 14.565517 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 15.689655 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 85.499149 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020874 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1494 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 618 # number of WriteReq hits -system.cpu.dcache.demand_hits 2112 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2112 # number of overall hits -system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 316 # number of WriteReq misses -system.cpu.dcache.demand_misses 429 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 429 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3938500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10708500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 14647000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 14647000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1607 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 83.526549 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.020392 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1417 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 858 # number of WriteReq hits +system.cpu.dcache.demand_hits 2275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2275 # number of overall hits +system.cpu.dcache.ReadReq_misses 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 76 # number of WriteReq misses +system.cpu.dcache.demand_misses 187 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 187 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3859500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 2916500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 6776000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 6776000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2541 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2541 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.070317 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.338330 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.168831 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.168831 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 34853.982301 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33887.658228 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34142.191142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34142.191142 # average overall miss latency +system.cpu.dcache.demand_accesses 2462 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2462 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.072644 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.075955 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.075955 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 34770.270270 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 38375 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 36235.294118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 36235.294118 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -378,63 +378,62 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 239 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 69 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 41 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 70 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 76 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2422500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2761000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5183500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5183500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2463000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2688500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5151500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5151500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.042937 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.057458 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.057458 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35108.695652 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35857.142857 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.045812 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.059301 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.059301 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35185.714286 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35375 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35284.246575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35284.246575 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.614114 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 173.809724 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005495 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 365 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005479 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 178.614114 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005451 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 173.809724 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005304 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 365 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses 366 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 76 # number of ReadExReq misses system.cpu.l2cache.demand_misses 442 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12494500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2654000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 15148500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 15148500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 367 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency 12541000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2603000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 15144000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 15144000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 368 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994550 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate 0.994565 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.995495 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.995495 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34231.506849 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34467.532468 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34272.624434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34272.624434 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34265.027322 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34250 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34262.443439 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34262.443439 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,24 +445,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 365 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 76 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 442 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11330000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2409500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13739500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13739500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11369000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2368500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13737500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994550 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994565 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.995495 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.995495 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.095890 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31292.207792 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31084.841629 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31084.841629 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31062.841530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.473684 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |