diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
| commit | 08f7a8bc005507117ffda41f283adecf7e4d24f2 (patch) | |
| tree | d3588f01b572538601360998b89e23607549934c /tests/quick | |
| parent | 93a8423dea8f8194d83df85a5b3043f9beaf0a1e (diff) | |
| download | gem5-08f7a8bc005507117ffda41f283adecf7e4d24f2.tar.xz | |
stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
Diffstat (limited to 'tests/quick')
5 files changed, 2420 insertions, 2421 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 3e3128027..91c2fb18d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.954691 # Nu sim_ticks 1954691371500 # Number of ticks simulated final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 798728 # Simulator instruction rate (inst/s) -host_op_rate 798728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26318676085 # Simulator tick rate (ticks/s) -host_mem_usage 332420 # Number of bytes of host memory used -host_seconds 74.27 # Real time elapsed on the host +host_inst_rate 888978 # Simulator instruction rate (inst/s) +host_op_rate 888978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29292473013 # Simulator tick rate (ticks/s) +host_mem_usage 331536 # Number of bytes of host memory used +host_seconds 66.73 # Real time elapsed on the host sim_insts 59321614 # Number of instructions simulated sim_ops 59321614 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory @@ -50,13 +50,13 @@ system.physmem.bw_total::cpu1.data 199364 # To system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 447836 # Total number of read requests seen system.physmem.writeReqs 119953 # Total number of write requests seen -system.physmem.cpureqs 572898 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 570963 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 28661504 # Total number of bytes read from memory system.physmem.bytesWritten 7676992 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 3162 # Reqs where no action is needed system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis @@ -90,7 +90,7 @@ system.physmem.perBankWrReqs::13 7492 # Tr system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 12 # Number of times wr buffer was full causing retry system.physmem.totGap 1954684300500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -106,26 +106,26 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 119953 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4805 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1540 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1510 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 781 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see @@ -161,23 +161,23 @@ system.physmem.wrQLenPdf::19 5215 # Wh system.physmem.wrQLenPdf::20 5215 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5215 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.totQLat 4783798250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13397999500 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::23 1508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see +system.physmem.totQLat 4783941000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13398087250 # Sum of mem lat for all requests system.physmem.totBusLat 2238835000 # Total cycles spent in databus access -system.physmem.totBankLat 6375366250 # Total cycles spent in bank access -system.physmem.avgQLat 10683.68 # Average queueing delay per request -system.physmem.avgBankLat 14238.13 # Average bank access latency per request +system.physmem.totBankLat 6375311250 # Total cycles spent in bank access +system.physmem.avgQLat 10684.00 # Average queueing delay per request +system.physmem.avgBankLat 14238.01 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29921.81 # Average memory access latency +system.physmem.avgMemAccLat 29922.01 # Average memory access latency system.physmem.avgRdBW 14.66 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.66 # Average consumed read bandwidth in MB/s @@ -192,14 +192,14 @@ system.physmem.readRowHitRate 93.77 # Ro system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes system.physmem.avgGap 3442624.46 # Average gap between requests system.l2c.replacements 340771 # number of replacements -system.l2c.tagsinuse 65303.436480 # Cycle average of tags in use -system.l2c.total_refs 2493415 # Total number of references to valid blocks. +system.l2c.tagsinuse 65303.436431 # Cycle average of tags in use +system.l2c.total_refs 2493405 # Total number of references to valid blocks. system.l2c.sampled_refs 405943 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.142279 # Average number of references to valid blocks. +system.l2c.avg_refs 6.142254 # Average number of references to valid blocks. system.l2c.warmup_cycle 6937754751 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55559.705668 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4839.489270 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4775.815267 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 55559.705591 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4839.489284 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4775.815281 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 117.980929 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 10.445347 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.847774 # Average percentage of cache occupancy @@ -209,39 +209,39 @@ system.l2c.occ_percent::cpu1.inst 0.001800 # Av system.l2c.occ_percent::cpu1.data 0.000159 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.996451 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 902966 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 773506 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 773500 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 86370 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 33767 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1796609 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820435 # number of Writeback hits -system.l2c.Writeback_hits::total 820435 # number of Writeback hits +system.l2c.ReadReq_hits::total 1796603 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 820431 # number of Writeback hits +system.l2c.Writeback_hits::total 820431 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 171833 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 171831 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 12858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 184691 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 184689 # number of ReadExReq hits system.l2c.demand_hits::cpu0.inst 902966 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 945339 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 945331 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 86370 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 46625 # number of demand (read+write) hits -system.l2c.demand_hits::total 1981300 # number of demand (read+write) hits +system.l2c.demand_hits::total 1981292 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 902966 # number of overall hits -system.l2c.overall_hits::cpu0.data 945339 # number of overall hits +system.l2c.overall_hits::cpu0.data 945331 # number of overall hits system.l2c.overall_hits::cpu1.inst 86370 # number of overall hits system.l2c.overall_hits::cpu1.data 46625 # number of overall hits -system.l2c.overall_hits::total 1981300 # number of overall hits +system.l2c.overall_hits::total 1981292 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 12959 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 271596 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 545 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 189 # number of ReadReq misses system.l2c.ReadReq_misses::total 285289 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2443 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2926 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 27 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 100 # number of SCUpgradeReq misses @@ -258,104 +258,104 @@ system.l2c.overall_misses::cpu0.data 387219 # nu system.l2c.overall_misses::cpu1.inst 545 # number of overall misses system.l2c.overall_misses::cpu1.data 6107 # number of overall misses system.l2c.overall_misses::total 406830 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 800348000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11682390000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 800540000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11682471000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 34833000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 14789000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 12532360000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1038000 # number of UpgradeReq miss cycles +system.l2c.ReadReq_miss_latency::total 12532633000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1038500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 229000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1267000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1267500 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 115000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 137500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5536684000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5536696500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 338210000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5874894000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 800348000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 17219074000 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::total 5874906500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 800540000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 17219167500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 34833000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 352999000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 18407254000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 800348000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 17219074000 # number of overall miss cycles +system.l2c.demand_miss_latency::total 18407539500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 800540000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 17219167500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 34833000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 352999000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 18407254000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 18407539500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 915925 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1045102 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1045096 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 86915 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 33956 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2081898 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 820435 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 820435 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2605 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2081892 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 820431 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 820431 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2606 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3144 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3145 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 48 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 92 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 140 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 287456 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 287454 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 18776 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306232 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 306230 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 915925 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1332558 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1332550 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 86915 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 52732 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2388130 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2388122 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 32932.289205 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49190.963886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32169.431745 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 32932.289205 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -492,7 +492,7 @@ system.iocache.tagsinuse 0.572561 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1746701282000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1746701284000 # Cycle when the warmup percentage was hit. system.iocache.occ_blocks::tsunami.ide 0.572561 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.035785 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.035785 # Average percentage of cache occupancy @@ -506,12 +506,12 @@ system.iocache.overall_misses::tsunami.ide 41726 # system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10674900806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10674900806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10695943804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10695943804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10695943804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10695943804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10675580676 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10675580676 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10696623674 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10696623674 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10696623674 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10696623674 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -530,17 +530,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256904.620861 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256904.620861 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 256337.626516 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 256337.626516 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 286340 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256920.982769 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256920.982769 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 256353.920194 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 256353.920194 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 256353.920194 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 256353.920194 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 286338 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27291 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27305 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.492104 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.486651 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -556,12 +556,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41726 system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8513588925 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8513588925 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8525583174 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8525583174 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8525583174 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8525583174 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -572,12 +572,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204889.991456 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204889.991456 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204323.040167 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204323.040167 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204323.040167 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204323.040167 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -641,8 +641,8 @@ system.cpu0.num_fp_register_writes 146520 # nu system.cpu0.num_mem_refs 14722187 # number of memory refs system.cpu0.num_load_insts 8662865 # Number of load instructions system.cpu0.num_store_insts 6059322 # Number of store instructions -system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles -system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles +system.cpu0.num_idle_cycles 3679287255.686766 # Number of idle cycles +system.cpu0.num_busy_cycles 228924280.313234 # Number of busy cycles system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -660,11 +660,11 @@ system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # nu system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1898301427500 97.14% 97.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 762226000 0.04% 97.19% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 54943825500 2.81% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -730,8 +730,8 @@ system.cpu0.kern.mode_switch_good::kernel 0.175657 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3454635500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1950347158000 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3454773000 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3897 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -766,12 +766,12 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.icache.replacements 915312 # number of replacements -system.cpu0.icache.tagsinuse 509.170565 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 509.170564 # Cycle average of tags in use system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.170565 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.170564 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits @@ -786,12 +786,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 915946 # system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses system.cpu0.icache.overall_misses::total 915946 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645153500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12645153500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12645153500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12645153500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12645153500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12645153500 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645308000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12645308000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12645308000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12645308000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12645308000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12645308000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses @@ -804,12 +804,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940 system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.566595 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.566595 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13805.566595 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13805.566595 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.735273 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.735273 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.735273 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13805.735273 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.735273 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13805.735273 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -824,70 +824,70 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 915946 system.cpu0.icache.demand_mshr_misses::total 915946 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 915946 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 915946 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813261500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813261500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813261500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10813261500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813261500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10813261500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813416000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813416000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813416000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10813416000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813416000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10813416000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.566595 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.735273 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.735273 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.735273 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1337909 # number of replacements -system.cpu0.dcache.tagsinuse 506.537579 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13346950 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338324 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.972884 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337901 # number of replacements +system.cpu0.dcache.tagsinuse 506.537580 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13346958 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1338316 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.972950 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.537579 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 506.537580 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.989331 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.989331 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7419116 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7419116 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5560491 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5560491 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 7419122 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7419122 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5560492 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5560492 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176356 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 176356 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191669 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 191669 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12979607 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12979607 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12979607 # number of overall hits -system.cpu0.dcache.overall_hits::total 12979607 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1035921 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1035921 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291041 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291041 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12979614 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12979614 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12979614 # number of overall hits +system.cpu0.dcache.overall_hits::total 12979614 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1035915 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1035915 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291040 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 291040 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16710 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 16710 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 430 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326962 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326962 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326962 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326962 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391252000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 22391252000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190685500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8190685500 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1326955 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326955 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326955 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326955 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391266500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 22391266500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190691500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8190691500 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219165000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 219165000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2509000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 2509000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 30581937500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 30581937500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 30581937500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 30581937500 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 30581958000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 30581958000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 30581958000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 30581958000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 8455037 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8455037 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851532 # number of WriteReq accesses(hits+misses) @@ -900,30 +900,30 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14306569 system.cpu0.dcache.demand_accesses::total 14306569 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14306569 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14306569 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122521 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122521 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049738 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049738 # miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122520 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122520 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049737 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049737 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086551 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092752 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092752 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092752 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092752 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.825841 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.825841 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.720441 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.720441 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092751 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092751 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092751 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092751 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.965031 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.965031 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.837754 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.837754 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.718238 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23046.718238 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.718238 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23046.718238 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -932,62 +932,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks -system.cpu0.dcache.writebacks::total 789805 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035921 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1035921 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291041 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 291041 # number of WriteReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 789801 # number of writebacks +system.cpu0.dcache.writebacks::total 789801 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035915 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1035915 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291040 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291040 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326962 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1326962 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326962 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1326962 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319410000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319410000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608603500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608603500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326955 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326955 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326955 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326955 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319436500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319436500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608611500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608611500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928013500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 27928013500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928013500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 27928013500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465455500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465455500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092162000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092162000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557617500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928048000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 27928048000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928048000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 27928048000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465347500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465347500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092159000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092159000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557506500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557506500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122520 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122520 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049737 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049737 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092751 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092751 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092751 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092751 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.965031 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.965031 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.837754 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.837754 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.718238 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.718238 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.718238 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.718238 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1045,8 +1045,8 @@ system.cpu1.num_fp_register_writes 21862 # nu system.cpu1.num_mem_refs 1706720 # number of memory refs system.cpu1.num_load_insts 1053093 # Number of load instructions system.cpu1.num_store_insts 653627 # Number of store instructions -system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles +system.cpu1.num_idle_cycles 3890042730.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 19340012.001990 # Number of busy cycles system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -1062,10 +1062,10 @@ system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # nu system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1917858601000 98.12% 98.12% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 36066950000 1.85% 100.00% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1138,12 +1138,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 86916 # system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses system.cpu1.icache.overall_misses::total 86916 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175951500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1175951500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1175951500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1175951500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1175951500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1175951500 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175956500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1175956500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1175956500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1175956500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1175956500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1175956500 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses @@ -1156,12 +1156,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.747112 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.747112 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13529.747112 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13529.747112 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.804639 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.804639 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13529.804639 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13529.804639 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1176,70 +1176,70 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916 system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002119500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002119500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002119500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1002119500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002119500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1002119500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002124500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002124500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002124500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1002124500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002124500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1002124500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.747112 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.804639 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.804639 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.804639 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 52807 # number of replacements system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1641018 # Total number of references to valid blocks. +system.cpu1.dcache.total_refs 1641017 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 30.777340 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1001238 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1001238 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 1001237 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1001237 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1617458 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1617458 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1617458 # number of overall hits -system.cpu1.dcache.overall_hits::total 1617458 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 37008 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 37008 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 1617457 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1617457 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1617457 # number of overall hits +system.cpu1.dcache.overall_hits::total 1617457 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 37009 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 37009 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 20401 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 956 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 500 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 500 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 57409 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 57409 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 57409 # number of overall misses -system.cpu1.dcache.overall_misses::total 57409 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463706500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 463706500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 540901000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 540901000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10601500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 10601500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.demand_misses::cpu1.data 57410 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 57410 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 57410 # number of overall misses +system.cpu1.dcache.overall_misses::total 57410 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463717500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 463717500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 540903500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 540903500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10599500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 10599500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3694000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 3694000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1004607500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1004607500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1004607500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1004607500 # number of overall miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1004621000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1004621000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1004621000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1004621000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038246 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1038246 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 636621 # number of WriteReq accesses(hits+misses) @@ -1252,8 +1252,8 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1674867 system.cpu1.dcache.demand_accesses::total 1674867 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 1674867 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1674867 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035645 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035645 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035646 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035646 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032046 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.032046 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081279 # miss rate for LoadLockedReq accesses @@ -1264,18 +1264,18 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277 system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.898941 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.455223 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.455223 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11089.435146 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.857602 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.857602 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.577766 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.577766 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11087.343096 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11087.343096 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.059397 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17499.059397 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.059397 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17499.059397 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1286,38 +1286,38 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks system.cpu1.dcache.writebacks::total 30630 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37008 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37009 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 37009 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 57409 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 57409 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 57409 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 57409 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389690500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389690500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500099000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500099000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8689500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57410 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57410 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57410 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57410 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389699500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389699500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500101500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500101500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8687500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8687500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889789500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 889789500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889789500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 889789500 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889801000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 889801000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889801000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 889801000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035645 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035646 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035646 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses @@ -1328,18 +1328,18 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.898941 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.857602 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.857602 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.577766 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.577766 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9087.343096 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9087.343096 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.059397 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.059397 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.059397 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.059397 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 10a028441..9db64d392 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.913475 # Nu sim_ticks 1913474690000 # Number of ticks simulated final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1324010 # Simulator instruction rate (inst/s) -host_op_rate 1324010 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45134311907 # Simulator tick rate (ticks/s) -host_mem_usage 328328 # Number of bytes of host memory used -host_seconds 42.40 # Real time elapsed on the host +host_inst_rate 960952 # Simulator instruction rate (inst/s) +host_op_rate 960952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32757999490 # Simulator tick rate (ticks/s) +host_mem_usage 329472 # Number of bytes of host memory used +host_seconds 58.41 # Real time elapsed on the host sim_insts 56131527 # Number of instructions simulated sim_ops 56131527 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory @@ -40,7 +40,7 @@ system.physmem.bw_total::tsunami.ide 1386010 # To system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 443158 # Total number of read requests seen system.physmem.writeReqs 115703 # Total number of write requests seen -system.physmem.cpureqs 560726 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 559001 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 28362112 # Total number of bytes read from memory system.physmem.bytesWritten 7404992 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize() @@ -80,7 +80,7 @@ system.physmem.perBankWrReqs::13 7186 # Tr system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry system.physmem.totGap 1913462790000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -96,26 +96,26 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 115703 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 402452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 402453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1367 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -132,11 +132,11 @@ system.physmem.wrQLenPdf::0 3531 # Wh system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see @@ -155,19 +155,19 @@ system.physmem.wrQLenPdf::23 1500 # Wh system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see -system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::27 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.totQLat 4710239250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13222743000 # Sum of mem lat for all requests system.physmem.totBusLat 2215485000 # Total cycles spent in databus access -system.physmem.totBankLat 6297005000 # Total cycles spent in bank access -system.physmem.avgQLat 10649.88 # Average queueing delay per request -system.physmem.avgBankLat 14211.35 # Average bank access latency per request +system.physmem.totBankLat 6297018750 # Total cycles spent in bank access +system.physmem.avgQLat 10630.27 # Average queueing delay per request +system.physmem.avgBankLat 14211.38 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29861.22 # Average memory access latency +system.physmem.avgMemAccLat 29841.64 # Average memory access latency system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s @@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10661973806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10661973806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10682901804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10682901804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10682901804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10682901804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10653271428 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10653271428 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10674199426 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10674199426 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10674199426 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10674199426 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -224,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256593.516702 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256593.516702 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 256031.199617 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 256031.199617 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285723 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256384.083269 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256384.083269 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255822.634536 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255822.634536 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285520 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27146 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27149 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.525418 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.516778 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8499962078 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8499962078 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8511893327 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8511893327 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8511893327 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8511893327 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8491261949 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8491261949 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8503193198 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8503193198 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8503193198 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8503193198 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204562.044619 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204562.044619 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204352.665311 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204352.665311 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -335,8 +335,8 @@ system.cpu.num_fp_register_writes 166418 # nu system.cpu.num_mem_refs 15461819 # number of memory refs system.cpu.num_load_insts 9093811 # Number of load instructions system.cpu.num_store_insts 6368008 # Number of store instructions -system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles -system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles +system.cpu.num_idle_cycles 3593002703.998122 # Number of idle cycles +system.cpu.num_busy_cycles 233946676.001878 # Number of busy cycles system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles system.cpu.idle_fraction 0.938869 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -352,10 +352,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1858610730000 97.13% 97.13% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54034649000 2.82% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -420,9 +420,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323898 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 45394332000 2.37% 2.37% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5131699000 0.27% 2.64% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862947923000 97.36% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -476,12 +476,12 @@ system.cpu.icache.demand_misses::cpu.inst 928628 # n system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 928628 # number of overall misses system.cpu.icache.overall_misses::total 928628 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770278000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12770278000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12770278000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12770278000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12770278000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12770278000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770432000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12770432000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12770432000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12770432000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12770432000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12770432000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 56143366 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56143366 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 56143366 # number of demand (read+write) accesses @@ -494,12 +494,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.769277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13751.769277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13751.769277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13751.769277 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.935113 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13751.935113 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13751.935113 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13751.935113 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,53 +514,53 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 928628 system.cpu.icache.demand_mshr_misses::total 928628 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 928628 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 928628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913022000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10913022000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913022000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10913022000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913022000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10913022000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913176000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10913176000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913176000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10913176000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913176000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10913176000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.769277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.769277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.935113 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.935113 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.935113 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.935113 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 336244 # number of replacements -system.cpu.l2cache.tagsinuse 65321.744295 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2445552 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 65321.744334 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2445560 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 401406 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.092465 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 6.092485 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 5250002751 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55750.890928 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4786.700552 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4784.152815 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 55750.890947 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4786.700562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4784.152824 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.850691 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.073039 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.073000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.996731 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 915318 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 813981 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1729299 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 834498 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834498 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 813988 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1729306 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 834499 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 834499 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187514 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187514 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 915318 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001495 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1916813 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1001502 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1916820 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 915318 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1001495 # number of overall hits -system.cpu.l2cache.overall_hits::total 1916813 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1001502 # number of overall hits +system.cpu.l2cache.overall_hits::total 1916820 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 271963 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 285253 # number of ReadReq misses @@ -574,60 +574,60 @@ system.cpu.l2cache.demand_misses::total 402109 # nu system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 388819 # number of overall misses system.cpu.l2cache.overall_misses::total 402109 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831194000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11699138000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12530332000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831348000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11699456000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12530804000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 189500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 189500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5596958000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5596958000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 831194000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17296096000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18127290000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 831194000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17296096000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18127290000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5596921000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5596921000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 831348000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17296377000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18127725000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 831348000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17296377000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18127725000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 928608 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1085944 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2014552 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 834498 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 834498 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1085951 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2014559 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 834499 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 834499 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304370 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304370 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 928608 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390314 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2318922 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390321 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2318929 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 928608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390314 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2318922 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390321 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2318929 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014312 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250439 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250438 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.141596 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383927 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.383927 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014312 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279663 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279661 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.173403 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014312 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279663 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279661 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.173403 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62542.814146 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43017.388395 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 43927.082274 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62554.401806 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43018.557671 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 43928.736946 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47896.197029 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47896.197029 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 45080.537864 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 45080.537864 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47895.880400 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47895.880400 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62554.401806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44484.392481 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 45081.619660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62554.401806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44484.392481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 45081.619660 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -651,19 +651,19 @@ system.cpu.l2cache.demand_mshr_misses::total 402109 system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 388819 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 402109 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666266030 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8360156960 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9026422990 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666421030 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8360475460 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9026896490 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4160193080 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4160193080 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666266030 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12520350040 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13186616070 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666266030 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12520350040 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13186616070 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4160156080 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4160156080 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666421030 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12520631540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13187052570 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666421030 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12520631540 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13187052570 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895853000 # number of WriteReq MSHR uncacheable cycles @@ -671,31 +671,31 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895853000 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229999000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229999000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250438 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141596 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383927 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383927 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279661 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.173403 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279661 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.173403 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50132.884123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30740.052728 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31643.569007 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50144.547028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30741.223843 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31645.228937 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35601.022455 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35601.022455 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35600.705826 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35600.705826 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -703,47 +703,47 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1389801 # number of replacements +system.cpu.dcache.replacements 1389808 # number of replacements system.cpu.dcache.tagsinuse 511.980871 # Cycle average of tags in use -system.cpu.dcache.total_refs 14037928 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1390313 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.096955 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14037921 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1390320 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.096899 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807394 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807394 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7807387 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807387 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848285 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848285 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199228 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655679 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655679 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655679 # number of overall hits -system.cpu.dcache.overall_hits::total 13655679 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1068700 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1068700 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13655672 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655672 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655672 # number of overall hits +system.cpu.dcache.overall_hits::total 13655672 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1068707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1068707 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304387 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304387 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373087 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373087 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373087 # number of overall misses -system.cpu.dcache.overall_misses::total 1373087 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22867911000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22867911000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385686000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8385686000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1373094 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373094 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373094 # number of overall misses +system.cpu.dcache.overall_misses::total 1373094 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22868320000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22868320000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385649000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8385649000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228869000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 228869000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31253597000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31253597000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31253597000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31253597000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31253969000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31253969000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31253969000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31253969000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 8876094 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8876094 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152672 # number of WriteReq accesses(hits+misses) @@ -756,8 +756,8 @@ system.cpu.dcache.demand_accesses::cpu.data 15028766 # system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15028766 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120402 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120402 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120403 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120403 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049472 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049472 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses @@ -766,16 +766,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.091364 system.cpu.dcache.demand_miss_rate::total 0.091364 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091364 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.091364 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21397.876860 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21397.876860 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.422282 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.422282 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21398.119410 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21398.119410 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.300726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.300726 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13272.384598 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22761.711143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22761.711143 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -784,36 +784,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834498 # number of writebacks -system.cpu.dcache.writebacks::total 834498 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068700 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068700 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks +system.cpu.dcache.writebacks::total 834499 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068707 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1068707 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304387 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 304387 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373087 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373087 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373087 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373087 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730511000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730511000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1373094 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373094 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373094 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373094 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776875000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776875000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194381000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194381000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507423000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28507423000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507423000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28507423000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507781000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28507781000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507781000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28507781000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120403 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses @@ -822,16 +822,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364 system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19398.119410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19398.119410 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.300726 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.300726 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 38cfd80e2..2f6691c8d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.195162 # Nu sim_ticks 5195162021000 # Number of ticks simulated final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 926995 # Simulator instruction rate (inst/s) -host_op_rate 1786992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37543942770 # Simulator tick rate (ticks/s) -host_mem_usage 611560 # Number of bytes of host memory used -host_seconds 138.38 # Real time elapsed on the host -sim_insts 128273323 # Number of instructions simulated -sim_ops 247275942 # Number of ops (including micro ops) simulated +host_inst_rate 697576 # Simulator instruction rate (inst/s) +host_op_rate 1344736 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28252317760 # Simulator tick rate (ticks/s) +host_mem_usage 611664 # Number of bytes of host memory used +host_seconds 183.88 # Real time elapsed on the host +sim_insts 128273373 # Number of instructions simulated +sim_ops 247275988 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -48,16 +48,16 @@ system.physmem.bw_total::cpu.data 1734722 # To system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 198400 # Total number of read requests seen system.physmem.writeReqs 126924 # Total number of write requests seen -system.physmem.cpureqs 327581 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 326952 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 12697600 # Total number of bytes read from memory system.physmem.bytesWritten 8123136 # Total number of bytes written to memory system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12234 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis @@ -88,7 +88,7 @@ system.physmem.perBankWrReqs::13 7628 # Tr system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 633 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry system.physmem.totGap 5195161957500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -104,27 +104,27 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 126924 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 155117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 155109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -136,15 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5514 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see @@ -159,23 +159,23 @@ system.physmem.wrQLenPdf::19 5518 # Wh system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.totQLat 4073325250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7869155250 # Sum of mem lat for all requests -system.physmem.totBusLat 991710000 # Total cycles spent in databus access -system.physmem.totBankLat 2804120000 # Total cycles spent in bank access -system.physmem.avgQLat 20536.88 # Average queueing delay per request -system.physmem.avgBankLat 14137.80 # Average bank access latency per request +system.physmem.wrQLenPdf::23 1323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.totQLat 4118897499 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7915241249 # Sum of mem lat for all requests +system.physmem.totBusLat 991715000 # Total cycles spent in databus access +system.physmem.totBankLat 2804628750 # Total cycles spent in bank access +system.physmem.avgQLat 20766.54 # Average queueing delay per request +system.physmem.avgBankLat 14140.30 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39674.68 # Average memory access latency +system.physmem.avgMemAccLat 39906.83 # Average memory access latency system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s @@ -184,8 +184,8 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.66 # Average write queue length over time -system.physmem.readRowHits 175586 # Number of row buffer hits during reads -system.physmem.writeRowHits 94818 # Number of row buffer hits during writes +system.physmem.readRowHits 175593 # Number of row buffer hits during reads +system.physmem.writeRowHits 94810 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes system.physmem.avgGap 15969193.66 # Average gap between requests @@ -206,14 +206,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47564 system.iocache.demand_misses::total 47564 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses system.iocache.overall_misses::total 47564 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10699969160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10699969160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10839449092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10839449092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10839449092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10839449092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137986397 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 137986397 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732357682 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10732357682 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10870344079 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10870344079 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10870344079 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10870344079 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -230,19 +230,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229023.312500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229023.312500 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227891.873938 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227891.873938 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 173195 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163490.991706 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 163490.991706 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.559974 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229716.559974 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228541.419540 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228541.419540 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 175903 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16181 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16290 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.703603 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.798220 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -256,14 +256,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 95570962 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8269165315 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8269165315 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8364736277 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8364736277 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94077427 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 94077427 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301559588 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8301559588 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8395637015 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8395637015 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.736967 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.736967 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176994.120612 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176994.120612 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111466.145735 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111466.145735 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.491182 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.491182 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -296,72 +296,72 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10390324042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128273323 # Number of instructions committed -system.cpu.committedOps 247275942 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232011652 # Number of integer alu accesses +system.cpu.committedInsts 128273373 # Number of instructions committed +system.cpu.committedOps 247275988 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232011695 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls -system.cpu.num_int_insts 232011652 # number of integer instructions +system.cpu.num_conditional_control_insts 23157364 # number of instructions that are conditional controls +system.cpu.num_int_insts 232011695 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567056066 # number of times the integer registers were read -system.cpu.num_int_register_writes 293242220 # number of times the integer registers were written +system.cpu.num_int_register_reads 567056109 # number of times the integer registers were read +system.cpu.num_int_register_writes 293242196 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22232130 # number of memory refs -system.cpu.num_load_insts 13871776 # Number of load instructions -system.cpu.num_store_insts 8360354 # Number of store instructions -system.cpu.num_idle_cycles 9789674914.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600649127.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942191 # Percentage of idle cycles +system.cpu.num_mem_refs 22232145 # number of memory refs +system.cpu.num_load_insts 13871789 # Number of load instructions +system.cpu.num_store_insts 8360356 # Number of store instructions +system.cpu.num_idle_cycles 9789660715.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600663326.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057810 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942190 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791510 # number of replacements +system.cpu.icache.replacements 791527 # number of replacements system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use -system.cpu.icache.total_refs 144497671 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 792022 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.441486 # Average number of references to valid blocks. +system.cpu.icache.total_refs 144497724 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 792039 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.437638 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144497671 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144497671 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144497671 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144497671 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144497671 # number of overall hits -system.cpu.icache.overall_hits::total 144497671 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792029 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792029 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792029 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792029 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792029 # number of overall misses -system.cpu.icache.overall_misses::total 792029 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10955241500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10955241500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10955241500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10955241500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10955241500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10955241500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145289700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145289700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145289700 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145289700 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145289700 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145289700 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144497724 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144497724 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144497724 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144497724 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144497724 # number of overall hits +system.cpu.icache.overall_hits::total 144497724 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792046 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792046 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792046 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792046 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792046 # number of overall misses +system.cpu.icache.overall_misses::total 792046 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10958971500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10958971500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10958971500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10958971500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10958971500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10958971500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145289770 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145289770 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145289770 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145289770 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145289770 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145289770 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13831.869161 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13831.869161 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13831.869161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13831.869161 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13836.281605 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13836.281605 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13836.281605 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13836.281605 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,40 +370,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792029 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 792029 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 792029 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 792029 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 792029 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 792029 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9371183500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9371183500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9371183500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9371183500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9371183500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9371183500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792046 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 792046 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 792046 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 792046 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 792046 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 792046 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9374879500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9374879500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9374879500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9374879500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9374879500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9374879500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11831.869161 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11831.869161 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11836.281605 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11836.281605 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3425 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.077882 # Cycle average of tags in use +system.cpu.itb_walker_cache.tagsinuse 3.077880 # Cycle average of tags in use system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5164118674000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077882 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192368 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.192368 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.warmup_cycle 5164120857000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077880 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192367 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.192367 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8004 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 8004 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -479,13 +479,13 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7540 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.062515 # Cycle average of tags in use +system.cpu.dtb_walker_cache.replacements 7539 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.062514 # Cycle average of tags in use system.cpu.dtb_walker_cache.total_refs 13178 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7554 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.744506 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7553 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.744737 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062515 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062514 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits @@ -559,63 +559,63 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8554.033922 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1618785 # number of replacements +system.cpu.dcache.replacements 1618797 # number of replacements system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use -system.cpu.dcache.total_refs 20025893 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1619297 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.367029 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20025896 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1619309 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.366939 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11988262 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11988262 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8035470 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8035470 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20023732 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20023732 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20023732 # number of overall hits -system.cpu.dcache.overall_hits::total 20023732 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1306602 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1306602 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 314890 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 314890 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1621492 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1621492 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1621492 # number of overall misses -system.cpu.dcache.overall_misses::total 1621492 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18343104000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18343104000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556691000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8556691000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26899795000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26899795000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26899795000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26899795000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13294864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13294864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350360 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350360 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21645224 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21645224 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21645224 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21645224 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098279 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098279 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11988260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11988260 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035474 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035474 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20023734 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20023734 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20023734 # number of overall hits +system.cpu.dcache.overall_hits::total 20023734 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1306617 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1306617 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1621505 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1621505 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1621505 # number of overall misses +system.cpu.dcache.overall_misses::total 1621505 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18345510500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18345510500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8557598000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8557598000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26903108500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26903108500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26903108500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26903108500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13294877 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13294877 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8350362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21645239 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21645239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21645239 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21645239 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098280 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098280 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037710 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.037710 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074912 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074912 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074912 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074912 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.784573 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.784573 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27173.587602 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27173.587602 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16589.532973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16589.532973 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.074913 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074913 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074913 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074913 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14040.465186 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14040.465186 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27176.640583 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27176.640583 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16591.443443 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16591.443443 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,46 +624,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1536047 # number of writebacks -system.cpu.dcache.writebacks::total 1536047 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306602 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1306602 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314890 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 314890 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1621492 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1621492 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1621492 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1621492 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15729900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15729900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926911000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926911000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23656811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23656811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23656811000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23656811000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1536058 # number of writebacks +system.cpu.dcache.writebacks::total 1536058 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1306617 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1621505 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1621505 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1621505 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1621505 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15732276500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15732276500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7927822000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7927822000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23660098500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23660098500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23660098500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23660098500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467832500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467832500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613781500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613781500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098279 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467833000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467833000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613782000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613782000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098280 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098280 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037710 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037710 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074912 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074912 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12038.784573 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12038.784573 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25173.587602 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25173.587602 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074913 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074913 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12040.465186 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12040.465186 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25176.640583 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25176.640583 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -672,17 +672,17 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 86864 # number of replacements -system.cpu.l2cache.tagsinuse 64770.428925 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3484716 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 64770.428854 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3484759 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.981554 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 22.981837 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50336.266909 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 50336.272506 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.007172 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140366 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3358.136526 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11075.877952 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.768070 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140365 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3358.130752 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11075.878059 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.768071 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.051241 # Average percentage of cache occupancy @@ -690,25 +690,25 @@ system.cpu.l2cache.occ_percent::cpu.data 0.169004 # Av system.cpu.l2cache.occ_percent::total 0.988318 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6347 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2754 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779144 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1277462 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2065707 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1539401 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1539401 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779161 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1277476 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2065738 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1539412 # 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number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses @@ -867,37 +867,37 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362485 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362485 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063901 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063900 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063900 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48770.886964 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45633.854395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46613.996074 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36966.171554 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36966.171554 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49043.533017 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45712.487335 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46753.140004 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10716.162023 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10716.162023 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36974.038224 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36974.038224 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 159c48ed1..08d964bc4 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,634 +1,633 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000759 # Number of seconds simulated -sim_ticks 758619000 # Number of ticks simulated -final_tick 758619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000758 # Number of seconds simulated +sim_ticks 758227000 # Number of ticks simulated +final_tick 758227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 45315591 # Simulator tick rate (ticks/s) -host_mem_usage 399988 # Number of bytes of host memory used -host_seconds 16.74 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 93443 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 93419 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 89535 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 90172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 93283 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 92172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 94553 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 91950 # Number of bytes read from this memory -system.physmem.bytes_read::total 738527 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 485568 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5315 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5220 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5162 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5331 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5296 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5419 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5320 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5436 # Number of bytes written to this memory -system.physmem.bytes_written::total 528067 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11194 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88997 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7587 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5315 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5220 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5162 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5331 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5296 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5419 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5320 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5436 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50086 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 123175138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 123143502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 118023672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 118863356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 122964228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 121499725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 124638323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 121207088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 973515032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 640068335 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7006152 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6880924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 6804470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7027243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6981106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7143243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7012743 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7165652 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 696089869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 640068335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 130181290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 130024426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 124828142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 125890599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 129945335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 128642968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 131651066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 128372740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1669604900 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15559 # number of replacements -system.l2c.tagsinuse 800.707629 # Cycle average of tags in use -system.l2c.total_refs 151038 # Total number of references to valid blocks. -system.l2c.sampled_refs 16357 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.233845 # Average number of references to valid blocks. +host_tick_rate 200763174 # Simulator tick rate (ticks/s) +host_mem_usage 353776 # Number of bytes of host memory used +host_seconds 3.78 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 94296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 93084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 90684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 91125 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 90329 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 98961 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 91564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 94442 # Number of bytes read from this memory +system.physmem.bytes_read::total 744485 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 495744 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5338 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5288 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5371 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5302 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5445 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5231 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5430 # Number of bytes written to this memory +system.physmem.bytes_written::total 538519 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10932 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11202 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11345 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89033 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7746 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5338 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5288 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5371 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5302 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5445 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5231 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5430 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50521 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 124363812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 122765346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 119600067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 120181687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 119131869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 130516323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 120760669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 124556366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 981876140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 653820030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7040108 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6974165 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7083631 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6992629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 7181227 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 6898989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7082312 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7161444 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 710234534 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 653820030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 131403920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 129739511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 126683698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 127174316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 126313096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 137415312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 127842981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 131717810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1692110674 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15709 # number of replacements +system.l2c.tagsinuse 802.621152 # Cycle average of tags in use +system.l2c.total_refs 152986 # Total number of references to valid blocks. +system.l2c.sampled_refs 16508 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.267386 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 736.955948 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.896049 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.875266 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.499139 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.819632 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 8.127236 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 8.346952 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 8.379667 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 7.807741 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.719684 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007711 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007691 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007323 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007636 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007937 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.008151 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.008183 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.007625 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781941 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10425 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10868 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10852 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10879 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10945 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10774 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10623 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86293 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76698 # number of Writeback hits -system.l2c.Writeback_hits::total 76698 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 360 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 388 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 372 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 365 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 360 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 369 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2938 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2007 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1980 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2070 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2061 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1961 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2103 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16299 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12432 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12832 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 13006 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12726 # number of demand (read+write) hits -system.l2c.demand_hits::total 102592 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12432 # number of overall hits -system.l2c.overall_hits::cpu1 12963 # number of overall hits -system.l2c.overall_hits::cpu2 12832 # number of overall hits -system.l2c.overall_hits::cpu3 12949 # number of overall hits -system.l2c.overall_hits::cpu4 12949 # number of overall hits -system.l2c.overall_hits::cpu5 13006 # number of overall hits -system.l2c.overall_hits::cpu6 12735 # number of overall hits -system.l2c.overall_hits::cpu7 12726 # number of overall hits -system.l2c.overall_hits::total 102592 # number of overall hits -system.l2c.ReadReq_misses::cpu0 852 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 872 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 800 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 819 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 93100 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 76698 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 76698 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2283 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2164 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2311 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2182 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2165 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2205 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2226 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2237 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17773 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6257 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6468 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6193 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6365 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6303 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6255 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6411 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50564 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17534 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18208 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18063 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18106 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18128 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17898 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17882 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143664 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17534 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18208 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17845 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18063 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18106 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18128 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17898 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17882 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143664 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.075552 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.074276 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.068658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.070012 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.074218 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.073714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.074637 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.073926 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.073115 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.841437 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.833641 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.832107 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.829514 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.832794 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.834467 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.838275 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.835047 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.834693 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.679239 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.676098 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.680284 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.674784 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.679200 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.673479 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.686491 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.671970 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.677656 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.290978 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.288060 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.280919 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.283120 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.284823 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.282546 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.288468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.288335 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.285889 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.290978 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.288060 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.280919 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.283120 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.284823 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.282546 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.288468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.288335 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.285889 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 59222.949531 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 59900.165138 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 59754.930000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 59901.647131 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 58857.227169 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 60057.898967 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 58738.716916 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59022.336085 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 59426.845453 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28501.248829 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 27706.986696 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29199.117005 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29554.644199 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28250.644481 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28135.827717 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28648.929796 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29005.031049 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28629.878463 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53704.619529 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53734.991310 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53877.670544 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.444936 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53868.637234 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53885.814632 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53881.023754 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53889.766249 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53837.660878 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54626.143865 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54759.973499 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54815.593457 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54827.935080 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54716.030056 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54935.382273 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54698.636645 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54733.912723 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54763.975141 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54626.143865 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54759.973499 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54815.593457 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54827.935080 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54716.030056 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54935.382273 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54698.636645 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54733.912723 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54763.975141 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 10793 # number of cycles access was blocked +system.l2c.occ_blocks::writebacks 738.344301 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.856749 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.750709 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 7.581062 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 8.075895 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.623690 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 8.411297 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 8.326520 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 8.650930 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.721039 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007673 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007569 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007403 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007887 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007445 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.008214 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.008131 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.008448 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783810 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 11060 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10905 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10917 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10908 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 11025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10769 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 11003 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 11044 # number of ReadReq hits +system.l2c.ReadReq_hits::total 87631 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77283 # number of Writeback hits +system.l2c.Writeback_hits::total 77283 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 381 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 372 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 389 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 412 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 335 # 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number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 55911401 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 54499902 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 55745405 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 435303755 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 229815657 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 230400614 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 235881114 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 230703609 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 235441620 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 233239630 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 238696088 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 232987140 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11680 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11851 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11934 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 94422 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77283 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77283 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2321 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2274 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2226 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2246 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2275 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2240 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2285 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18149 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6279 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6366 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6369 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6276 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6439 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6314 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6509 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6333 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50885 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18096 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18093 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18035 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18292 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17994 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18360 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18267 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 145307 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18096 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18093 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18035 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18292 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17994 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18360 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18267 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 145307 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.069885 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.070332 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.068833 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.072370 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.069856 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.077997 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.071555 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.074577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.071922 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.835847 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.836412 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.825247 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.816563 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.852747 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.845089 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.835670 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.837637 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.835693 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.678771 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.672322 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.686607 # 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average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 60578.608426 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 59535.757932 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61088.085749 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 59778.755214 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 60649.102594 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 59660.591011 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 60240.609778 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28790.936082 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28313.562566 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 28965.924878 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27764.952563 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28509.746392 # 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average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53882.317299 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53897.337759 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55017.100334 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 54845.944564 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54974.527220 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54890.468006 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54951.499520 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55009.192352 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54937.800985 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54868.635596 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54936.995052 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55017.100334 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 54845.944564 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54974.527220 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54890.468006 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54951.499520 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55009.192352 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54937.800985 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54868.635596 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54936.995052 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 12946 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1480 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1808 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.292568 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.160398 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7587 # number of writebacks -system.l2c.writebacks::total 7587 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 7746 # number of writebacks +system.l2c.writebacks::total 7746 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 32 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 29 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 92 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 845 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 865 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 794 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 809 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 871 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 865 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 859 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 839 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6747 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1921 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1804 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1923 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1809 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1803 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1840 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1865 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1868 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14833 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4243 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4367 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4211 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4291 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4278 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4245 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4291 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4307 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34233 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5088 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5232 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5005 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5100 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5149 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5110 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5150 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5146 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40980 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5088 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5232 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5005 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5100 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5149 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5110 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5150 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5146 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40980 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 39952953 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 41536444 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 37955945 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 38925950 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 40835431 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 41565931 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 40269445 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 39637942 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 320680041 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78868808 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 73978329 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78794825 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 74230834 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 74073835 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 75455362 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76452812 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 76637320 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 608492125 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 176592133 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 181884117 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 175861127 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 179102612 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 178683137 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 177427598 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 179259117 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 179911613 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1428721454 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 216545086 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 223420561 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 213817072 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 218028562 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 219518568 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 218993529 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 219528562 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 219549555 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1749401495 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 216545086 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 223420561 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 213817072 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 218028562 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 219518568 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 218993529 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 219528562 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 219549555 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1749401495 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 402081632 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 400575089 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 409123618 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 408517090 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 408283130 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 406615614 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 405150633 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 405778615 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3246125421 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 225621486 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222590493 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 219789492 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 227766486 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225717983 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 229461987 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226436485 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 231064489 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1808448901 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 627703118 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 623165582 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 628913110 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 636283576 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 634001113 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 636077601 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 631587118 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 636843104 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5054574322 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.074931 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.073680 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068143 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.069157 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.073795 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.073206 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.073778 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073141 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.072470 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.841437 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.833641 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.832107 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.829056 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.832794 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.834467 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.837826 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.835047 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.834581 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.678121 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.675170 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679961 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.674156 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678724 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672529 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.686011 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.671814 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.677023 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285249 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285249 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 47281.601183 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48019.010405 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 47803.457179 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 48116.131026 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46883.388060 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48053.099422 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46879.447031 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47244.269368 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 47529.278346 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.120770 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41007.942905 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40974.947998 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41034.181316 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41083.657793 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41008.348913 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40993.464879 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41026.402570 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41022.862873 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41619.640113 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41649.671857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41762.319402 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41739.131205 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41767.914212 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41796.842874 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41775.604055 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41771.909218 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41735.210294 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 828 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 815 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 804 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 844 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 824 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 909 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 843 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 883 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6750 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1940 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1901 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1837 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1834 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1940 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1892 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1907 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1914 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15165 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4255 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4276 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4373 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4271 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4372 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4316 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4430 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4321 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34614 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5083 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5091 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5177 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5115 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5196 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5225 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5273 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5204 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 41364 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5083 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5091 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5177 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5115 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5196 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5225 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5273 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5204 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 41364 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 40211435 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 39357435 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 39064937 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 40158430 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 40512435 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 43385946 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 40969439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 42146427 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 325806484 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 79643349 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78062835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 75255324 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 75287345 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79635834 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77713835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78284820 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 78593341 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 622476683 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 178045657 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 178454114 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 182867114 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 178794609 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 182240620 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 180819630 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 184924089 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 180516140 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1446661973 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 218257092 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 217811549 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 221932051 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 218953039 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 222753055 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 224205576 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 225893528 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 222662567 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1772468457 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 218257092 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 217811549 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 221932051 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 218953039 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 222753055 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 224205576 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 225893528 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 222662567 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1772468457 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 410453631 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 397457157 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 406979111 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 406829637 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 405432120 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405171118 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 400882109 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 414057617 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3247262500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 226073488 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 225167477 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 228704981 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 225137481 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230851979 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 222187990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 228117990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230091986 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1816333372 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 636527119 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 622624634 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 635684092 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 631967118 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 636284099 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 627359108 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 629000099 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 644149603 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5063595872 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.069632 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.069480 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.071775 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069518 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.077825 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.071133 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073990 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.071488 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.835847 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.835972 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.825247 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.816563 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.852747 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844643 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.835670 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.837637 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.835583 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.677656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.671693 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.686607 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680529 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678987 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.683560 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680596 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.682299 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.680240 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.284666 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.284666 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48564.535024 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48291.331288 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48588.230100 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47581.078199 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49165.576456 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47729.313531 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 48599.571767 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47730.947905 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 48267.627259 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41053.272680 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41064.089953 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40966.425694 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41050.896947 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41049.398969 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41074.965645 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41051.295228 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41062.351620 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41046.929311 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41843.867685 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41733.890084 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41817.313972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41862.469913 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41683.581885 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41895.187674 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41743.586682 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41776.473039 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41794.128763 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -657,114 +656,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 97622 # number of read accesses completed -system.cpu0.num_writes 53016 # number of write accesses completed +system.cpu0.num_reads 98877 # number of read accesses completed +system.cpu0.num_writes 53303 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 21387 # number of replacements -system.cpu0.l1c.tagsinuse 393.959213 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13124 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 21798 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.602074 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22594 # number of replacements +system.cpu0.l1c.tagsinuse 395.326045 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13097 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 23010 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.569187 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 393.959213 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.769452 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.769452 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8513 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8513 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1098 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9611 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9611 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9611 # number of overall hits -system.cpu0.l1c.overall_hits::total 9611 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35379 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35379 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 22892 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 22892 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58271 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58271 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58271 # number of overall misses -system.cpu0.l1c.overall_misses::total 58271 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1332854037 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1332854037 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1090035309 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1090035309 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2422889346 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2422889346 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2422889346 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2422889346 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 43892 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 43892 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 23990 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 23990 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 67882 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 67882 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 67882 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 67882 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806047 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.806047 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954231 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954231 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858416 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858416 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858416 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858416 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37673.592724 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 37673.592724 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 47616.429713 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 47616.429713 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 41579.676786 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 41579.676786 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 41579.676786 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 41579.676786 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1432667 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 395.326045 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.772121 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.772121 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8525 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8525 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9567 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9567 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9567 # number of overall hits +system.cpu0.l1c.overall_hits::total 9567 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36170 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36170 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23033 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59203 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59203 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59203 # number of overall misses +system.cpu0.l1c.overall_misses::total 59203 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1338428684 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1338428684 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1081120140 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1081120140 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2419548824 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2419548824 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2419548824 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2419548824 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44695 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44695 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24075 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24075 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68770 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68770 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68770 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68770 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809263 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809263 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956719 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956719 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860884 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860884 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860884 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860884 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37003.834227 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 37003.834227 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 46937.877827 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 46937.877827 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 40868.686114 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 40868.686114 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 40868.686114 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 40868.686114 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1431079 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66221 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 67309 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.634633 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.261332 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9284 # number of writebacks -system.cpu0.l1c.writebacks::total 9284 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35379 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35379 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22892 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 22892 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58271 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58271 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58271 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58271 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1262100037 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1262100037 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1044251309 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1044251309 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2306351346 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2306351346 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2306351346 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2306351346 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 709848172 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 709848172 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 441878494 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 441878494 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1151726666 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1151726666 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806047 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806047 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954231 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954231 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858416 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858416 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35673.705786 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35673.705786 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 45616.429713 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 45616.429713 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9829 # number of writebacks +system.cpu0.l1c.writebacks::total 9829 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36170 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23033 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59203 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59203 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59203 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59203 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1266094684 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1266094684 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1035054140 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1035054140 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2301148824 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2301148824 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2301148824 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2301148824 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 713940998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 713940998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 425679500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 425679500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1139620498 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1139620498 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809263 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809263 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956719 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956719 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860884 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860884 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35004.000111 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35004.000111 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 44937.877827 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 44937.877827 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -772,114 +771,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98743 # number of read accesses completed -system.cpu1.num_writes 53079 # number of write accesses completed +system.cpu1.num_reads 98330 # number of read accesses completed +system.cpu1.num_writes 53283 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 22269 # number of replacements -system.cpu1.l1c.tagsinuse 395.693103 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13156 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22645 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.580967 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 22413 # number of replacements +system.cpu1.l1c.tagsinuse 397.274781 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13337 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22810 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.584700 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 395.693103 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.772838 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.772838 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8677 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8677 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1112 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1112 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9789 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9789 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9789 # number of overall hits -system.cpu1.l1c.overall_hits::total 9789 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35979 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35979 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22841 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22841 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 58820 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 58820 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 58820 # number of overall misses -system.cpu1.l1c.overall_misses::total 58820 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1346712982 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1346712982 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1084415887 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1084415887 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2431128869 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2431128869 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2431128869 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2431128869 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44656 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44656 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23953 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23953 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68609 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68609 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68609 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68609 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805692 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805692 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953576 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953576 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857322 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857322 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857322 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857322 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37430.528419 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 37430.528419 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47476.725494 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 47476.725494 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 41331.670673 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 41331.670673 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 41331.670673 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 41331.670673 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1432282 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 397.274781 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.775927 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.775927 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8758 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8758 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1087 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1087 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9845 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9845 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9845 # number of overall hits +system.cpu1.l1c.overall_hits::total 9845 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35763 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35763 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23060 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23060 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58823 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58823 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58823 # number of overall misses +system.cpu1.l1c.overall_misses::total 58823 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1339256827 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1339256827 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1098702208 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1098702208 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2437959035 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2437959035 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2437959035 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2437959035 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44521 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24147 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24147 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68668 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68668 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68668 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68668 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803284 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.803284 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954984 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954984 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.856629 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.856629 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.856629 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.856629 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37448.111931 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 37448.111931 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47645.368951 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 47645.368951 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 41445.676606 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 41445.676606 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 41445.676606 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 41445.676606 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1431601 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66708 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66652 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.470918 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.478740 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9759 # number of writebacks -system.cpu1.l1c.writebacks::total 9759 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35979 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22841 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22841 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 58820 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 58820 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 58820 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 58820 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1274756982 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1274756982 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1038739887 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1038739887 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2313496869 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2313496869 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2313496869 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2313496869 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 702867762 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 702867762 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 426288670 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 426288670 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1129156432 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1129156432 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805692 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805692 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953576 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953576 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857322 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857322 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35430.584007 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35430.584007 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45476.988179 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45476.988179 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9847 # number of writebacks +system.cpu1.l1c.writebacks::total 9847 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23060 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58823 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58823 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58823 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58823 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1267732827 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1267732827 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1052584208 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1052584208 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2320317035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2320317035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2320317035 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2320317035 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 694424746 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 694424746 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 428704098 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 428704098 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1123128844 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1123128844 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803284 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803284 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954984 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954984 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.856629 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.856629 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35448.167855 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35448.167855 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45645.455681 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45645.455681 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -887,114 +886,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 98534 # number of read accesses completed -system.cpu2.num_writes 52787 # number of write accesses completed +system.cpu2.num_reads 98918 # number of read accesses completed +system.cpu2.num_writes 53026 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 21873 # number of replacements -system.cpu2.l1c.tagsinuse 394.149978 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13285 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22270 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.596542 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22091 # number of replacements +system.cpu2.l1c.tagsinuse 394.122068 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13053 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22474 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.580804 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 394.149978 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.769824 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.769824 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8620 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8620 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1112 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1112 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9732 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9732 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9732 # number of overall hits -system.cpu2.l1c.overall_hits::total 9732 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 35901 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 35901 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22666 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22666 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 58567 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 58567 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 58567 # number of overall misses -system.cpu2.l1c.overall_misses::total 58567 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1333102057 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1333102057 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1080309021 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1080309021 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2413411078 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2413411078 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2413411078 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2413411078 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44521 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23778 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23778 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68299 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68299 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68299 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68299 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806384 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806384 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953234 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953234 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.857509 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.857509 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.857509 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.857509 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37132.727696 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 37132.727696 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47662.093929 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 47662.093929 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 41207.695084 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 41207.695084 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 41207.695084 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 41207.695084 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1432337 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 394.122068 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.769770 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.769770 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1062 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9719 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9719 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9719 # number of overall hits +system.cpu2.l1c.overall_hits::total 9719 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35792 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35792 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22782 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22782 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58574 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58574 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58574 # number of overall misses +system.cpu2.l1c.overall_misses::total 58574 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1334540137 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1334540137 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1086319531 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1086319531 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2420859668 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2420859668 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2420859668 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2420859668 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23844 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23844 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68293 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68293 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68293 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68293 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805237 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805237 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955460 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955460 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.857687 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.857687 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.857687 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.857687 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37285.989523 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 37285.989523 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47683.238127 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 47683.238127 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 41329.935944 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 41329.935944 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 41329.935944 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 41329.935944 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1431481 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66669 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66558 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.484303 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.507272 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9470 # number of writebacks -system.cpu2.l1c.writebacks::total 9470 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35901 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35901 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22666 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22666 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58567 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58567 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58567 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58567 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1261304057 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1261304057 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1034981021 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1034981021 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2296285078 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2296285078 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2296285078 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2296285078 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 719957534 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 719957534 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 417914602 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 417914602 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1137872136 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1137872136 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806384 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806384 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953234 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953234 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.857509 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.857509 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35132.839113 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35132.839113 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45662.270405 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45662.270405 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9590 # number of writebacks +system.cpu2.l1c.writebacks::total 9590 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22782 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22782 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58574 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58574 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58574 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58574 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1262960137 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1262960137 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040755531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040755531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2303715668 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2303715668 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2303715668 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2303715668 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 710805276 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 710805276 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 431026471 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 431026471 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1141831747 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1141831747 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805237 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805237 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955460 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955460 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.857687 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.857687 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35286.101280 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35286.101280 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45683.238127 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45683.238127 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1002,114 +1001,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99583 # number of read accesses completed -system.cpu3.num_writes 53448 # number of write accesses completed +system.cpu3.num_reads 98879 # number of read accesses completed +system.cpu3.num_writes 53514 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22221 # number of replacements -system.cpu3.l1c.tagsinuse 395.683952 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13227 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22614 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.584903 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 22321 # number of replacements +system.cpu3.l1c.tagsinuse 395.059941 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13052 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22702 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.574927 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.683952 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.772820 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.772820 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8699 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8699 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1092 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1092 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9791 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9791 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9791 # number of overall hits -system.cpu3.l1c.overall_hits::total 9791 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35935 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35935 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23086 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23086 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59021 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59021 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59021 # number of overall misses -system.cpu3.l1c.overall_misses::total 59021 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1329205475 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1329205475 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1090244238 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1090244238 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2419449713 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2419449713 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2419449713 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2419449713 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44634 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44634 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24178 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24178 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68812 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68812 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68812 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68812 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805104 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805104 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954835 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954835 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.857714 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.857714 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.857714 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.857714 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 36989.160289 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 36989.160289 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47225.341679 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 47225.341679 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 40993.031514 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 40993.031514 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 40993.031514 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 40993.031514 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1431757 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 395.059941 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.771601 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.771601 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1034 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1034 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9596 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9596 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9596 # number of overall hits +system.cpu3.l1c.overall_hits::total 9596 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35946 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35946 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22965 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22965 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58911 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58911 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58911 # number of overall misses +system.cpu3.l1c.overall_misses::total 58911 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1334193508 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1334193508 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1085703243 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1085703243 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2419896751 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2419896751 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2419896751 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2419896751 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44508 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44508 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 23999 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 23999 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68507 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68507 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68507 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68507 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807630 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807630 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956915 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.956915 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859927 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859927 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859927 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859927 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 37116.605686 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 37116.605686 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47276.431221 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 47276.431221 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 41077.163026 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 41077.163026 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 41077.163026 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 41077.163026 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1431288 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 67125 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66945 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.329713 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.380058 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9875 # number of writebacks -system.cpu3.l1c.writebacks::total 9875 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35935 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35935 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23086 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23086 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59021 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59021 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59021 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59021 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1257339475 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1257339475 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1044074238 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1044074238 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2301413713 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2301413713 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2301413713 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2301413713 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 714868620 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 714868620 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 436247033 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 436247033 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1151115653 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1151115653 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805104 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805104 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954835 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954835 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.857714 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.857714 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34989.271602 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34989.271602 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45225.428312 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45225.428312 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9751 # number of writebacks +system.cpu3.l1c.writebacks::total 9751 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35946 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35946 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22965 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58911 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58911 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58911 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58911 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1262305508 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1262305508 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1039775243 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1039775243 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2302080751 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2302080751 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2302080751 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2302080751 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 712475632 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 712475632 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 424398019 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 424398019 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1136873651 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1136873651 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807630 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807630 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956915 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956915 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859927 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859927 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 35116.716964 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35116.716964 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45276.518310 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45276.518310 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1117,114 +1116,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53418 # number of write accesses completed +system.cpu4.num_reads 99302 # number of read accesses completed +system.cpu4.num_writes 53818 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22068 # number of replacements -system.cpu4.l1c.tagsinuse 394.143159 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13375 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22471 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.595212 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22353 # number of replacements +system.cpu4.l1c.tagsinuse 396.021323 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13287 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22757 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.583864 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 394.143159 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.769811 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.769811 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8810 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8810 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1141 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1141 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9951 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9951 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9951 # number of overall hits -system.cpu4.l1c.overall_hits::total 9951 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36179 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36179 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22735 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22735 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 58914 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 58914 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 58914 # number of overall misses -system.cpu4.l1c.overall_misses::total 58914 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1352891584 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1352891584 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1067419012 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1067419012 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2420310596 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2420310596 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2420310596 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2420310596 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44989 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44989 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 23876 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 23876 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68865 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68865 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68865 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68865 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804174 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804174 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952211 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952211 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.855500 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.855500 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.855500 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.855500 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 37394.388568 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 37394.388568 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 46950.473367 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 46950.473367 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 41082.095869 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 41082.095869 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 41082.095869 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 41082.095869 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1431267 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 396.021323 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.773479 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.773479 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8768 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8768 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1075 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1075 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9843 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9843 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9843 # number of overall hits +system.cpu4.l1c.overall_hits::total 9843 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36125 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36125 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22981 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22981 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59106 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59106 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59106 # number of overall misses +system.cpu4.l1c.overall_misses::total 59106 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1336431585 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1336431585 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1085022253 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1085022253 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2421453838 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2421453838 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2421453838 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2421453838 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44893 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44893 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24056 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24056 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68949 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68949 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68949 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68949 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804691 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.804691 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955313 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.955313 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857242 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857242 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857242 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857242 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 36994.645952 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 36994.645952 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 47213.883338 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 47213.883338 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 40967.986973 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 40967.986973 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 40967.986973 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 40967.986973 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1430986 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66934 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 67143 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.383258 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.312512 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9521 # number of writebacks -system.cpu4.l1c.writebacks::total 9521 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36179 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36179 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22735 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22735 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 58914 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 58914 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1280533584 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1280533584 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1021953012 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1021953012 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2302486596 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2302486596 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2302486596 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2302486596 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 712917081 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 712917081 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 441958565 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 441958565 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1154875646 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1154875646 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804174 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804174 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952211 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952211 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.855500 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.855500 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35394.388568 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35394.388568 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 44950.649307 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 44950.649307 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9680 # number of writebacks +system.cpu4.l1c.writebacks::total 9680 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36125 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36125 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22981 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22981 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59106 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59106 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59106 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59106 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1264183585 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1264183585 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1039060253 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1039060253 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2303243838 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2303243838 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2303243838 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2303243838 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 711442657 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 711442657 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 433569420 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 433569420 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1145012077 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1145012077 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804691 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804691 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955313 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955313 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857242 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857242 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 34994.701315 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 34994.701315 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45213.883338 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45213.883338 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1232,114 +1231,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99061 # number of read accesses completed -system.cpu5.num_writes 53322 # number of write accesses completed +system.cpu5.num_reads 98038 # number of read accesses completed +system.cpu5.num_writes 52677 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22382 # number of replacements -system.cpu5.l1c.tagsinuse 394.919460 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13094 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22775 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.574929 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 21614 # number of replacements +system.cpu5.l1c.tagsinuse 395.041478 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13218 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22030 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.600000 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 394.919460 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.771327 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.771327 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8623 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8623 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1083 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1083 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9706 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9706 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9706 # number of overall hits -system.cpu5.l1c.overall_hits::total 9706 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 35968 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 35968 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 22960 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 22960 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 58928 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 58928 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 58928 # number of overall misses -system.cpu5.l1c.overall_misses::total 58928 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1339036093 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1339036093 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1083656826 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1083656826 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2422692919 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2422692919 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2422692919 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2422692919 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44591 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44591 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24043 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24043 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68634 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68634 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68634 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68634 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806620 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806620 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954956 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954956 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858583 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858583 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858583 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858583 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37228.539062 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 37228.539062 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47197.596951 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 47197.596951 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 41112.763355 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 41112.763355 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 41112.763355 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 41112.763355 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1432391 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 395.041478 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.771565 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.771565 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8654 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8654 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1143 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9797 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9797 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9797 # number of overall hits +system.cpu5.l1c.overall_hits::total 9797 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 35607 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 35607 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22649 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22649 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 58256 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 58256 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 58256 # number of overall misses +system.cpu5.l1c.overall_misses::total 58256 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1343353904 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1343353904 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1075550971 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1075550971 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2418904875 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2418904875 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2418904875 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2418904875 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44261 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44261 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 23792 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 23792 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68053 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68053 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68053 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68053 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804478 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.804478 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951959 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.951959 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.856039 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.856039 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.856039 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.856039 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37727.241947 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 37727.241947 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47487.790675 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 47487.790675 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 41521.987006 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 41521.987006 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 41521.987006 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 41521.987006 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1431933 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66951 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66282 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.394617 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.603648 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9691 # number of writebacks -system.cpu5.l1c.writebacks::total 9691 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35968 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35968 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22960 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22960 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58928 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58928 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58928 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58928 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1267104093 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1267104093 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1037740826 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1037740826 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2304844919 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2304844919 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2304844919 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2304844919 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 711626590 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 711626590 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 438340423 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 438340423 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1149967013 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1149967013 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806620 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806620 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954956 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954956 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858583 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858583 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35228.650272 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35228.650272 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45197.771167 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45197.771167 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9279 # number of writebacks +system.cpu5.l1c.writebacks::total 9279 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35607 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 35607 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22649 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22649 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 58256 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 58256 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 58256 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 58256 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1272141904 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1272141904 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1030256971 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1030256971 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2302398875 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2302398875 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2302398875 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2302398875 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 712509152 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 712509152 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 420356599 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 420356599 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1132865751 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1132865751 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804478 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804478 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951959 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951959 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.856039 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.856039 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35727.298116 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35727.298116 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45487.967283 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45487.967283 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1347,114 +1346,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 98175 # number of read accesses completed -system.cpu6.num_writes 52998 # number of write accesses completed +system.cpu6.num_reads 98486 # number of read accesses completed +system.cpu6.num_writes 53296 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21915 # number of replacements -system.cpu6.l1c.tagsinuse 395.370816 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13077 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22297 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.586491 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22107 # number of replacements +system.cpu6.l1c.tagsinuse 394.242179 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13254 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22518 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.588596 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 395.370816 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.772209 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.772209 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8591 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8591 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1078 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1078 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9669 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9669 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9669 # number of overall hits -system.cpu6.l1c.overall_hits::total 9669 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35673 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35673 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22773 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22773 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 58446 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 58446 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 58446 # number of overall misses -system.cpu6.l1c.overall_misses::total 58446 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1336174857 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1336174857 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1084897863 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1084897863 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2421072720 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2421072720 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2421072720 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2421072720 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44264 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44264 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23851 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23851 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68115 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68115 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68115 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68115 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805915 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805915 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954803 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954803 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858049 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858049 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858049 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858049 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37456.195358 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 37456.195358 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47639.654986 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 47639.654986 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 41424.096089 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 41424.096089 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 41424.096089 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 41424.096089 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1432460 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 394.242179 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.770004 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.770004 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8629 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8629 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1104 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1104 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9733 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9733 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9733 # number of overall hits +system.cpu6.l1c.overall_hits::total 9733 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35833 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35833 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23033 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58866 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58866 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58866 # number of overall misses +system.cpu6.l1c.overall_misses::total 58866 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1334639245 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1334639245 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1095786214 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1095786214 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2430425459 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2430425459 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2430425459 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2430425459 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44462 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44462 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24137 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68599 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68599 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68599 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68599 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805924 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805924 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954261 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954261 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858117 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858117 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858117 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858117 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37246.092847 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 37246.092847 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47574.619633 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 47574.619633 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 41287.423283 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 41287.423283 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 41287.423283 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 41287.423283 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1431647 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66523 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66759 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.533304 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.445004 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9553 # number of writebacks -system.cpu6.l1c.writebacks::total 9553 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35673 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35673 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22773 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22773 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 58446 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 58446 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 58446 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 58446 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1264832857 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1264832857 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1039353863 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1039353863 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2304186720 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2304186720 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2304186720 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2304186720 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 711871628 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 711871628 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 446494550 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 446494550 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1158366178 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1158366178 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954803 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954803 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858049 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858049 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35456.307487 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35456.307487 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45639.742809 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45639.742809 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9651 # number of writebacks +system.cpu6.l1c.writebacks::total 9651 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35833 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35833 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58866 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58866 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58866 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58866 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1262977245 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1262977245 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1049724214 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1049724214 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2312701459 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2312701459 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2312701459 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2312701459 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702275141 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702275141 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 427671023 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 427671023 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1129946164 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1129946164 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805924 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805924 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954261 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954261 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858117 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858117 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35246.204476 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35246.204476 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45574.793297 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45574.793297 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1462,114 +1461,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98453 # number of read accesses completed -system.cpu7.num_writes 53303 # number of write accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 53815 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22126 # number of replacements -system.cpu7.l1c.tagsinuse 394.997672 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13256 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22544 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.588006 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22563 # number of replacements +system.cpu7.l1c.tagsinuse 397.316418 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13400 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22950 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.583878 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 394.997672 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.771480 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.771480 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8720 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8720 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1098 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9818 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9818 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9818 # number of overall hits -system.cpu7.l1c.overall_hits::total 9818 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35443 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35443 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23039 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23039 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58482 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58482 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58482 # number of overall misses -system.cpu7.l1c.overall_misses::total 58482 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1325635544 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1325635544 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1095033308 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1095033308 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2420668852 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2420668852 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2420668852 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2420668852 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44163 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44163 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24137 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68300 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68300 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68300 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68300 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.802550 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.802550 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954510 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954510 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.856252 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.856252 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.856252 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.856252 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37401.900065 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 37401.900065 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47529.550241 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 47529.550241 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 41391.690640 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 41391.690640 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 41391.690640 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 41391.690640 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1432038 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 397.316418 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.776009 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.776009 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8738 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8738 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1123 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1123 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9861 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9861 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9861 # number of overall hits +system.cpu7.l1c.overall_hits::total 9861 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36561 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36561 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22883 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22883 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59444 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59444 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59444 # number of overall misses +system.cpu7.l1c.overall_misses::total 59444 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1338317183 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1338317183 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1076026419 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1076026419 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2414343602 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2414343602 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2414343602 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2414343602 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69305 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69305 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69305 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69305 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807104 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807104 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953220 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953220 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857716 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857716 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857716 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857716 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 36605.048631 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 36605.048631 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47022.961106 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 47022.961106 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 40615.429682 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 40615.429682 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 40615.429682 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 40615.429682 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1430407 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 66517 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 67553 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.528902 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.174589 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9733 # number of writebacks -system.cpu7.l1c.writebacks::total 9733 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35443 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35443 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23039 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23039 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58482 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58482 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58482 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58482 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1254751544 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1254751544 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1048957308 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1048957308 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2303708852 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2303708852 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2303708852 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2303708852 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 712119692 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 712119692 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 450587409 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 450587409 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1162707101 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1162707101 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.802550 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.802550 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954510 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954510 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.856252 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.856252 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35401.956494 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35401.956494 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45529.637050 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45529.637050 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9844 # number of writebacks +system.cpu7.l1c.writebacks::total 9844 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36561 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36561 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22883 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22883 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59444 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59444 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59444 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59444 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1265201183 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1265201183 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1030262419 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1030262419 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2295463602 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2295463602 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2295463602 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2295463602 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 718920000 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 718920000 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432823408 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432823408 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1151743408 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1151743408 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807104 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807104 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953220 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953220 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857716 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857716 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 34605.212740 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 34605.212740 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45023.048508 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45023.048508 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt index fd1ec361f..3f17aa9b6 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 31243111314 # Simulator tick rate (ticks/s) -host_mem_usage 230668 # Number of bytes of host memory used -host_seconds 3.20 # Real time elapsed on the host +host_tick_rate 15527580566 # Simulator tick rate (ticks/s) +host_mem_usage 226756 # Number of bytes of host memory used +host_seconds 6.44 # Real time elapsed on the host system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory system.physmem.bytes_written::cpu 213335552 # Number of bytes written to this memory @@ -151,9 +151,9 @@ system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% # system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1 # Read request-response latency system.monitor.writeLatencyHist::samples 3333367 # Write request-response latency -system.monitor.writeLatencyHist::mean 30000 # Write request-response latency -system.monitor.writeLatencyHist::gmean 29999.999984 # Write request-response latency -system.monitor.writeLatencyHist::stdev 0 # Write request-response latency +system.monitor.writeLatencyHist::mean 30000.000098 # Write request-response latency +system.monitor.writeLatencyHist::gmean 30000.000081 # Write request-response latency +system.monitor.writeLatencyHist::stdev 0.179652 # Write request-response latency system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency @@ -204,8 +204,8 @@ system.monitor.ittReadRead::min_value 0 # Re system.monitor.ittReadRead::max_value 0 # Read-to-read inter transaction time system.monitor.ittReadRead::total 0 # Read-to-read inter transaction time system.monitor.ittWriteWrite::samples 3333367 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::mean 29999.695203 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::stdev 539.134360 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::mean 29999.695301 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::stdev 539.310304 # Write-to-write inter transaction time system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::5001-10000 99 0.00% 0.00% # Write-to-write inter transaction time @@ -229,11 +229,11 @@ system.monitor.ittWriteWrite::90001-95000 0 0.00% 100.00% # W system.monitor.ittWriteWrite::95001-100000 0 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::overflows 1 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::min_value 10000 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::max_value 994000 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::max_value 994328 # Write-to-write inter transaction time system.monitor.ittWriteWrite::total 3333367 # Write-to-write inter transaction time system.monitor.ittReqReq::samples 3333368 # Request-to-request inter transaction time system.monitor.ittReqReq::mean 29999.687703 # Request-to-request inter transaction time -system.monitor.ittReqReq::stdev 539.308135 # Request-to-request inter transaction time +system.monitor.ittReqReq::stdev 539.488612 # Request-to-request inter transaction time system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::1-5000 1 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::5001-10000 99 0.00% 0.00% # Request-to-request inter transaction time @@ -256,8 +256,8 @@ system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Re system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::min_value 5000 # Request-to-request inter transaction time -system.monitor.ittReqReq::max_value 994000 # Request-to-request inter transaction time +system.monitor.ittReqReq::min_value 4672 # Request-to-request inter transaction time +system.monitor.ittReqReq::max_value 994328 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333368 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions system.monitor.outstandingReadsHist::mean 0 # Outstanding read transactions |