diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/quick | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/quick')
28 files changed, 5893 insertions, 4431 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index f697c291f..730b05e22 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -60,6 +65,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -93,6 +99,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -115,11 +122,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu0.icache] @@ -128,6 +137,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -150,21 +160,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu0.isa] type=AlphaISA +eventq_index=0 [system.cpu0.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=AtomicSimpleCPU @@ -176,6 +191,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -209,6 +225,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -231,11 +248,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu1.icache] @@ -244,6 +263,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -266,25 +286,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu1.isa] type=AlphaISA +eventq_index=0 [system.cpu1.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -292,19 +318,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -312,28 +341,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -347,6 +381,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -369,6 +404,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -378,6 +414,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -400,6 +437,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -407,6 +445,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -418,6 +457,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -433,51 +473,34 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -486,6 +509,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -496,6 +520,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -504,6 +529,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -514,6 +540,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -542,6 +569,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -551,8 +579,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -569,6 +629,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -592,6 +653,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -609,6 +671,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -626,6 +689,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -643,6 +707,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -660,6 +725,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -677,6 +743,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -694,6 +761,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -711,6 +779,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -728,6 +797,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -745,6 +815,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -762,6 +833,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -779,6 +851,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -796,6 +869,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -813,6 +887,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -830,6 +905,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -847,6 +923,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -864,6 +941,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -881,6 +959,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -898,6 +977,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -916,6 +996,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -943,6 +1024,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -952,8 +1034,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -965,6 +1079,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -979,6 +1094,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -991,6 +1107,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -1001,6 +1118,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -1011,6 +1129,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1020,5 +1139,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 447e2a06f..e7342cf46 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2234616 # Simulator instruction rate (inst/s) -host_op_rate 2234615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66179117761 # Simulator tick rate (ticks/s) -host_mem_usage 308940 # Number of bytes of host memory used -host_seconds 28.26 # Real time elapsed on the host +host_inst_rate 1806360 # Simulator instruction rate (inst/s) +host_op_rate 1806359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53496127424 # Simulator tick rate (ticks/s) +host_mem_usage 353980 # Number of bytes of host memory used +host_seconds 34.96 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory @@ -267,7 +267,7 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.numCycles 3740671046 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 57222076 # Number of instructions committed @@ -285,8 +285,8 @@ system.cpu0.num_fp_register_writes 150835 # nu system.cpu0.num_mem_refs 15135515 # number of memory refs system.cpu0.num_load_insts 9184477 # Number of load instructions system.cpu0.num_store_insts 5951038 # Number of store instructions -system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles -system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles +system.cpu0.num_idle_cycles 3683437200.584730 # Number of idle cycles +system.cpu0.num_busy_cycles 57233845.415270 # Number of busy cycles system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index ac72e998f..7f56b644f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -60,6 +65,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -93,6 +99,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -115,11 +122,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -128,6 +137,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -150,17 +160,21 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -169,6 +183,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -191,12 +206,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -206,10 +223,12 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -217,19 +236,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -237,28 +259,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -272,6 +299,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -294,6 +322,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -301,6 +330,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -312,6 +342,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -327,51 +358,34 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -380,6 +394,7 @@ port=3456 [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -388,6 +403,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -398,6 +414,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -426,6 +443,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -435,8 +453,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -453,6 +503,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -476,6 +527,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -493,6 +545,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -510,6 +563,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -527,6 +581,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -544,6 +599,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -561,6 +617,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -578,6 +635,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -595,6 +653,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -612,6 +671,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -629,6 +689,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -646,6 +707,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -663,6 +725,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -680,6 +743,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -697,6 +761,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -714,6 +779,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -731,6 +797,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -748,6 +815,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -765,6 +833,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -782,6 +851,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -800,6 +870,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -827,6 +898,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -836,8 +908,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -849,6 +953,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -863,6 +968,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -875,6 +981,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -885,6 +992,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -895,6 +1003,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -904,5 +1013,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 066f6fce7..01a06923f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1630624 # Simulator instruction rate (inst/s) -host_op_rate 1630623 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49684114233 # Simulator tick rate (ticks/s) -host_mem_usage 305868 # Number of bytes of host memory used -host_seconds 36.82 # Real time elapsed on the host +host_inst_rate 1538182 # Simulator instruction rate (inst/s) +host_op_rate 1538181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46867449524 # Simulator tick rate (ticks/s) +host_mem_usage 350908 # Number of bytes of host memory used +host_seconds 39.03 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory @@ -129,7 +129,7 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.numCycles 3658664517 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60038305 # Number of instructions committed @@ -147,8 +147,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115709 # number of memory refs system.cpu.num_load_insts 9747513 # Number of load instructions system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles -system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles +system.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles +system.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983585 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 4764f4e77..c1c2c449d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -13,15 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/m5/system/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console +eventq_index=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -39,6 +42,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 @@ -48,6 +52,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -60,6 +65,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -86,6 +92,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -108,11 +115,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu0.icache] @@ -121,6 +130,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -143,21 +153,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu0.isa] type=AlphaISA +eventq_index=0 [system.cpu0.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -169,6 +184,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts @@ -195,6 +211,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -217,11 +234,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu1.icache] @@ -230,6 +249,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -252,25 +272,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu1.isa] type=AlphaISA +eventq_index=0 [system.cpu1.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.disk0] @@ -278,19 +304,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk0.image [system.disk0.image] type=CowDiskImage children=child child=system.disk0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -298,28 +327,33 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.disk2.image [system.disk2.image] type=CowDiskImage children=child child=system.disk2.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -333,6 +367,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -355,6 +390,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -364,6 +400,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -386,6 +423,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -393,6 +431,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -404,6 +443,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -430,6 +470,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -441,29 +482,35 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[1] [system.simple_disk] type=SimpleDisk children=disk disk=system.simple_disk.disk +eventq_index=0 system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -472,6 +519,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -482,6 +530,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +eventq_index=0 intrctrl=system.intrctrl system=system @@ -490,6 +539,7 @@ type=AlphaBackdoor clk_domain=system.clk_domain cpu=system.cpu0 disk=system.simple_disk +eventq_index=0 pio_addr=8804682956800 pio_latency=100000 platform=system.tsunami @@ -500,6 +550,7 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8803072344064 pio_latency=100000 system=system @@ -528,6 +579,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=2 Command=0 @@ -537,8 +589,40 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=52 MinimumGrant=176 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=0 Revision=0 Status=656 @@ -555,6 +639,7 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 +eventq_index=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 pci_bus=0 @@ -578,6 +663,7 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8796093677568 pio_latency=100000 @@ -595,6 +681,7 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848432 pio_latency=100000 @@ -612,6 +699,7 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848304 pio_latency=100000 @@ -629,6 +717,7 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848569 pio_latency=100000 @@ -646,6 +735,7 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848451 pio_latency=100000 @@ -663,6 +753,7 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848515 pio_latency=100000 @@ -680,6 +771,7 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848579 pio_latency=100000 @@ -697,6 +789,7 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848643 pio_latency=100000 @@ -714,6 +807,7 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848707 pio_latency=100000 @@ -731,6 +825,7 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848771 pio_latency=100000 @@ -748,6 +843,7 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848835 pio_latency=100000 @@ -765,6 +861,7 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848899 pio_latency=100000 @@ -782,6 +879,7 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615850617 pio_latency=100000 @@ -799,6 +897,7 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848891 pio_latency=100000 @@ -816,6 +915,7 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848816 pio_latency=100000 @@ -833,6 +933,7 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848696 pio_latency=100000 @@ -850,6 +951,7 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848936 pio_latency=100000 @@ -867,6 +969,7 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848680 pio_latency=100000 @@ -884,6 +987,7 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=8804615848944 pio_latency=100000 @@ -902,6 +1006,7 @@ pio=system.iobus.master[6] type=BadDevice clk_domain=system.clk_domain devicename=FrameBuffer +eventq_index=0 pio_addr=8804615848912 pio_latency=100000 system=system @@ -929,6 +1034,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -938,8 +1044,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -951,6 +1089,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=0 @@ -965,6 +1104,7 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO clk_domain=system.clk_domain +eventq_index=0 frequency=976562500 pio_addr=8804615847936 pio_latency=100000 @@ -977,6 +1117,7 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +eventq_index=0 pio_addr=8802535473152 pio_latency=100000 system=system @@ -987,6 +1128,7 @@ pio=system.iobus.master[1] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.tsunami @@ -997,6 +1139,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain +eventq_index=0 pio_addr=8804615848952 pio_latency=100000 platform=system.tsunami @@ -1006,5 +1149,6 @@ pio=system.iobus.master[23] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 676e01409..8b5007cf5 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.961837 # Number of seconds simulated -sim_ticks 1961837389000 # Number of ticks simulated -final_tick 1961837389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.960910 # Number of seconds simulated +sim_ticks 1960909874500 # Number of ticks simulated +final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1325125 # Simulator instruction rate (inst/s) -host_op_rate 1325124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42668778131 # Simulator tick rate (ticks/s) -host_mem_usage 308960 # Number of bytes of host memory used -host_seconds 45.98 # Real time elapsed on the host -sim_insts 60926932 # Number of instructions simulated -sim_ops 60926932 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 833280 # Number of bytes read from this memory +host_inst_rate 787846 # Simulator instruction rate (inst/s) +host_op_rate 787845 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25353578812 # Simulator tick rate (ticks/s) +host_mem_usage 353976 # Number of bytes of host memory used +host_seconds 77.34 # Real time elapsed on the host +sim_insts 60933947 # Number of instructions simulated +sim_ops 60933947 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 338432 # Number of bytes read from this memory -system.physmem.bytes_read::total 28741376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833280 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 338304 # Number of bytes read from this memory +system.physmem.bytes_read::total 28741248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833472 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7742464 # Number of bytes written to this memory -system.physmem.bytes_written::total 7742464 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13020 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::total 865152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7743680 # Number of bytes written to this memory +system.physmem.bytes_written::total 7743680 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13023 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5288 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449084 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120976 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120976 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12685610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 172508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14650234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424745 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16148 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3946537 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3946537 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3946537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424745 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12685610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 172508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18596771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449084 # Number of read requests accepted -system.physmem.writeReqs 120976 # Number of write requests accepted -system.physmem.readBursts 449084 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120976 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28737920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3456 # Total number of bytes read from write queue -system.physmem.bytesWritten 7741568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28741376 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7742464 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 54 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu1.data 5286 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449082 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120995 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120995 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12691610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 172524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14657098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16156 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3949024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3949024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3949024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12691610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 172524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18606122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449082 # Number of read requests accepted +system.physmem.writeReqs 120995 # Number of write requests accepted +system.physmem.readBursts 449082 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120995 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28737664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue +system.physmem.bytesWritten 7742592 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28741248 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7743680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7077 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 7094 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 28167 # Per bank write bursts -system.physmem.perBankRdBursts::1 28458 # Per bank write bursts -system.physmem.perBankRdBursts::2 28055 # Per bank write bursts -system.physmem.perBankRdBursts::3 27665 # Per bank write bursts +system.physmem.perBankRdBursts::1 28459 # Per bank write bursts +system.physmem.perBankRdBursts::2 28057 # Per bank write bursts +system.physmem.perBankRdBursts::3 27664 # Per bank write bursts system.physmem.perBankRdBursts::4 27762 # Per bank write bursts -system.physmem.perBankRdBursts::5 27792 # Per bank write bursts -system.physmem.perBankRdBursts::6 28261 # Per bank write bursts -system.physmem.perBankRdBursts::7 27879 # Per bank write bursts -system.physmem.perBankRdBursts::8 28077 # Per bank write bursts -system.physmem.perBankRdBursts::9 27735 # Per bank write bursts -system.physmem.perBankRdBursts::10 27671 # Per bank write bursts +system.physmem.perBankRdBursts::5 27793 # Per bank write bursts +system.physmem.perBankRdBursts::6 28259 # Per bank write bursts +system.physmem.perBankRdBursts::7 27872 # Per bank write bursts +system.physmem.perBankRdBursts::8 28083 # Per bank write bursts +system.physmem.perBankRdBursts::9 27730 # Per bank write bursts +system.physmem.perBankRdBursts::10 27672 # Per bank write bursts system.physmem.perBankRdBursts::11 28135 # Per bank write bursts -system.physmem.perBankRdBursts::12 28173 # Per bank write bursts +system.physmem.perBankRdBursts::12 28179 # Per bank write bursts system.physmem.perBankRdBursts::13 28505 # Per bank write bursts -system.physmem.perBankRdBursts::14 28655 # Per bank write bursts -system.physmem.perBankRdBursts::15 28040 # Per bank write bursts -system.physmem.perBankWrBursts::0 7931 # Per bank write bursts -system.physmem.perBankWrBursts::1 7869 # Per bank write bursts -system.physmem.perBankWrBursts::2 7539 # Per bank write bursts +system.physmem.perBankRdBursts::14 28654 # Per bank write bursts +system.physmem.perBankRdBursts::15 28035 # Per bank write bursts +system.physmem.perBankWrBursts::0 7928 # Per bank write bursts +system.physmem.perBankWrBursts::1 7868 # Per bank write bursts +system.physmem.perBankWrBursts::2 7543 # Per bank write bursts system.physmem.perBankWrBursts::3 7157 # Per bank write bursts system.physmem.perBankWrBursts::4 7275 # Per bank write bursts -system.physmem.perBankWrBursts::5 7313 # Per bank write bursts -system.physmem.perBankWrBursts::6 7748 # Per bank write bursts -system.physmem.perBankWrBursts::7 7258 # Per bank write bursts -system.physmem.perBankWrBursts::8 7316 # Per bank write bursts -system.physmem.perBankWrBursts::9 7114 # Per bank write bursts -system.physmem.perBankWrBursts::10 7078 # Per bank write bursts +system.physmem.perBankWrBursts::5 7314 # Per bank write bursts +system.physmem.perBankWrBursts::6 7747 # Per bank write bursts +system.physmem.perBankWrBursts::7 7251 # Per bank write bursts +system.physmem.perBankWrBursts::8 7322 # Per bank write bursts +system.physmem.perBankWrBursts::9 7110 # Per bank write bursts +system.physmem.perBankWrBursts::10 7099 # Per bank write bursts system.physmem.perBankWrBursts::11 7523 # Per bank write bursts -system.physmem.perBankWrBursts::12 7676 # Per bank write bursts +system.physmem.perBankWrBursts::12 7681 # Per bank write bursts system.physmem.perBankWrBursts::13 8141 # Per bank write bursts -system.physmem.perBankWrBursts::14 8336 # Per bank write bursts -system.physmem.perBankWrBursts::15 7688 # Per bank write bursts +system.physmem.perBankWrBursts::14 8335 # Per bank write bursts +system.physmem.perBankWrBursts::15 7684 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1961830378000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1960902862500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 449084 # Read request sizes (log2) +system.physmem.readPktSize::6 449082 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120976 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 409885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 977 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 960 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120995 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 409890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -141,444 +141,446 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 740.628604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 223.502021 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1737.958624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 17638 35.81% 35.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7255 14.73% 50.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4934 10.02% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2938 5.97% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1843 3.74% 70.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1471 2.99% 73.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1137 2.31% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 871 1.77% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 749 1.52% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 678 1.38% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 696 1.41% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 441 0.90% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 346 0.70% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 295 0.60% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 325 0.66% 84.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 366 0.74% 85.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 215 0.44% 85.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 196 0.40% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 200 0.41% 86.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 126 0.26% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 182 0.37% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 862 1.75% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 228 0.46% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 113 0.23% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 126 0.26% 89.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 100 0.20% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 86 0.17% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 47 0.10% 90.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 73 0.15% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 75 0.15% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 79 0.16% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 32 0.06% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 84 0.17% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 62 0.13% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 61 0.12% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 26 0.05% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 60 0.12% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 59 0.12% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 68 0.14% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 29 0.06% 91.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 67 0.14% 91.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 63 0.13% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 57 0.12% 92.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 25 0.05% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 61 0.12% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 59 0.12% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 69 0.14% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 25 0.05% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 65 0.13% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 58 0.12% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 65 0.13% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 25 0.05% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 59 0.12% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 71 0.14% 93.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 22 0.04% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 70 0.14% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 53 0.11% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 60 0.12% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 27 0.05% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 61 0.12% 93.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 53 0.11% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 63 0.13% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 34 0.07% 94.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 63 0.13% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 57 0.12% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 62 0.13% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 28 0.06% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 58 0.12% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 54 0.11% 94.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 66 0.13% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 361 0.73% 95.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 57 0.12% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 23 0.05% 95.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 53 0.11% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 23 0.05% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 58 0.12% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 23 0.05% 96.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 51 0.10% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 22 0.04% 96.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 54 0.11% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 39 0.08% 96.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 55 0.11% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 21 0.04% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 55 0.11% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 27 0.05% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 50 0.10% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 22 0.04% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 54 0.11% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 25 0.05% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 53 0.11% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 22 0.04% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 52 0.11% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 23 0.05% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 54 0.11% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 23 0.05% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 52 0.11% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 23 0.05% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 54 0.11% 97.97% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::stdev 1735.319745 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 17723 35.89% 35.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 7354 14.89% 50.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4892 9.91% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2955 5.98% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1860 3.77% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1462 2.96% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1143 2.31% 75.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 851 1.72% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 746 1.51% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 676 1.37% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 661 1.34% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 443 0.90% 82.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 337 0.68% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 276 0.56% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 300 0.61% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 399 0.81% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 192 0.39% 85.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 178 0.36% 85.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 196 0.40% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 170 0.34% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 202 0.41% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 873 1.77% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 184 0.37% 89.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 168 0.34% 89.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 96 0.19% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 82 0.17% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 107 0.22% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 72 0.15% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 81 0.16% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 51 0.10% 90.58% # Bytes accessed per row activation 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99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.41% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 40 0.08% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 179 0.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49252 # Bytes accessed per row activation -system.physmem.totQLat 6314810500 # Total ticks spent queuing -system.physmem.totMemAccLat 14686644250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2245150000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6126683750 # Total ticks spent accessing banks -system.physmem.avgQLat 14063.23 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13644.26 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 3 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 36 0.07% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 180 0.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49380 # Bytes accessed per row activation +system.physmem.totQLat 6346588750 # Total ticks spent queuing +system.physmem.totMemAccLat 14721193750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2245130000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6129475000 # Total ticks spent accessing banks +system.physmem.avgQLat 14134.12 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13650.60 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32707.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32784.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing -system.physmem.readRowHits 424855 # Number of row buffer hits during reads -system.physmem.writeRowHits 95885 # Number of row buffer hits during writes -system.physmem.readRowHitRate 94.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.26 # Row buffer hit rate for writes -system.physmem.avgGap 3441445.42 # Average gap between requests -system.physmem.pageHitRate 91.36 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 10.65 # Average write queue length when enqueuing +system.physmem.readRowHits 424775 # Number of row buffer hits during reads +system.physmem.writeRowHits 95849 # Number of row buffer hits during writes +system.physmem.readRowHitRate 94.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.22 # Row buffer hit rate for writes +system.physmem.avgGap 3439715.80 # Average gap between requests +system.physmem.pageHitRate 91.33 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18657286 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292799 # Transaction distribution -system.membus.trans_dist::ReadResp 292799 # Transaction distribution -system.membus.trans_dist::WriteReq 14111 # Transaction distribution -system.membus.trans_dist::WriteResp 14111 # Transaction distribution -system.membus.trans_dist::Writeback 120976 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16467 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11554 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7080 # Transaction distribution -system.membus.trans_dist::ReadExReq 164905 # Transaction distribution -system.membus.trans_dist::ReadExResp 164053 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930997 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 973617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1098283 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82306 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31175680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31257986 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36566146 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36566146 # Total data (bytes) -system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 43190000 # Layer occupancy (ticks) +system.membus.throughput 18666756 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292805 # Transaction distribution +system.membus.trans_dist::ReadResp 292805 # Transaction distribution +system.membus.trans_dist::WriteReq 14109 # Transaction distribution +system.membus.trans_dist::WriteResp 14109 # Transaction distribution +system.membus.trans_dist::Writeback 120995 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16488 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11559 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7097 # Transaction distribution +system.membus.trans_dist::ReadExReq 164894 # Transaction distribution +system.membus.trans_dist::ReadExResp 164048 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931055 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124663 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124663 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1098334 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82290 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31259250 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307968 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5307968 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36567218 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36567218 # Total data (bytes) +system.membus.snoop_data_through_bus 36608 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43251000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1566162500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1579578000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3824002662 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3830990646 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376301000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 342163 # number of replacements -system.l2c.tags.tagsinuse 65223.750612 # Cycle average of tags in use -system.l2c.tags.total_refs 2442870 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407350 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.996980 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8613125750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55316.946263 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4805.666179 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4897.139369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 159.783438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.215363 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.844070 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073329 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074724 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002438 # Average percentage of cache occupancy +system.l2c.tags.replacements 342160 # number of replacements +system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use +system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407347 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 5.997899 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8615385750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55312.026017 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4807.093964 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4897.564051 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 159.017352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 44.243921 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.843995 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073350 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.074731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995235 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 684304 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664415 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 317640 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 107160 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1773519 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 792069 # number of Writeback hits -system.l2c.Writeback_hits::total 792069 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 188 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 543 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits +system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 107430 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774057 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 791641 # number of Writeback hits +system.l2c.Writeback_hits::total 791641 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 180 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 539 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 719 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 129070 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43262 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172332 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 684304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 793485 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 317640 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 150422 # number of demand (read+write) hits -system.l2c.demand_hits::total 1945851 # number of demand (read+write) hits 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+system.iocache.overall_miss_latency::tsunami.ide 12987651947 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12987651947 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -754,19 +756,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 311722.704467 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 311722.704467 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 310932.037555 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 310932.037555 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 405757 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122121.454023 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122121.454023 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312052.435839 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 312052.435839 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 311260.411901 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 311260.411901 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 401197 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29467 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28980 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.769878 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.843927 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -780,14 +782,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41726 system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10790464816 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10790464816 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10802664199 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10802664199 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10802664199 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10802664199 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12200133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12200133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10804136814 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10804136814 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10816336947 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10816336947 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10816336947 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10816336947 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -796,14 +798,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 259685.810936 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 259685.810936 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -821,22 +823,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7530179 # DTB read hits -system.cpu0.dtb.read_misses 7765 # DTB read misses +system.cpu0.dtb.read_hits 7532654 # DTB read hits +system.cpu0.dtb.read_misses 7812 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5118893 # DTB write hits -system.cpu0.dtb.write_misses 910 # DTB write misses -system.cpu0.dtb.write_acv 133 # DTB write access violations -system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12649072 # DTB hits -system.cpu0.dtb.data_misses 8675 # DTB misses -system.cpu0.dtb.data_acv 343 # DTB access violations -system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3650586 # ITB hits -system.cpu0.itb.fetch_misses 3984 # ITB misses +system.cpu0.dtb.read_accesses 524694 # DTB read accesses +system.cpu0.dtb.write_hits 5120278 # DTB write hits +system.cpu0.dtb.write_misses 919 # DTB write misses +system.cpu0.dtb.write_acv 139 # DTB write access violations +system.cpu0.dtb.write_accesses 202960 # DTB write accesses +system.cpu0.dtb.data_hits 12652932 # DTB hits +system.cpu0.dtb.data_misses 8731 # DTB misses +system.cpu0.dtb.data_acv 349 # DTB access violations +system.cpu0.dtb.data_accesses 727654 # DTB accesses +system.cpu0.itb.fetch_hits 3655515 # ITB hits +system.cpu0.itb.fetch_misses 4023 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3654570 # ITB accesses +system.cpu0.itb.fetch_accesses 3659538 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -849,55 +851,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923674778 # number of cpu cycles simulated +system.cpu0.numCycles 3921819749 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47959136 # Number of instructions committed -system.cpu0.committedOps 47959136 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44491652 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211334 # Number of float alu accesses -system.cpu0.num_func_calls 1203195 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5632072 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44491652 # number of integer instructions -system.cpu0.num_fp_insts 211334 # number of float instructions -system.cpu0.num_int_register_reads 61191395 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33136181 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 103249 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 105046 # number of times the floating registers were written -system.cpu0.num_mem_refs 12690027 # number of memory refs -system.cpu0.num_load_insts 7557911 # Number of load instructions -system.cpu0.num_store_insts 5132116 # Number of store instructions -system.cpu0.num_idle_cycles 3700191977.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223482800.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.056958 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.943042 # Percentage of idle cycles +system.cpu0.committedInsts 47983654 # Number of instructions committed +system.cpu0.committedOps 47983654 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44515044 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211401 # Number of float alu accesses +system.cpu0.num_func_calls 1203620 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5635723 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44515044 # number of integer instructions +system.cpu0.num_fp_insts 211401 # number of float instructions +system.cpu0.num_int_register_reads 61226145 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33154260 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 103282 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 105080 # number of times the floating registers were written +system.cpu0.num_mem_refs 12694028 # number of memory refs +system.cpu0.num_load_insts 7560495 # Number of load instructions +system.cpu0.num_store_insts 5133533 # Number of store instructions +system.cpu0.num_idle_cycles 3698209766.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223609982.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057017 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942983 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6812 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165228 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56779 40.23% 40.23% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165343 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56789 40.24% 40.24% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1974 1.40% 41.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 42.03% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81809 57.97% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141128 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56269 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1973 1.40% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 42.04% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81806 57.96% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141134 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56279 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55834 48.70% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114643 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1902446374500 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95095000 0.00% 96.98% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 766988500 0.04% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 322426000 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58205747500 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961836631500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991018 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 55844 48.70% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114662 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1901501471500 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95150500 0.00% 96.98% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 767153500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 322241000 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58223100500 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1960909117000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991019 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682492 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812333 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682639 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812434 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -933,33 +935,33 @@ system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3084 2.06% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3090 2.07% 2.42% # number of callpals executed +system.cpu0.kern.callpal::tbi 52 0.03% 2.45% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134176 89.75% 92.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6701 4.48% 96.68% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134176 89.74% 92.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6700 4.48% 96.68% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.68% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rti 4411 2.95% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::rti 4418 2.95% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 396 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149500 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7010 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches +system.cpu0.kern.callpal::total 149515 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7023 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1378 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1372 -system.cpu0.kern.mode_good::user 1373 +system.cpu0.kern.mode_good::kernel 1377 +system.cpu0.kern.mode_good::user 1378 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195720 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.196070 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327448 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958037655500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3798971500 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327937 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1957102433500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3806679000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3085 # number of times the context was actually changed +system.cpu0.kern.swap_context 3091 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -991,47 +993,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 103908079 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2101783 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2101768 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14111 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14111 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 792069 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16689 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11613 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28302 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 338794 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297244 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1394675 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121086 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 636287 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 464415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5616463 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44628928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119461456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20361152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17008562 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 201460098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 201449794 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2400960 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4792055385 # Layer occupancy (ticks) +system.toL2Bus.throughput 103937669 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2101927 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101912 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14109 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14109 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 791641 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16698 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11618 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28316 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 338479 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296929 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1395511 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 635773 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 463473 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5616114 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44655680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119473096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20344704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16974250 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 201447730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201437426 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2374976 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4790041400 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3140628756 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3142512505 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5519397625 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5519878863 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1431747492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1430590492 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 796288703 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 794307231 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1398649 # Throughput (bytes/s) +system.iobus.throughput 1399302 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55663 # Transaction distribution -system.iobus.trans_dist::WriteResp 55663 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14010 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 55661 # Transaction distribution +system.iobus.trans_dist::WriteResp 55661 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1043,11 +1045,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42620 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42616 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126072 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 126068 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56024 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1059,12 +1061,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 82306 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 82290 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2743922 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2743922 # Total data (bytes) -system.iobus.reqLayer0.occupancy 13365000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2743906 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2743906 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13361000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1086,59 +1088,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377760199 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 377744447 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28509000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28507000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42664000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42681500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 696718 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.401211 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47270807 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 697230 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.798011 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40083254250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.401211 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992971 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992971 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 47270807 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47270807 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47270807 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47270807 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47270807 # number of overall hits -system.cpu0.icache.overall_hits::total 47270807 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 697348 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 697348 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 697348 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 697348 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 697348 # number of overall misses -system.cpu0.icache.overall_misses::total 697348 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9977651756 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9977651756 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9977651756 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9977651756 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9977651756 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9977651756 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47968155 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47968155 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47968155 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47968155 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47968155 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47968155 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014538 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014538 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014538 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014538 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014538 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014538 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14307.995084 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14307.995084 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14307.995084 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14307.995084 # average overall miss latency +system.cpu0.icache.tags.replacements 697136 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.398756 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47294969 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 697648 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.792023 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40091069250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47294969 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47294969 # number of overall hits +system.cpu0.icache.overall_hits::total 47294969 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 697766 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 697766 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 697766 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 697766 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 697766 # number of overall misses +system.cpu0.icache.overall_misses::total 697766 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9984385005 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9984385005 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9984385005 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9984385005 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9984385005 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9984385005 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47992735 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47992735 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47992735 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47992735 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47992735 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47992735 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014539 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014539 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014539 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014539 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014539 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014539 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14309.073536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14309.073536 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1147,112 +1149,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697348 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 697348 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 697348 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 697348 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 697348 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 697348 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8577830244 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8577830244 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8577830244 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8577830244 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8577830244 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8577830244 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014538 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014538 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014538 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12300.645078 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697766 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 697766 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 697766 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 697766 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 697766 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 697766 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8583721995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8583721995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8583721995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8583721995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8583721995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8583721995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12301.720054 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1186136 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.274988 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11457169 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1186648 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.655070 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 107469250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.274988 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986865 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986865 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6449366 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6449366 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4705451 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4705451 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140478 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140478 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147984 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 147984 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11154817 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11154817 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11154817 # number of overall hits -system.cpu0.dcache.overall_hits::total 11154817 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 939343 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 939343 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 256772 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 256772 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13639 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13639 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5591 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5591 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1196115 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1196115 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1196115 # number of overall misses -system.cpu0.dcache.overall_misses::total 1196115 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27074316502 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27074316502 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10448735954 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10448735954 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148878750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 148878750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43336419 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 43336419 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37523052456 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37523052456 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37523052456 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37523052456 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7388709 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7388709 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4962223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4962223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154117 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154117 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153575 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153575 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12350932 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12350932 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12350932 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12350932 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127132 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127132 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051745 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051745 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088498 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088498 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036406 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036406 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096844 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.096844 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096844 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.096844 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28822.609528 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28822.609528 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40692.661014 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40692.661014 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10915.664638 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10915.664638 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7751.103380 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7751.103380 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31370.773258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31370.773258 # average overall miss latency +system.cpu0.dcache.tags.replacements 1186229 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.271614 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11460994 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1186741 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.657536 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 107902250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.271614 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986859 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986859 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6451735 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6451735 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4706856 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4706856 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140512 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140512 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148003 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148003 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11158591 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11158591 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11158591 # number of overall hits +system.cpu0.dcache.overall_hits::total 11158591 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 939483 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 939483 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 256736 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 256736 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13633 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13633 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5600 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5600 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1196219 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1196219 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1196219 # number of overall misses +system.cpu0.dcache.overall_misses::total 1196219 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27076055500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27076055500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10459807694 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10459807694 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148332750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 148332750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43345419 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 43345419 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37535863194 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37535863194 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37535863194 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37535863194 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7391218 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7391218 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4963592 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4963592 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154145 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154145 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153603 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153603 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12354810 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12354810 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12354810 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12354810 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127108 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127108 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051724 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051724 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088443 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088443 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036458 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036458 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096822 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096822 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096822 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096822 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28820.165453 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28820.165453 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40741.492015 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40741.492015 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10880.418837 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10880.418837 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7740.253393 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7740.253393 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31378.755223 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31378.755223 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1261,62 +1263,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682430 # number of writebacks -system.cpu0.dcache.writebacks::total 682430 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939343 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939343 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256772 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 256772 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13639 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13639 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5590 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5590 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196115 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1196115 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196115 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1196115 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25063726498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25063726498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9880374046 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9880374046 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121588250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121588250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32154581 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32154581 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34944100544 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 34944100544 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34944100544 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 34944100544 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465575000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465575000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284904500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284904500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750479500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750479500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127132 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127132 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051745 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051745 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036399 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036399 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096844 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096844 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26682.187974 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26682.187974 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38479.172363 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38479.172363 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8914.748149 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8914.748149 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5752.161181 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5752.161181 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 682519 # number of writebacks +system.cpu0.dcache.writebacks::total 682519 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939483 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939483 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256736 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256736 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13633 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13633 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5600 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5600 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1196219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196219 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1196219 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25065202500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25065202500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9891526306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9891526306 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121052250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121052250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32145581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32145581 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34956728806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34956728806 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34956728806 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34956728806 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284723500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284723500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750325500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750325500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127108 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127108 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088443 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088443 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036458 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036458 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096822 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096822 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8879.355241 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8879.355241 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5740.282321 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5740.282321 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1328,22 +1334,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2385380 # DTB read hits +system.cpu1.dtb.read_hits 2383442 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1707840 # DTB write hits +system.cpu1.dtb.write_hits 1706844 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4093220 # DTB hits +system.cpu1.dtb.data_hits 4090286 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1814538 # ITB hits +system.cpu1.itb.fetch_hits 1814139 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1815602 # ITB accesses +system.cpu1.itb.fetch_accesses 1815203 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1356,51 +1362,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3921880904 # number of cpu cycles simulated +system.cpu1.numCycles 3919927793 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12967796 # Number of instructions committed -system.cpu1.committedOps 12967796 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11946960 # Number of integer alu accesses +system.cpu1.committedInsts 12950293 # Number of instructions committed +system.cpu1.committedOps 12950293 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11929999 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses -system.cpu1.num_func_calls 410982 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1284197 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11946960 # number of integer instructions +system.cpu1.num_func_calls 410658 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1281658 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11929999 # number of integer instructions system.cpu1.num_fp_insts 174217 # number of float instructions -system.cpu1.num_int_register_reads 16422187 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8787604 # number of times the integer registers were written +system.cpu1.num_int_register_reads 16394755 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8774296 # number of times the integer registers were written system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written -system.cpu1.num_mem_refs 4116157 # number of memory refs -system.cpu1.num_load_insts 2399132 # Number of load instructions -system.cpu1.num_store_insts 1717025 # Number of store instructions -system.cpu1.num_idle_cycles 3872385828.119347 # Number of idle cycles -system.cpu1.num_busy_cycles 49495075.880653 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012620 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987380 # Percentage of idle cycles +system.cpu1.num_mem_refs 4113222 # number of memory refs +system.cpu1.num_load_insts 2397194 # Number of load instructions +system.cpu1.num_store_insts 1716028 # Number of store instructions +system.cpu1.num_idle_cycles 3870487590.349789 # Number of idle cycles +system.cpu1.num_busy_cycles 49440202.650211 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2742 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78306 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26634 38.27% 38.27% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78268 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26619 38.27% 38.27% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40476 58.16% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69596 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25767 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 40454 58.16% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69559 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25752 48.16% 48.16% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25250 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53503 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909643308000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700945000 0.04% 97.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 361639500 0.02% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50234529500 2.56% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1960940422000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967448 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 25236 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53474 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1908686801000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700508000 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 362068000 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50214489500 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1959963866500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967429 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.623826 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.768765 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.623820 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.768757 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1419,78 +1425,78 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2001 2.78% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2001 2.79% 3.40% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63390 88.19% 91.60% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 2.99% 94.59% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63355 88.19% 91.60% # number of callpals executed +system.cpu1.kern.callpal::rdps 2145 2.99% 94.59% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::rti 3719 5.17% 99.77% # number of callpals executed +system.cpu1.kern.callpal::rti 3718 5.18% 99.77% # number of callpals executed system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71875 # number of callpals executed +system.cpu1.kern.callpal::total 71838 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2907 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2906 # number of protection mode switches system.cpu1.kern.mode_good::kernel 809 system.cpu1.kern.mode_good::user 368 system.cpu1.kern.mode_good::idle 441 system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.151703 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309310 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17986321500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1483696000 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1940592550000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.151755 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.309369 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17986814000 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1484472500 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1939632240000 99.01% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2002 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 317593 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.454785 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12652531 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318104 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.774825 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1959964216000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.454785 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871982 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871982 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 12652531 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12652531 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12652531 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12652531 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12652531 # number of overall hits -system.cpu1.icache.overall_hits::total 12652531 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318144 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318144 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318144 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318144 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318144 # number of overall misses -system.cpu1.icache.overall_misses::total 318144 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4187615492 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4187615492 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4187615492 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4187615492 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4187615492 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4187615492 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12970675 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12970675 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12970675 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12970675 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12970675 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12970675 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024528 # miss rate for ReadReq accesses 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+system.cpu1.dcache.overall_miss_latency::cpu1.data 2455506804 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2455506804 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2337373 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2337373 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1652172 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1652172 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57112 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57112 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56632 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56632 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3989545 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3989545 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3989545 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3989545 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049930 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049930 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034433 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034433 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159003 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159003 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106283 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106283 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043512 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043512 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043512 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043512 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12094.581163 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12094.581163 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18351.892352 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18351.892352 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9069.155379 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9069.155379 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7340.908290 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7340.908290 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14145.194818 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14145.194818 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1613,62 +1619,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 109639 # number of writebacks -system.cpu1.dcache.writebacks::total 109639 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116850 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 116850 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57159 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57159 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9086 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9086 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6023 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6023 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 174009 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 174009 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 174009 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 174009 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1177711751 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1177711751 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 928682973 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 928682973 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64347500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64347500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32228573 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32228573 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2106394724 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2106394724 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2106394724 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2106394724 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18769000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18769000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718428000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718428000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737197000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737197000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034576 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034576 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159069 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159069 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106338 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106338 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043584 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043584 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10078.833984 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10078.833984 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16247.362148 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16247.362148 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7082.049307 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7082.049307 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5350.916985 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5350.916985 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 109122 # number of writebacks +system.cpu1.dcache.writebacks::total 109122 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116704 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116704 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 56889 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 56889 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9081 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9081 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6019 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6019 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 173593 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 173593 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 173593 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 173593 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1178000000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1178000000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 927938196 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 927938196 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64195000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64195000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32145073 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32145073 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2105938196 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2105938196 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2105938196 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2105938196 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718207000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718207000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 736983000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 736983000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049930 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049930 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034433 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034433 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159003 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159003 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043512 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043512 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7069.155379 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7069.155379 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5340.600266 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5340.600266 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index b499d5442..db7088ff9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,18 +228,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=AtomicSimpleCPU @@ -234,6 +254,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -267,6 +288,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -289,18 +311,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -311,6 +336,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -333,14 +359,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -359,31 +388,37 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -396,6 +431,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -418,6 +454,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -427,6 +464,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -449,6 +487,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -456,6 +495,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -467,6 +507,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -482,41 +523,22 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -526,6 +548,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -535,6 +558,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -563,6 +587,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -572,8 +597,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -585,6 +642,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -600,6 +658,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -614,6 +674,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -623,6 +684,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -644,8 +706,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -654,6 +718,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -664,6 +729,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -674,6 +740,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -684,6 +751,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -698,6 +766,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -711,6 +780,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -728,6 +798,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -740,6 +811,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -751,6 +823,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -761,6 +834,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -773,6 +847,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -786,6 +861,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -796,6 +872,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -806,6 +883,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -816,6 +894,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -828,6 +907,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -842,6 +922,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -854,6 +935,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -868,6 +950,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -878,6 +961,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -888,6 +972,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -898,6 +983,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -906,6 +992,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -914,6 +1001,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -923,11 +1011,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index fb725ba91..622f0dad2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1640213 # Simulator instruction rate (inst/s) -host_op_rate 2111770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24275992963 # Simulator tick rate (ticks/s) -host_mem_usage 394600 # Number of bytes of host memory used -host_seconds 37.57 # Real time elapsed on the host +host_inst_rate 1031681 # Simulator instruction rate (inst/s) +host_op_rate 1328287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15269405009 # Simulator tick rate (ticks/s) +host_mem_usage 443324 # Number of bytes of host memory used +host_seconds 59.73 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -316,7 +316,7 @@ system.cpu0.itb.inst_accesses 30240979 # IT system.cpu0.itb.hits 30238804 # DTB hits system.cpu0.itb.misses 2175 # DTB misses system.cpu0.itb.accesses 30240979 # DTB accesses -system.cpu0.numCycles 1823633059 # number of cpu cycles simulated +system.cpu0.numCycles 1823671407 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 29750005 # Number of instructions committed @@ -334,8 +334,8 @@ system.cpu0.num_fp_register_writes 916 # nu system.cpu0.num_mem_refs 14626951 # number of memory refs system.cpu0.num_load_insts 8357226 # Number of load instructions system.cpu0.num_store_insts 6269725 # Number of store instructions -system.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles -system.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles +system.cpu0.num_idle_cycles 1784006336.868180 # Number of idle cycles +system.cpu0.num_busy_cycles 39665070.131821 # Number of busy cycles system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -492,7 +492,7 @@ system.cpu1.itb.inst_accesses 32414506 # IT system.cpu1.itb.hits 32412306 # DTB hits system.cpu1.itb.misses 2200 # DTB misses system.cpu1.itb.accesses 32414506 # DTB accesses -system.cpu1.numCycles 1824154149 # number of cpu cycles simulated +system.cpu1.numCycles 1824193528 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 31875965 # Number of instructions committed @@ -510,8 +510,8 @@ system.cpu1.num_fp_register_writes 1416 # nu system.cpu1.num_mem_refs 13370713 # number of memory refs system.cpu1.num_load_insts 7642673 # Number of load instructions system.cpu1.num_store_insts 5728040 # Number of store instructions -system.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles -system.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles +system.cpu1.num_idle_cycles 1783401357.733683 # Number of idle cycles +system.cpu1.num_busy_cycles 40792170.266317 # Number of busy cycles system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 4246eb19f..196c32809 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,12 +228,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -227,6 +246,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -249,12 +269,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -264,19 +286,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -289,6 +315,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -311,6 +338,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -318,6 +346,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -329,6 +358,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -344,41 +374,22 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -388,6 +399,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -397,6 +409,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -425,6 +438,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -434,8 +448,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -447,6 +493,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -462,6 +509,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -476,6 +525,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -485,6 +535,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -506,8 +557,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -516,6 +569,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -526,6 +580,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -536,6 +591,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -546,6 +602,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -560,6 +617,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -573,6 +631,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -590,6 +649,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -602,6 +662,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -613,6 +674,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -623,6 +685,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -635,6 +698,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -648,6 +712,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -658,6 +723,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -668,6 +734,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -678,6 +745,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -690,6 +758,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -704,6 +773,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -716,6 +786,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -730,6 +801,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -740,6 +812,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -750,6 +823,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -760,6 +834,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -768,6 +843,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -775,11 +851,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 503d37a74..cb6c51df2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1754227 # Simulator instruction rate (inst/s) -host_op_rate 2255827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67743178392 # Simulator tick rate (ticks/s) -host_mem_usage 394608 # Number of bytes of host memory used -host_seconds 34.44 # Real time elapsed on the host +host_inst_rate 993135 # Simulator instruction rate (inst/s) +host_op_rate 1277110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38352024586 # Simulator tick rate (ticks/s) +host_mem_usage 443324 # Number of bytes of host memory used +host_seconds 60.83 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -114,7 +114,7 @@ system.cpu.itb.inst_accesses 61436311 # IT system.cpu.itb.hits 61431840 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61436311 # DTB accesses -system.cpu.numCycles 4665543516 # number of cpu cycles simulated +system.cpu.numCycles 4665620529 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60408639 # Number of instructions committed @@ -132,8 +132,8 @@ system.cpu.num_fp_register_writes 2780 # nu system.cpu.num_mem_refs 27361637 # number of memory refs system.cpu.num_load_insts 15639527 # Number of load instructions system.cpu.num_store_insts 11722110 # Number of store instructions -system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles -system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles +system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles +system.cpu.num_busy_cycles 78798455.992855 # Number of busy cycles system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 6e5d183fa..051cf58a2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -112,6 +121,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -134,18 +144,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -156,6 +169,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -178,14 +192,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -204,18 +221,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -227,6 +247,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts @@ -253,6 +274,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -275,18 +297,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -297,6 +322,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -319,14 +345,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -345,31 +374,37 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -382,6 +417,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -404,6 +440,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -413,6 +450,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -435,6 +473,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -442,6 +481,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -453,6 +493,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -479,6 +520,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -490,19 +532,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -512,6 +558,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -521,6 +568,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -549,6 +597,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -558,8 +607,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -571,6 +652,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -586,6 +668,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -600,6 +684,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -609,6 +694,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -630,8 +716,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -640,6 +728,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -650,6 +739,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -660,6 +750,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -670,6 +761,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -684,6 +776,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -697,6 +790,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -714,6 +808,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -726,6 +821,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -737,6 +833,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -747,6 +844,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -759,6 +857,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -772,6 +871,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -782,6 +882,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -792,6 +893,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -802,6 +904,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -814,6 +917,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -828,6 +932,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -840,6 +945,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -854,6 +960,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -864,6 +971,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -874,6 +982,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -884,6 +993,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -892,6 +1002,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -900,6 +1011,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -909,11 +1021,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 951921c42..168e14479 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,150 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.195756 # Number of seconds simulated -sim_ticks 1195756323500 # Number of ticks simulated -final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.195792 # Number of seconds simulated +sim_ticks 1195791950500 # Number of ticks simulated +final_tick 1195791950500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 469394 # Simulator instruction rate (inst/s) -host_op_rate 598174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9145402965 # Simulator tick rate (ticks/s) -host_mem_usage 398732 # Number of bytes of host memory used -host_seconds 130.75 # Real time elapsed on the host -sim_insts 61373013 # Number of instructions simulated -sim_ops 78210923 # Number of ops (including micro ops) simulated +host_inst_rate 418462 # Simulator instruction rate (inst/s) +host_op_rate 533251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8153682245 # Simulator tick rate (ticks/s) +host_mem_usage 447424 # Number of bytes of host memory used +host_seconds 146.66 # Real time elapsed on the host +sim_insts 61370228 # Number of instructions simulated +sim_ops 78204808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626164 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory -system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 2903920 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155172 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136128 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163472 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103606 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 45400 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654629 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64627 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821463 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43405972 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 387790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5541235 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2428449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51978249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 387790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602218 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3458903 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2531631 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5990567 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3458903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43405972 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 387790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8072866 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654771 # Number of read requests accepted -system.physmem.writeReqs 821574 # Number of write requests accepted -system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415729 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 214429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2428483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57968816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654629 # Number of read requests accepted +system.physmem.writeReqs 821463 # Number of write requests accepted +system.physmem.readBursts 6654629 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821463 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425873472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7293184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62155172 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7163472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 356 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707504 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 10661 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415730 # Per bank write bursts system.physmem.perBankRdBursts::1 415559 # Per bank write bursts -system.physmem.perBankRdBursts::2 414962 # Per bank write bursts -system.physmem.perBankRdBursts::3 415336 # Per bank write bursts -system.physmem.perBankRdBursts::4 422370 # Per bank write bursts +system.physmem.perBankRdBursts::2 414961 # Per bank write bursts +system.physmem.perBankRdBursts::3 415335 # Per bank write bursts +system.physmem.perBankRdBursts::4 422368 # Per bank write bursts system.physmem.perBankRdBursts::5 415375 # Per bank write bursts -system.physmem.perBankRdBursts::6 415451 # Per bank write bursts +system.physmem.perBankRdBursts::6 415446 # Per bank write bursts system.physmem.perBankRdBursts::7 415289 # Per bank write bursts system.physmem.perBankRdBursts::8 415350 # Per bank write bursts system.physmem.perBankRdBursts::9 415631 # Per bank write bursts system.physmem.perBankRdBursts::10 415265 # Per bank write bursts system.physmem.perBankRdBursts::11 414898 # Per bank write bursts -system.physmem.perBankRdBursts::12 415464 # Per bank write bursts +system.physmem.perBankRdBursts::12 415491 # Per bank write bursts system.physmem.perBankRdBursts::13 416088 # Per bank write bursts -system.physmem.perBankRdBursts::14 415829 # Per bank write bursts -system.physmem.perBankRdBursts::15 415792 # Per bank write bursts -system.physmem.perBankWrBursts::0 7314 # Per bank write bursts -system.physmem.perBankWrBursts::1 7200 # Per bank write bursts -system.physmem.perBankWrBursts::2 6696 # Per bank write bursts -system.physmem.perBankWrBursts::3 6864 # Per bank write bursts -system.physmem.perBankWrBursts::4 7395 # Per bank write bursts -system.physmem.perBankWrBursts::5 6961 # Per bank write bursts -system.physmem.perBankWrBursts::6 7170 # Per bank write bursts -system.physmem.perBankWrBursts::7 6990 # Per bank write bursts -system.physmem.perBankWrBursts::8 6985 # Per bank write bursts -system.physmem.perBankWrBursts::9 7249 # Per bank write bursts +system.physmem.perBankRdBursts::14 415759 # Per bank write bursts +system.physmem.perBankRdBursts::15 415728 # Per bank write bursts +system.physmem.perBankWrBursts::0 7313 # Per bank write bursts +system.physmem.perBankWrBursts::1 7201 # Per bank write bursts +system.physmem.perBankWrBursts::2 6692 # Per bank write bursts +system.physmem.perBankWrBursts::3 6866 # Per bank write bursts +system.physmem.perBankWrBursts::4 7393 # Per bank write bursts +system.physmem.perBankWrBursts::5 6958 # Per bank write bursts +system.physmem.perBankWrBursts::6 7169 # Per bank write bursts +system.physmem.perBankWrBursts::7 6986 # Per bank write bursts +system.physmem.perBankWrBursts::8 6988 # Per bank write bursts +system.physmem.perBankWrBursts::9 7250 # Per bank write bursts system.physmem.perBankWrBursts::10 6972 # Per bank write bursts system.physmem.perBankWrBursts::11 6687 # Per bank write bursts -system.physmem.perBankWrBursts::12 7224 # Per bank write bursts -system.physmem.perBankWrBursts::13 7527 # Per bank write bursts -system.physmem.perBankWrBursts::14 7429 # Per bank write bursts -system.physmem.perBankWrBursts::15 7403 # Per bank write bursts +system.physmem.perBankWrBursts::12 7223 # Per bank write bursts +system.physmem.perBankWrBursts::13 7529 # Per bank write bursts +system.physmem.perBankWrBursts::14 7375 # Per bank write bursts +system.physmem.perBankWrBursts::15 7354 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1195751937000 # Total gap between requests +system.physmem.totGap 1195787534500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6825 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159882 # Read request sizes (log2) +system.physmem.readPktSize::6 159740 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64738 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64627 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 636769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 483388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 484627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1579502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1123930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1118197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1114450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -159,31 +159,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -191,423 +191,408 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 392.553072 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 26180 34.89% 34.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15268 20.35% 55.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3440 4.58% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2311 3.08% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1510 2.01% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1328 1.77% 66.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1040 1.39% 68.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1132 1.51% 69.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 816 1.09% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 593 0.79% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 586 0.78% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 709 0.94% 73.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 314 0.42% 73.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 269 0.36% 73.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 220 0.29% 74.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 291 0.39% 74.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 182 0.24% 74.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 143 0.19% 75.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 140 0.19% 75.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 157 0.21% 75.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2241 2.99% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 115 0.15% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 232 0.31% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 71 0.09% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 55 0.07% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 54 0.07% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 56 0.07% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 28 0.04% 79.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 107 0.14% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 143 0.19% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 11 0.01% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 15 0.02% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 43 0.06% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 9 0.01% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 16 0.02% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 18 0.02% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 98 0.13% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 8 0.01% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 10 0.01% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 12 0.02% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 9 0.01% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 5 0.01% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 168 0.22% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 11 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 9 0.01% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 4 0.01% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 161 0.21% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 6 0.01% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 16 0.02% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 2 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 6 0.01% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 30 0.04% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 86 0.11% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 3 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 188 0.25% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 22 0.03% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 27 0.04% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 207 0.28% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 1 0.00% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 13 0.02% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 90 0.12% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 76 0.10% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 12 0.02% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 206 0.27% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 11 0.01% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 30 0.04% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 2 0.00% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 144 0.19% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 2 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 86 0.11% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 18 0.02% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 5 0.01% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 166 0.22% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 24 0.03% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 69 0.09% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 161 0.21% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 26 0.03% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 70 0.09% 83.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 24 0.03% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 2 0.00% 83.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 167 0.22% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 10 0.01% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 21 0.03% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 83 0.11% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 148 0.20% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10311 1 0.00% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 31 0.04% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 9 0.01% 83.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10951 1 0.00% 83.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 75 0.10% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 96 0.13% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 79 0.11% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 29 0.04% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.28% # Bytes accessed per row activation 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Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 15301 20.41% 55.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3417 4.56% 59.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2337 3.12% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1552 2.07% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1311 1.75% 66.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1048 1.40% 68.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1133 1.51% 69.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 708 0.94% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 576 0.77% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 588 0.78% 72.13% # Bytes accessed per row activation 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8 0.01% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 6 0.01% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 197 0.26% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 10 0.01% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 14 0.02% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 80 0.11% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 4 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 14 0.02% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 33 0.04% 81.42% # Bytes accessed per row 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1 0.00% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 108 0.14% 82.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 1 0.00% 82.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 32 0.04% 82.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 132 0.18% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 28 0.04% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 74 0.10% 82.96% # Bytes accessed per row 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+system.physmem.bytesPerActivate::22272-22279 9 0.01% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 89 0.12% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22592-22599 2 0.00% 88.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22791 71 0.09% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 103 0.14% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 16 0.02% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23360-23367 1 0.00% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 26 0.03% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 131 0.17% 88.61% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::26112-26119 98 0.13% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26247 1 0.00% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26311 2 0.00% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26375 75 0.10% 89.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26560-26567 1 0.00% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 84 0.11% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 13 0.02% 89.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 81 0.11% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 23 0.03% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 143 0.19% 89.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27840-27847 1 0.00% 89.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 9 0.01% 89.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28032-28039 1 0.00% 89.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 25 0.03% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 80 0.11% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28544-28551 3 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28615 1 0.00% 90.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 176 0.23% 90.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28743 1 0.00% 90.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 40 0.05% 90.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 16 0.02% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 72 0.10% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29639 1 0.00% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 167 0.22% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29760-29767 1 0.00% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29959 13 0.02% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30215 6 0.01% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30279 2 0.00% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 29 0.04% 90.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 150 0.20% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30855 1 0.00% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 84 0.11% 91.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 19 0.03% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 30 0.04% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 220 0.29% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32007 20 0.03% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 17 0.02% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 10 0.01% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 269 0.36% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 14 0.02% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 1 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 25 0.03% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 2 0.00% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 22 0.03% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 216 0.29% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 26 0.03% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34176-34183 1 0.00% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 19 0.03% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 84 0.11% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 2 0.00% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 148 0.20% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34880-34887 1 0.00% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 27 0.04% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35328-35335 6 0.01% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35591 13 0.02% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35776-35783 1 0.00% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 165 0.22% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35904-35911 1 0.00% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 71 0.09% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 14 0.02% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36480-36487 1 0.00% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 37 0.05% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36800-36807 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 169 0.23% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36928-36935 1 0.00% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36992-36999 2 0.00% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 79 0.11% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 25 0.03% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 9 0.01% 93.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 142 0.19% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 22 0.03% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 79 0.11% 93.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 11 0.01% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 85 0.11% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 73 0.10% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 2 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 96 0.13% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 14 0.02% 94.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 27 0.04% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 131 0.17% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40320-40327 1 0.00% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 24 0.03% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40512-40519 1 0.00% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 75 0.10% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40768-40775 1 0.00% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 23 0.03% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 72 0.10% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 1 0.00% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 24 0.03% 94.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 130 0.17% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 25 0.03% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 15 0.02% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 101 0.13% 94.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 70 0.09% 95.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 85 0.11% 95.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 8 0.01% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 78 0.10% 95.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 24 0.03% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 140 0.19% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 23 0.03% 95.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 80 0.11% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 2 0.00% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 165 0.22% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 38 0.05% 95.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 12 0.02% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 71 0.09% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 165 0.22% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 15 0.02% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 12 0.02% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 1 0.00% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 31 0.04% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 151 0.20% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 87 0.12% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 21 0.03% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 24 0.03% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 239 0.32% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 36 0.05% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 14 0.02% 97.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 17 0.02% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 9 0.01% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 6 0.01% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation -system.physmem.totQLat 159590177750 # Total ticks spent queuing -system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks -system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2125 2.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74963 # Bytes accessed per row activation +system.physmem.totQLat 159518930750 # Total ticks spent queuing +system.physmem.totMemAccLat 202571234500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33271365000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9780938750 # Total ticks spent accessing banks +system.physmem.avgQLat 23972.41 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1469.87 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30442.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing -system.physmem.readRowHits 6598517 # Number of row buffer hits during reads -system.physmem.writeRowHits 94894 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.12 # Average write queue length when enqueuing +system.physmem.readRowHits 6598430 # Number of row buffer hits during reads +system.physmem.writeRowHits 94836 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes -system.physmem.avgGap 159938.04 # Average gap between requests +system.physmem.writeRowHitRate 83.22 # Row buffer hit rate for writes +system.physmem.avgGap 159948.21 # Average gap between requests system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 4.87 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -626,286 +611,286 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 59999152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703168 # Transaction distribution -system.membus.trans_dist::ReadResp 7703168 # Transaction distribution +system.membus.throughput 59983824 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703157 # Transaction distribution +system.membus.trans_dist::ReadResp 7703157 # Transaction distribution system.membus.trans_dist::WriteReq 767205 # Transaction distribution system.membus.trans_dist::WriteResp 767205 # Transaction distribution -system.membus.trans_dist::Writeback 64738 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27605 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16481 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10656 # Transaction distribution -system.membus.trans_dist::ReadExReq 137900 # Transaction distribution -system.membus.trans_dist::ReadExResp 137428 # Transaction distribution +system.membus.trans_dist::Writeback 64627 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27746 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16446 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10661 # Transaction distribution +system.membus.trans_dist::ReadExReq 137744 # Transaction distribution +system.membus.trans_dist::ReadExResp 137297 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4359426 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359117 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335554 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17335245 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17430324 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19839854 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19823662 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71744366 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71744366 # Total data (bytes) +system.membus.tot_pkt_size::total 71728174 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71728174 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1219669500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224786000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7974500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7986500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 782000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9159249500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9213145499 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5040906450 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5079077969 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657427498 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657796999 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 69764 # number of replacements -system.l2c.tags.tagsinuse 53155.979727 # Cycle average of tags in use -system.l2c.tags.total_refs 1654767 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134953 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.261802 # Average number of references to valid blocks. +system.l2c.tags.replacements 69622 # number of replacements +system.l2c.tags.tagsinuse 53154.714662 # Cycle average of tags in use +system.l2c.tags.total_refs 1651251 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134786 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.250909 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40044.748185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40043.388352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667642 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4637.745622 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5787.407955 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4637.694613 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5787.547519 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1927.694562 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 755.712463 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.611034 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 1927.667021 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 755.746308 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.611014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.088309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.088311 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011531 # Average percentage of cache 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hits -system.l2c.UpgradeReq_hits::total 1741 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 268 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 366 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65622 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 45295 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110917 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4686 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1510 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 483170 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 307663 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3562 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1809 # number of demand (read+write) hits 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average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66057.804233 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61604.186027 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.547900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.172281 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.948784 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.574742 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.874739 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.685121 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56045.714220 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64546.202494 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58758.594590 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56666.917644 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64607.662938 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59152.393857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56666.917644 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64607.662938 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59152.393857 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1087,56 +1072,56 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118413539 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution +system.toL2Bus.throughput 118330469 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2505274 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2505274 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137274438 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 576138 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27005 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16807 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43812 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262415 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262415 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993978 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5841 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753985 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879812 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 12022 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7617898 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31385016 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53721240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5780 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24096780 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27936146 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7468 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15168 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 137185718 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137185718 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4312904 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4765712727 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2217854478 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2469983321 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10396000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1698669462 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2208533441 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8230499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45405912 # Throughput (bytes/s) +system.iobus.throughput 45404559 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution @@ -1246,13 +1231,13 @@ system.iobus.reqLayer25.occupancy 6488064000 # La system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17777853001 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9652613 # DTB read hits -system.cpu0.dtb.read_misses 3746 # DTB read misses -system.cpu0.dtb.write_hits 7596890 # DTB write hits +system.cpu0.dtb.read_hits 9652640 # DTB read hits +system.cpu0.dtb.read_misses 3742 # DTB read misses +system.cpu0.dtb.write_hits 7596858 # DTB write hits system.cpu0.dtb.write_misses 1582 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -1260,16 +1245,16 @@ system.cpu0.dtb.flush_tlb_mva_asid 1439 # Nu system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9656359 # DTB read accesses -system.cpu0.dtb.write_accesses 7598472 # DTB write accesses +system.cpu0.dtb.read_accesses 9656382 # DTB read accesses +system.cpu0.dtb.write_accesses 7598440 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17249503 # DTB hits -system.cpu0.dtb.misses 5328 # DTB misses -system.cpu0.dtb.accesses 17254831 # DTB accesses -system.cpu0.itb.inst_hits 43298526 # ITB inst hits +system.cpu0.dtb.hits 17249498 # DTB hits +system.cpu0.dtb.misses 5324 # DTB misses +system.cpu0.dtb.accesses 17254822 # DTB accesses +system.cpu0.itb.inst_hits 43298691 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1286,79 +1271,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43300731 # ITB inst accesses -system.cpu0.itb.hits 43298526 # DTB hits +system.cpu0.itb.inst_accesses 43300896 # ITB inst accesses +system.cpu0.itb.hits 43298691 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43300731 # DTB accesses -system.cpu0.numCycles 2391512647 # number of cpu cycles simulated +system.cpu0.itb.accesses 43300896 # DTB accesses +system.cpu0.numCycles 2391583901 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42571581 # Number of instructions committed -system.cpu0.committedOps 53301862 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48058821 # Number of integer alu accesses +system.cpu0.committedInsts 42571767 # Number of instructions committed +system.cpu0.committedOps 53302041 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48059042 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403638 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582830 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48058821 # number of integer instructions +system.cpu0.num_func_calls 1403630 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582817 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48059042 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272440712 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52270303 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272441604 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52270515 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written system.cpu0.num_mem_refs 18019009 # number of memory refs -system.cpu0.num_load_insts 10036459 # Number of load instructions -system.cpu0.num_store_insts 7982550 # Number of store instructions -system.cpu0.num_idle_cycles 2151176097.904201 # Number of idle cycles -system.cpu0.num_busy_cycles 240336549.095799 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100496 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899504 # Percentage of idle cycles +system.cpu0.num_load_insts 10036503 # Number of load instructions +system.cpu0.num_store_insts 7982506 # Number of store instructions +system.cpu0.num_idle_cycles 2151142905.888201 # Number of idle cycles +system.cpu0.num_busy_cycles 240440995.111799 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100536 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899464 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51331 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 490259 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.365280 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42807737 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 490771 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 87.225482 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76178400000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.365280 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994854 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994854 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42807737 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42807737 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42807737 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42807737 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42807737 # number of overall hits -system.cpu0.icache.overall_hits::total 42807737 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490772 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490772 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490772 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490772 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490772 # 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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5497.898371 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26815.399057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26815.399057 # average overall miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.656866 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921205 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.921205 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9136610 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9136610 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6494353 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6494353 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156522 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156522 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158977 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 158977 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 15630963 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 15630963 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 15630963 # number of overall hits +system.cpu0.dcache.overall_hits::total 15630963 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 263803 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 263803 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 176623 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 176623 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9911 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9911 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7399 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7399 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 440426 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 440426 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 440426 # number of overall misses +system.cpu0.dcache.overall_misses::total 440426 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3917573248 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3917573248 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7906184046 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7906184046 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99581999 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 99581999 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40689888 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 40689888 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11823757294 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11823757294 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11823757294 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11823757294 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400413 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9400413 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6670976 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6670976 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166433 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166433 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166376 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166376 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16071389 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16071389 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16071389 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16071389 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028063 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028063 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026476 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026476 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059549 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059549 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044472 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044472 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027404 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027404 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027404 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027404 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14850.374135 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.374135 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44763.049240 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44763.049240 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10047.623751 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10047.623751 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5499.376673 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5499.376673 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26846.183681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26846.183681 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1489,66 +1474,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376552 # number of writebacks -system.cpu0.dcache.writebacks::total 376552 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 264039 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 264039 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176698 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176698 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7424 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7424 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 440737 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 440737 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 440737 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 440737 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3395057254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3395057254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7495344212 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7495344212 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78904750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78904750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25999113 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25999113 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 376546 # number of writebacks +system.cpu0.dcache.writebacks::total 376546 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263803 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 263803 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176623 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176623 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9911 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9911 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7395 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7395 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440426 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440426 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440426 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440426 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3387671752 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3387671752 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7508595954 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7508595954 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79710001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79710001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25901112 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25901112 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10896267706 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10896267706 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10896267706 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10896267706 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765830000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765830000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807312360 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807312360 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39573142360 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39573142360 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026476 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026476 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059549 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059549 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044448 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044448 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027404 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027404 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.672581 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.672581 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42511.994214 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42511.994214 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8042.579054 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8042.579054 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.516836 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.516836 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1558,26 +1543,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5708064 # DTB read hits -system.cpu1.dtb.read_misses 3582 # DTB read misses -system.cpu1.dtb.write_hits 3874465 # DTB write hits -system.cpu1.dtb.write_misses 647 # DTB write misses +system.cpu1.dtb.read_hits 5706417 # DTB read hits +system.cpu1.dtb.read_misses 3586 # DTB read misses +system.cpu1.dtb.write_hits 3873093 # DTB write hits +system.cpu1.dtb.write_misses 644 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5711646 # DTB read accesses -system.cpu1.dtb.write_accesses 3875112 # DTB write accesses +system.cpu1.dtb.read_accesses 5710003 # DTB read accesses +system.cpu1.dtb.write_accesses 3873737 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9582529 # DTB hits -system.cpu1.dtb.misses 4229 # DTB misses -system.cpu1.dtb.accesses 9586758 # DTB accesses -system.cpu1.itb.inst_hits 19382020 # ITB inst hits +system.cpu1.dtb.hits 9579510 # DTB hits +system.cpu1.dtb.misses 4230 # DTB misses +system.cpu1.dtb.accesses 9583740 # DTB accesses +system.cpu1.itb.inst_hits 19379017 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1594,79 +1579,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses -system.cpu1.itb.hits 19382020 # DTB hits +system.cpu1.itb.inst_accesses 19381188 # ITB inst accesses +system.cpu1.itb.hits 19379017 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19384191 # DTB accesses -system.cpu1.numCycles 2390063941 # number of cpu cycles simulated +system.cpu1.itb.accesses 19381188 # DTB accesses +system.cpu1.numCycles 2390136116 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18801432 # Number of instructions committed -system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses +system.cpu1.committedInsts 18798461 # Number of instructions committed +system.cpu1.committedOps 24902767 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22266699 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796781 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22272671 # number of integer instructions +system.cpu1.num_func_calls 796691 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514546 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22266699 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130767489 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23318960 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10017952 # number of memory refs -system.cpu1.num_load_insts 5984754 # Number of load instructions -system.cpu1.num_store_insts 4033198 # Number of store instructions -system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles -system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles -system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles +system.cpu1.num_mem_refs 10014870 # number of memory refs +system.cpu1.num_load_insts 5983067 # Number of load instructions +system.cpu1.num_store_insts 4031803 # Number of store instructions +system.cpu1.num_idle_cycles 1969216562.004314 # Number of idle cycles +system.cpu1.num_busy_cycles 420919553.995686 # Number of busy cycles +system.cpu1.not_idle_fraction 0.176107 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.823893 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 376793 # number of replacements -system.cpu1.icache.tags.tagsinuse 474.907040 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.907040 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19004711 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19004711 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19004711 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19004711 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19004711 # number of overall hits -system.cpu1.icache.overall_hits::total 19004711 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377305 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377305 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377305 # number of overall misses -system.cpu1.icache.overall_misses::total 377305 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5159789711 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19382016 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19382016 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency +system.cpu1.kern.inst.quiesce 39069 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376769 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.890792 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19001732 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377281 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.364932 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327211938000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.890792 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927521 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927521 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19001732 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19001732 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19001732 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19001732 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19001732 # number of overall hits +system.cpu1.icache.overall_hits::total 19001732 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377281 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377281 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377281 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377281 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377281 # number of overall misses +system.cpu1.icache.overall_misses::total 377281 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5163865212 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5163865212 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5163865212 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5163865212 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5163865212 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5163865212 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19379013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19379013 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19379013 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19379013 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19379013 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019469 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019469 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019469 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019469 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019469 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019469 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13687.053448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13687.053448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13687.053448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13687.053448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1675,120 +1660,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377305 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377305 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377305 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377305 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377305 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377305 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4403600289 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4403600289 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4403600289 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4403600289 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4403600289 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4403600289 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6432750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6432750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6432750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6432750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019467 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019467 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019467 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.195158 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377281 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377281 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377281 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377281 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 377281 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 377281 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4407732788 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4407732788 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4407732788 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4407732788 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4407732788 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4407732788 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6483750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6483750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6483750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6483750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019469 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019469 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019469 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11682.890970 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 220883 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.477381 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8233318 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 221230 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.216101 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106377423000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.477381 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920854 # Average percentage of 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# average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24304.302372 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24304.302372 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24304.302372 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24304.302372 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1797,66 +1782,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed 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+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1380025261 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1380025261 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4109897774 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4109897774 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 57992002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 57992002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30524522 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30524522 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5489923035 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5489923035 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5489923035 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5489923035 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387761500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387761500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531061000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531061000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918822500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918822500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029582 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029582 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029793 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029793 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117200 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117200 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113254 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113254 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029678 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029678 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029678 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029678 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10313.858890 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10313.858890 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36436.233003 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36436.233003 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5946.677810 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5946.677810 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3242.115985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3242.115985 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1878,10 +1863,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651879453001 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651879453001 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651879453001 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651879453001 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 01d95ba19..925b86307 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -112,6 +121,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -134,18 +144,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -156,6 +169,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -178,14 +192,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -204,12 +221,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -220,6 +239,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -242,12 +262,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -257,19 +279,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -282,6 +308,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -304,6 +331,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -311,6 +339,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -322,6 +351,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -348,6 +378,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -359,19 +390,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -381,6 +416,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -390,6 +426,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -418,6 +455,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -427,8 +465,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -440,6 +510,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -455,6 +526,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -469,6 +542,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -478,6 +552,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -499,8 +574,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -509,6 +586,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -519,6 +597,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -529,6 +608,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -539,6 +619,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -553,6 +634,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -566,6 +648,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -583,6 +666,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -595,6 +679,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -606,6 +691,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -616,6 +702,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -628,6 +715,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -641,6 +729,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -651,6 +740,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -661,6 +751,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -671,6 +762,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -683,6 +775,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -697,6 +790,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -709,6 +803,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -723,6 +818,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -733,6 +829,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -743,6 +840,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -753,6 +851,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -761,6 +860,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -768,11 +868,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 50a428e90..df8a2beae 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.616536 # Nu sim_ticks 2616536483000 # Number of ticks simulated final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 552343 # Simulator instruction rate (inst/s) -host_op_rate 702879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24008008080 # Simulator tick rate (ticks/s) -host_mem_usage 395660 # Number of bytes of host memory used -host_seconds 108.99 # Real time elapsed on the host +host_inst_rate 343075 # Simulator instruction rate (inst/s) +host_op_rate 436578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14912044248 # Simulator tick rate (ticks/s) +host_mem_usage 444348 # Number of bytes of host memory used +host_seconds 175.46 # Real time elapsed on the host sim_insts 60197580 # Number of instructions simulated sim_ops 76603973 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory @@ -110,23 +110,23 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 57909 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1265330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1118297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1122310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3740106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2667387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2661184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2667924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 52364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 54482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20747 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1246989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1099674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1103822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2684241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2677986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2686359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 54486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 161 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -174,461 +174,452 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11127.069087 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1028.273701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16706.873806 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23194 25.85% 25.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14559 16.23% 42.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2860 3.19% 45.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2118 2.36% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1356 1.51% 49.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1216 1.36% 50.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 947 1.06% 51.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1180 1.32% 52.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 650 0.72% 53.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 587 0.65% 54.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 521 0.58% 54.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 703 0.78% 55.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 336 0.37% 55.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 268 0.30% 56.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 216 0.24% 56.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 509 0.57% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 151 0.17% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 159 0.18% 57.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 138 0.15% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 229 0.26% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 246 0.27% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 69 0.08% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 53 0.06% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 188 0.21% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 32 0.04% 61.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 26 0.03% 61.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 180 0.20% 61.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 16 0.02% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 28 0.03% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 12 0.01% 61.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 150 0.17% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 27 0.03% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 112 0.12% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 11 0.01% 62.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 62.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 157 0.17% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 16 0.02% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 359 0.40% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 18 0.02% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 100 0.11% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 18 0.02% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 89 0.10% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 18 0.02% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 147 0.16% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 89677 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11133.273058 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1028.792401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16712.114180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23203 25.87% 25.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14561 16.24% 42.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2861 3.19% 45.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2042 2.28% 47.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1356 1.51% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1217 1.36% 50.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 956 1.07% 51.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1130 1.26% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 649 0.72% 53.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 589 0.66% 54.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 514 0.57% 54.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 694 0.77% 55.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 336 0.37% 55.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 266 0.30% 56.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 214 0.24% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 152 0.17% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 137 0.15% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 157 0.18% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 104 0.12% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 181 0.20% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 57 0.06% 61.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 133 0.15% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 31 0.03% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 17 0.02% 61.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 32 0.04% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 11 0.01% 61.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 93 0.10% 61.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 15 0.02% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 26 0.03% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 91 0.10% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 14 0.02% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 12 0.01% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 12 0.01% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 372 0.41% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 19 0.02% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 153 0.17% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 102 0.11% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 10 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 17 0.02% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904-3911 12 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 63.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4039 10 0.01% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 177 0.20% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 8 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 12 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 149 0.17% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 10 0.01% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 161 0.18% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 11 0.01% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 82 0.09% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 497 0.55% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 11 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 7 0.01% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 18 0.02% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 64 0.07% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 10 0.01% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 138 0.15% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 89 0.10% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 276 0.31% 65.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 33 0.04% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 146 0.16% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 83 0.09% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 5 0.01% 65.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 526 0.59% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 79 0.09% 66.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 1 0.00% 66.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 66.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 37 0.04% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 1 0.00% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 10 0.01% 66.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 407 0.45% 66.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 12 0.01% 66.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 33 0.04% 66.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 77 0.09% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 527 0.59% 67.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9351 2 0.00% 67.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 85 0.09% 67.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 150 0.17% 67.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 67.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 29 0.03% 67.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 279 0.31% 68.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 84 0.09% 68.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 6 0.01% 68.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 13 0.01% 68.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.22% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::36608-36615 131 0.15% 86.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 154 0.17% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 139 0.15% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 153 0.17% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 133 0.15% 85.96% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 84 0.09% 87.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 271 0.30% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 30 0.03% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 152 0.17% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 3 0.00% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 86 0.10% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 521 0.58% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40064-40071 2 0.00% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 77 0.09% 88.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 28 0.03% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 10 0.01% 88.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 402 0.45% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 9 0.01% 89.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 35 0.04% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 4 0.00% 89.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 79 0.09% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 523 0.58% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 79 0.09% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 146 0.16% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 34 0.04% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 269 0.30% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 89 0.10% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 3 0.00% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 13 0.01% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43904-43911 1 0.00% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 482 0.54% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 78 0.09% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 151 0.17% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 138 0.15% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 3 0.00% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 153 0.17% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45120-45127 2 0.00% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 134 0.15% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 77 0.09% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 82 0.09% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 341 0.38% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 89 0.10% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 419 0.47% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37959 1 0.00% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 18 0.02% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 140 0.16% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38528-38535 3 0.00% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 69 0.08% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38848-38855 2 0.00% 87.46% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 93 0.10% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 1 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 133 0.15% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 149 0.17% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 3 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 156 0.17% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 157 0.17% 93.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 3 0.00% 93.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 88 0.10% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 298 0.33% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 110 0.12% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 200 0.22% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 70 0.08% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 136 0.15% 94.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 5 0.01% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 9 0.01% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 6 0.01% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5002 5.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89727 # Bytes accessed per row activation -system.physmem.totQLat 373414318500 # Total ticks spent queuing -system.physmem.totMemAccLat 469593144750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 145 0.16% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 72 0.08% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 3 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 83 0.09% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 266 0.30% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 97 0.11% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 5 0.01% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 17 0.02% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 515 0.57% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 2 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 100 0.11% 94.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 142 0.16% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 8 0.01% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5062 5.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89677 # Bytes accessed per row activation +system.physmem.totQLat 373683436750 # Total ticks spent queuing +system.physmem.totMemAccLat 469596379250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18713571250 # Total ticks spent accessing banks -system.physmem.avgQLat 24102.05 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1207.87 # Average bank access latency per DRAM burst +system.physmem.totBankLat 18447687500 # Total ticks spent accessing banks +system.physmem.avgQLat 24119.42 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1190.71 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30309.92 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30310.13 # Average memory access latency per DRAM burst system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s @@ -639,12 +630,12 @@ system.physmem.busUtilRead 2.96 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing -system.physmem.readRowHits 15419103 # Number of row buffer hits during reads -system.physmem.writeRowHits 91153 # Number of row buffer hits during writes +system.physmem.readRowHits 15419160 # Number of row buffer hits during reads +system.physmem.writeRowHits 91146 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.23 # Row buffer hit rate for writes +system.physmem.writeRowHitRate 85.22 # Row buffer hit rate for writes system.physmem.avgGap 160458.28 # Average gap between requests -system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -696,11 +687,11 @@ system.membus.reqLayer2.occupancy 3614000 # La system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17910601500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17910610000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4950348835 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4950347835 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34633819250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34635983250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -818,7 +809,7 @@ system.iobus.reqLayer25.occupancy 15335424000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42037561750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -886,33 +877,33 @@ system.cpu.not_idle_fraction 0.124505 # Pe system.cpu.idle_fraction 0.875495 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856254 # number of replacements +system.cpu.icache.tags.replacements 856260 # number of replacements system.cpu.icache.tags.tagsinuse 510.868538 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60634647 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856766 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.771537 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 60634641 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.771035 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60634647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60634647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60634647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60634647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60634647 # number of overall hits -system.cpu.icache.overall_hits::total 60634647 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856766 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856766 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856766 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856766 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856766 # number of overall misses -system.cpu.icache.overall_misses::total 856766 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773893500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11773893500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11773893500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11773893500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11773893500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11773893500 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 60634641 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60634641 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60634641 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60634641 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60634641 # number of overall hits +system.cpu.icache.overall_hits::total 60634641 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856772 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856772 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856772 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses +system.cpu.icache.overall_misses::total 856772 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773713250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11773713250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11773713250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11773713250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11773713250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11773713250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses @@ -925,12 +916,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.251093 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13742.251093 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13742.251093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13742.251093 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.944473 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13741.944473 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13741.944473 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13741.944473 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -939,18 +930,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856766 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856766 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856766 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856766 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856766 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856766 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10056315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10056315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056315500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10056315500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856772 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856772 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856772 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056122750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10056122750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056122750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10056122750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056122750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10056122750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435321250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435321250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435321250 # number of overall MSHR uncacheable cycles @@ -961,28 +952,28 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.528683 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.528683 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.528683 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.528683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.528683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.528683 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.221513 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.221513 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 62509 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50754.670173 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1682271 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 50754.670351 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1682272 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.153944 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.153951 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37718.408308 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 37718.407530 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.399948 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.976844 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400299 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977449 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -991,122 +982,122 @@ system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844545 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 369635 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226417 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595234 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595234 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 844551 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 369631 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226419 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595233 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595233 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113385 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113385 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113388 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113388 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 8705 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3532 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844545 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 483020 # number of demand (read+write) hits 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60524.447331 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59374.304918 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59374.304918 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58563.863958 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59597.697660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.421514 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58563.863958 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59597.697660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.421514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1210,47 +1201,47 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626141 # number of replacements +system.cpu.dcache.tags.replacements 626139 # number of replacements system.cpu.dcache.tags.tagsinuse 511.876746 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655438 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626653 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.748863 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 23655440 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626651 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.748986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195736 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195736 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972597 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236394 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236394 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13195741 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195741 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972594 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972594 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236393 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236393 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168333 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168333 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168333 # number of overall hits -system.cpu.dcache.overall_hits::total 23168333 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368059 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250142 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250142 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11385 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11385 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618201 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618201 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618201 # number of overall misses -system.cpu.dcache.overall_misses::total 618201 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416878250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5416878250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11621403015 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11621403015 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158363750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158363750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17038281265 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17038281265 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17038281265 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17038281265 # number of overall miss cycles +system.cpu.dcache.demand_hits::cpu.data 23168335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168335 # number of overall hits +system.cpu.dcache.overall_hits::total 23168335 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368054 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368054 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250145 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250145 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11386 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11386 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 618199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618199 # number of overall misses +system.cpu.dcache.overall_misses::total 618199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416240000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5416240000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11622215515 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11622215515 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158376750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158376750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17038455515 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17038455515 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17038455515 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17038455515 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) @@ -1267,22 +1258,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027135 system.cpu.dcache.ReadReq_miss_rate::total 0.027135 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045948 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045948 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025990 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025990 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025990 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025990 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14717.418267 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14717.418267 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46459.223221 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46459.223221 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.859464 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.859464 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27561.070372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27561.070372 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14715.884082 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14715.884082 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46461.914150 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46461.914150 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.779554 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.779554 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27561.441405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27561.441405 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1291,28 +1282,28 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595234 # number of writebacks -system.cpu.dcache.writebacks::total 595234 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250142 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250142 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11385 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11385 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618201 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678465750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678465750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069177985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069177985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135539250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135539250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747643735 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15747643735 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747643735 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15747643735 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 595233 # number of writebacks +system.cpu.dcache.writebacks::total 595233 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368054 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368054 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250145 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250145 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618199 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618199 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618199 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618199 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069989485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069989485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135550250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135550250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747826485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15747826485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747826485 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15747826485 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles @@ -1323,22 +1314,22 @@ system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045948 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045948 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025990 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025990 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12711.184212 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12711.184212 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44251.577044 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44251.577044 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11905.072464 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.072464 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045952 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12709.648584 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12709.648584 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44254.290452 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44254.290452 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.992974 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.992974 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1346,33 +1337,33 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52965120 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454582 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454582 # Transaction distribution +system.cpu.toL2Bus.throughput 52965193 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595234 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247209 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::Writeback 595233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247211 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749349 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7514380 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54754804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615077 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755188 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614885 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138418857 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138418857 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138419049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138419049 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3008581500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3008582500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295429750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295439000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2534385915 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2534381165 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1392,10 +1383,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1538389615750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1538389615750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1538393065750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1538393065750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index d251aac9e..44d2483e8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,22 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,18 +228,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=AtomicSimpleCPU @@ -234,6 +254,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -262,17 +283,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -291,30 +315,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -327,6 +357,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -349,6 +380,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -358,6 +390,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -380,6 +413,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -387,6 +421,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -398,6 +433,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -413,41 +449,22 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -457,6 +474,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -466,6 +484,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -494,6 +513,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -503,8 +523,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -516,6 +568,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -531,6 +584,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -545,6 +600,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -554,6 +610,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -575,8 +632,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -585,6 +644,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -595,6 +655,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -605,6 +666,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -615,6 +677,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -629,6 +692,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -642,6 +706,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -659,6 +724,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -671,6 +737,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -682,6 +749,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -692,6 +760,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -704,6 +773,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -717,6 +787,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -727,6 +798,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -737,6 +809,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -747,6 +820,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -759,6 +833,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -773,6 +848,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -785,6 +861,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -799,6 +876,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -809,6 +887,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -819,6 +898,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -829,6 +909,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -837,6 +918,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -845,6 +927,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -854,11 +937,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index fae0b4d4b..7eb912550 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,13 +4,25 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1464492 # Simulator instruction rate (inst/s) -host_op_rate 1883246 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56554479678 # Simulator tick rate (ticks/s) -host_mem_usage 398712 # Number of bytes of host memory used -host_seconds 41.25 # Real time elapsed on the host +host_inst_rate 840369 # Simulator instruction rate (inst/s) +host_op_rate 1080663 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32452660609 # Simulator tick rate (ticks/s) +host_mem_usage 444352 # Number of bytes of host memory used +host_seconds 71.88 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory @@ -62,18 +74,6 @@ system.physmem.bw_total::cpu0.data 3386724 # To system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 55969561 # Throughput (bytes/s) system.membus.data_through_bus 130566366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -286,7 +286,7 @@ system.cpu0.itb.inst_accesses 32546956 # IT system.cpu0.itb.hits 32543253 # DTB hits system.cpu0.itb.misses 3703 # DTB misses system.cpu0.itb.accesses 32546956 # DTB accesses -system.cpu0.numCycles 4633589665 # number of cpu cycles simulated +system.cpu0.numCycles 4633633401 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 31998091 # Number of instructions committed @@ -304,8 +304,8 @@ system.cpu0.num_fp_register_writes 1428 # nu system.cpu0.num_mem_refs 15013057 # number of memory refs system.cpu0.num_load_insts 8304661 # Number of load instructions system.cpu0.num_store_insts 6708396 # Number of store instructions -system.cpu0.num_idle_cycles 4555625120.147407 # Number of idle cycles -system.cpu0.num_busy_cycles 77964544.852593 # Number of busy cycles +system.cpu0.num_idle_cycles 4555668120.247687 # Number of idle cycles +system.cpu0.num_busy_cycles 77965280.752313 # Number of busy cycles system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -496,7 +496,7 @@ system.cpu1.itb.inst_accesses 28889355 # IT system.cpu1.itb.hits 28886892 # DTB hits system.cpu1.itb.misses 2463 # DTB misses system.cpu1.itb.accesses 28889355 # DTB accesses -system.cpu1.numCycles 4279954879 # number of cpu cycles simulated +system.cpu1.numCycles 4279988156 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 28410548 # Number of instructions committed @@ -514,8 +514,8 @@ system.cpu1.num_fp_register_writes 1352 # nu system.cpu1.num_mem_refs 12348580 # number of memory refs system.cpu1.num_load_insts 7334866 # Number of load instructions system.cpu1.num_store_insts 5013714 # Number of store instructions -system.cpu1.num_idle_cycles 4217653381.679553 # Number of idle cycles -system.cpu1.num_busy_cycles 62301497.320448 # Number of busy cycles +system.cpu1.num_idle_cycles 4217686174.280304 # Number of idle cycles +system.cpu1.num_busy_cycles 62301981.719696 # Number of busy cycles system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 5c09eba9d..299ddfd61 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -14,10 +16,11 @@ boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 cache_line_size=64 clk_domain=system.clk_domain e820_table=system.e820_table +eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -38,6 +41,7 @@ system_port=system.membus.slave[1] [system.acpi_description_table_pointer] type=X86ACPIRSDP children=xsdt +eventq_index=0 oem_id= revision=2 rsdt=Null @@ -48,6 +52,7 @@ type=X86ACPIXSDT creator_id= creator_revision=0 entries= +eventq_index=0 oem_id= oem_revision=0 oem_table_id= @@ -56,6 +61,7 @@ oem_table_id= type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=11529215046068469760:11529215046068473855 req_size=16 resp_size=16 @@ -66,6 +72,7 @@ slave=system.iobus.master[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 @@ -75,6 +82,7 @@ slave=system.membus.master[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -87,6 +95,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -118,6 +127,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -125,6 +135,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -147,18 +158,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.dtb_walker_cache.cpu_side @@ -169,6 +183,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -191,6 +206,7 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=1024 @@ -200,6 +216,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -222,12 +239,14 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -238,16 +257,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.itb_walker_cache.cpu_side @@ -258,6 +280,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -280,6 +303,7 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=1024 @@ -289,6 +313,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -311,12 +336,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -326,44 +353,52 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table children=entries0 entries1 entries2 entries3 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +eventq_index=0 [system.e820_table.entries0] type=X86E820Entry addr=0 +eventq_index=0 range_type=1 size=654336 [system.e820_table.entries1] type=X86E820Entry addr=654336 +eventq_index=0 range_type=2 size=394240 [system.e820_table.entries2] type=X86E820Entry addr=1048576 +eventq_index=0 range_type=1 size=133169152 [system.e820_table.entries3] type=X86E820Entry addr=4294901760 +eventq_index=0 range_type=2 size=65536 [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 +eventq_index=0 imcr_present=true spec_rev=4 @@ -371,6 +406,7 @@ spec_rev=4 type=X86IntelMPConfigTable children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +eventq_index=0 ext_entries=system.intel_mp_table.ext_entries local_apic=4276092928 oem_id= @@ -383,6 +419,7 @@ spec_rev=4 type=X86IntelMPProcessor bootstrap=true enable=true +eventq_index=0 family=0 feature_flags=0 local_apic_id=0 @@ -394,6 +431,7 @@ stepping=0 type=X86IntelMPIOAPIC address=4273995776 enable=true +eventq_index=0 id=1 version=17 @@ -401,16 +439,19 @@ version=17 type=X86IntelMPBus bus_id=0 bus_type=ISA +eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 bus_type=PCI +eventq_index=0 [system.intel_mp_table.base_entries04] type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=16 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=1 @@ -421,6 +462,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -431,6 +473,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=2 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -441,6 +484,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -451,6 +495,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=1 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -461,6 +506,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -471,6 +517,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=3 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -481,6 +528,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -491,6 +539,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=4 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -501,6 +550,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -511,6 +561,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=5 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -521,6 +572,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -531,6 +583,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=6 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -541,6 +594,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -551,6 +605,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=7 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -561,6 +616,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -571,6 +627,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=8 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -581,6 +638,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -591,6 +649,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=9 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -601,6 +660,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -611,6 +671,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=10 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -621,6 +682,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -631,6 +693,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=11 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -641,6 +704,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -651,6 +715,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=12 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -661,6 +726,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -671,6 +737,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=13 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -681,6 +748,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=0 +eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity source_bus_id=0 @@ -691,6 +759,7 @@ trigger=ConformTrigger type=X86IntelMPIOIntAssignment dest_io_apic_id=1 dest_io_apic_intin=14 +eventq_index=0 interrupt_type=INT polarity=ConformPolarity source_bus_id=0 @@ -700,16 +769,19 @@ trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy bus_id=0 +eventq_index=0 parent_bus=1 subtractive_decode=true [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=true width=8 @@ -723,6 +795,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -745,6 +818,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -752,6 +826,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -763,6 +838,7 @@ slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side sy [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -779,13 +855,15 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge +eventq_index=0 intrctrl=system.intrctrl system=system [system.pc.behind_pci] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854779128 pio_latency=100000 @@ -804,6 +882,7 @@ pio=system.iobus.master[12] type=Uart8250 children=terminal clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854776824 pio_latency=100000 platform=system.pc @@ -813,13 +892,7 @@ pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.pc.com_1.terminal] -type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -828,6 +901,7 @@ port=3456 [system.pc.fake_com_2] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776568 pio_latency=100000 @@ -845,6 +919,7 @@ pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776808 pio_latency=100000 @@ -862,6 +937,7 @@ pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776552 pio_latency=100000 @@ -879,6 +955,7 @@ pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854776818 pio_latency=100000 @@ -896,6 +973,7 @@ pio=system.iobus.master[17] [system.pc.i_dont_exist] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=9223372036854775936 pio_latency=100000 @@ -914,6 +992,7 @@ pio=system.iobus.master[11] type=PciConfigAll bus=0 clk_domain=system.clk_domain +eventq_index=0 pio_addr=0 pio_latency=30000 platform=system.pc @@ -926,6 +1005,7 @@ type=SouthBridge children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker cmos=system.pc.south_bridge.cmos dma1=system.pc.south_bridge.dma1 +eventq_index=0 io_apic=system.pc.south_bridge.io_apic keyboard=system.pc.south_bridge.keyboard pic1=system.pc.south_bridge.pic1 @@ -938,6 +1018,7 @@ speaker=system.pc.south_bridge.speaker type=Cmos children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=100000 @@ -947,10 +1028,12 @@ pio=system.iobus.master[1] [system.pc.south_bridge.cmos.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.dma1] type=I8237 clk_domain=system.clk_domain +eventq_index=0 pio_addr=9223372036854775808 pio_latency=100000 system=system @@ -979,6 +1062,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=0 @@ -988,8 +1072,40 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=128 Revision=0 Status=640 @@ -1001,6 +1117,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +eventq_index=0 io_shift=0 pci_bus=0 pci_dev=4 @@ -1017,19 +1134,22 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks0.image [system.pc.south_bridge.ide.disks0.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1037,102 +1157,120 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.pc.south_bridge.ide.disks1.image [system.pc.south_bridge.ide.disks1.image] type=CowDiskImage children=child child=system.pc.south_bridge.ide.disks1.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines0.sink source=system.pc.south_bridge.pic1.output [system.pc.south_bridge.int_lines0.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=0 [system.pc.south_bridge.int_lines1] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines1.sink source=system.pc.south_bridge.pic2.output [system.pc.south_bridge.int_lines1.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=2 [system.pc.south_bridge.int_lines2] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines2.sink source=system.pc.south_bridge.cmos.int_pin [system.pc.south_bridge.int_lines2.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic2 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines3] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines3.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines3.sink] type=X86IntSinkPin device=system.pc.south_bridge.pic1 +eventq_index=0 number=0 [system.pc.south_bridge.int_lines4] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines4.sink source=system.pc.south_bridge.pit.int_pin [system.pc.south_bridge.int_lines4.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=2 [system.pc.south_bridge.int_lines5] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines5.sink source=system.pc.south_bridge.keyboard.keyboard_int_pin [system.pc.south_bridge.int_lines5.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=1 [system.pc.south_bridge.int_lines6] type=X86IntLine children=sink +eventq_index=0 sink=system.pc.south_bridge.int_lines6.sink source=system.pc.south_bridge.keyboard.mouse_int_pin [system.pc.south_bridge.int_lines6.sink] type=X86IntSinkPin device=system.pc.south_bridge.io_apic +eventq_index=0 number=12 [system.pc.south_bridge.io_apic] type=I82094AA apic_id=1 clk_domain=system.clk_domain +eventq_index=0 external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 @@ -1147,6 +1285,7 @@ children=keyboard_int_pin mouse_int_pin clk_domain=system.clk_domain command_port=9223372036854775908 data_port=9223372036854775904 +eventq_index=0 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 @@ -1156,14 +1295,17 @@ pio=system.iobus.master[5] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.keyboard.mouse_int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic1] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 @@ -1174,11 +1316,13 @@ pio=system.iobus.master[6] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pic2] type=I8259 children=output clk_domain=system.clk_domain +eventq_index=0 mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 @@ -1189,11 +1333,13 @@ pio=system.iobus.master[7] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.pit] type=I8254 children=int_pin clk_domain=system.clk_domain +eventq_index=0 int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 @@ -1202,10 +1348,12 @@ pio=system.iobus.master[8] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin +eventq_index=0 [system.pc.south_bridge.speaker] type=PcSpeaker clk_domain=system.clk_domain +eventq_index=0 i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 @@ -1213,41 +1361,22 @@ system=system pio=system.iobus.master[9] [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[3] [system.smbios_table] type=X86SMBiosSMBiosTable children=structures +eventq_index=0 major_version=2 minor_version=5 structures=system.smbios_table.structures @@ -1258,6 +1387,7 @@ characteristic_ext_bytes= characteristics= emb_cont_firmware_major=0 emb_cont_firmware_minor=0 +eventq_index=0 major=0 minor=0 release_date=06/08/2008 @@ -1268,5 +1398,6 @@ version= [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index e8eca4ecf..8eed6a1f4 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112126 # Nu sim_ticks 5112126264500 # Number of ticks simulated final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1904189 # Simulator instruction rate (inst/s) -host_op_rate 3898708 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48689346278 # Simulator tick rate (ticks/s) -host_mem_usage 587596 # Number of bytes of host memory used -host_seconds 104.99 # Real time elapsed on the host +host_inst_rate 1049292 # Simulator instruction rate (inst/s) +host_op_rate 2148359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26829969216 # Simulator tick rate (ticks/s) +host_mem_usage 634884 # Number of bytes of host memory used +host_seconds 190.54 # Real time elapsed on the host sim_insts 199929810 # Number of instructions simulated sim_ops 409343850 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory @@ -107,7 +107,7 @@ system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.iobus.throughput 2555207 # Throughput (bytes/s) system.iobus.data_through_bus 13062542 # Total data (bytes) -system.cpu.numCycles 10224252551 # number of cpu cycles simulated +system.cpu.numCycles 10224253904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 199929810 # Number of instructions committed @@ -127,8 +127,8 @@ system.cpu.num_cc_register_writes 157233555 # nu system.cpu.num_mem_refs 35660913 # number of memory refs system.cpu.num_load_insts 27238816 # Number of load instructions system.cpu.num_store_insts 8422097 # Number of store instructions -system.cpu.num_idle_cycles 9770516920.735764 # Number of idle cycles -system.cpu.num_busy_cycles 453735630.264235 # Number of busy cycles +system.cpu.num_idle_cycles 9770518213.691833 # Number of idle cycles +system.cpu.num_busy_cycles 453735690.308166 # Number of busy cycles system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955622 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index b09aafac2..07eaff0f1 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 0ff2f61a7..cfed15046 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21065000 # Number of ticks simulated final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31290 # Simulator instruction rate (inst/s) -host_op_rate 31288 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 103426086 # Simulator tick rate (ticks/s) -host_mem_usage 226120 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 36663 # Simulator instruction rate (inst/s) +host_op_rate 36659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121177991 # Simulator tick rate (ticks/s) +host_mem_usage 273132 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -214,8 +214,8 @@ system.membus.reqLayer0.occupancy 619000 # La system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 21.6 # Layer utilization (%) -system.cpu.branchPred.lookups 2884 # Number of BP lookups -system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2883 # Number of BP lookups +system.cpu.branchPred.condPredicted 1697 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups system.cpu.branchPred.BTBHits 756 # Number of BTB hits @@ -259,11 +259,11 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 42131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 8531 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2883 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2963 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -271,24 +271,24 @@ system.cpu.fetch.PendingTrapStallCycles 747 # Nu system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.095282 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.492986 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12150 80.39% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.10% 82.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 84.05% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.69% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 240 1.59% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 183 1.21% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1255 8.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.068429 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.392894 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2764 # Number of cycles decode is running diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 8335373d5..90b395123 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,19 +518,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=MipsInterrupts +eventq_index=0 [system.cpu.isa] type=MipsISA +eventq_index=0 num_threads=1 num_vpes=1 [system.cpu.itb] type=MipsTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -484,6 +543,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -506,12 +566,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -521,6 +583,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -530,7 +593,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -544,11 +608,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -568,6 +634,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -579,17 +646,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 1c2de0612..3589948bc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21898500 # Number of ticks simulated final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64871 # Simulator instruction rate (inst/s) -host_op_rate 64859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 275425114 # Simulator tick rate (ticks/s) -host_mem_usage 255508 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 34889 # Simulator instruction rate (inst/s) +host_op_rate 34885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148144968 # Simulator tick rate (ticks/s) +host_mem_usage 274956 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -208,9 +208,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4474750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 20.4 # Layer utilization (%) system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted @@ -272,31 +272,31 @@ system.cpu.fetch.rateDist::max_value 8 # Nu system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 8890 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3026 # Number of cycles decode is running +system.cpu.decode.RunCycles 3025 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 9072 # Number of cycles rename is idle system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2899 # Number of cycles rename is running +system.cpu.rename.RunCycles 2898 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer @@ -423,7 +423,7 @@ system.cpu.iew.iewSquashCycles 868 # Nu system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions @@ -538,12 +538,12 @@ system.cpu.icache.demand_misses::cpu.inst 451 # n system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses system.cpu.icache.overall_misses::total 451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31196500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31196500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31196500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31196500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31196500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31196500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses @@ -556,12 +556,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69171.840355 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69171.840355 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69171.840355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69171.840355 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -582,32 +582,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338 system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24201750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24201750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24201750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24201750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24201750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24201750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71602.810651 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71602.810651 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.801023 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923735 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy @@ -629,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23833750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30860500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23833750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 34674750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23833750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34674750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -662,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71145.522388 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72442.488263 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72693.396226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72693.396226 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index ffa288769..708085ca5 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,20 +518,25 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa0] type=AlphaISA +eventq_index=0 [system.cpu.isa1] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -485,6 +545,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -507,12 +568,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -522,6 +585,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload0] type=LiveProcess @@ -531,7 +595,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -550,7 +615,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +eventq_index=0 +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -564,11 +630,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -588,6 +656,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -599,17 +668,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 15c806f18..b48213381 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24229500 # Number of ticks simulated final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81251 # Simulator instruction rate (inst/s) -host_op_rate 81244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 154440285 # Simulator tick rate (ticks/s) -host_mem_usage 227736 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 38113 # Simulator instruction rate (inst/s) +host_op_rate 38111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72448291 # Simulator tick rate (ticks/s) +host_mem_usage 273720 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory @@ -219,34 +219,34 @@ system.membus.reqLayer0.utilization 5.1 # La system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 37.4 # Layer utilization (%) system.cpu.branchPred.lookups 6676 # Number of BP lookups -system.cpu.branchPred.condPredicted 3773 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 3772 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4746 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 4747 # Number of BTB lookups system.cpu.branchPred.BTBHits 873 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.394437 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 18.390562 # BTB Hit Percentage system.cpu.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 179 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4588 # DTB read hits +system.cpu.dtb.read_hits 4587 # DTB read hits system.cpu.dtb.read_misses 111 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4699 # DTB read accesses +system.cpu.dtb.read_accesses 4698 # DTB read accesses system.cpu.dtb.write_hits 2013 # DTB write hits -system.cpu.dtb.write_misses 87 # DTB write misses +system.cpu.dtb.write_misses 86 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2100 # DTB write accesses -system.cpu.dtb.data_hits 6601 # DTB hits -system.cpu.dtb.data_misses 198 # DTB misses +system.cpu.dtb.write_accesses 2099 # DTB write accesses +system.cpu.dtb.data_hits 6600 # DTB hits +system.cpu.dtb.data_misses 197 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6799 # DTB accesses -system.cpu.itb.fetch_hits 5373 # ITB hits +system.cpu.dtb.data_accesses 6797 # DTB accesses +system.cpu.itb.fetch_hits 5374 # ITB hits system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5430 # ITB accesses +system.cpu.itb.fetch_accesses 5431 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -265,50 +265,50 @@ system.cpu.numCycles 48460 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 1592 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 37136 # Number of instructions fetch has processed +system.cpu.fetch.Insts 37128 # Number of instructions fetch has processed system.cpu.fetch.Branches 6676 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1759 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 6222 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1834 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 325 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5373 # Number of cache lines fetched +system.cpu.fetch.CacheLines 5374 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 890 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 29553 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.256590 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.686803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 29555 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.256234 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.686456 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23330 78.94% 78.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23333 78.95% 78.95% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 540 1.83% 80.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 380 1.29% 82.06% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 444 1.50% 83.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 426 1.44% 85.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 410 1.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 457 1.55% 87.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 520 1.76% 89.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3046 10.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 457 1.55% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 520 1.76% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3045 10.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 29553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 29555 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.137763 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.766323 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40475 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9887 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5338 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 491 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2736 # Number of cycles decode is squashing +system.cpu.fetch.rate 0.766158 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40476 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9889 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5340 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2737 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 565 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 333 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 32705 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 703 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2736 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 41176 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6161 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 2737 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 41177 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6164 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1585 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 5023 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2246 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30191 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 53 # Number of times rename has blocked due to ROB full +system.cpu.rename.UnblockCycles 2245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30189 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 54 # Number of times rename has blocked due to ROB full system.cpu.rename.LSQFullEvents 2292 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 22672 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 37159 # Number of register rename lookups that rename has made @@ -318,31 +318,31 @@ system.cpu.rename.CommittedMaps 9140 # Nu system.cpu.rename.UndoneMaps 13532 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 49 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6118 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 6114 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2970 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1346 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 3035 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 3034 # Number of loads inserted to the mem dependence unit. system.cpu.memDep1.insertedStores 1382 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26321 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsAdded 26322 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 21626 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 12553 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 8051 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 29553 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.731770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.328577 # Number of insts issued each cycle +system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 29555 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.731721 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.328495 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 20214 68.40% 68.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3351 11.34% 79.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2621 8.87% 88.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1590 5.38% 93.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1011 3.42% 97.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20216 68.40% 68.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3350 11.33% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2622 8.87% 88.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1591 5.38% 93.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1010 3.42% 97.41% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 474 1.60% 99.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 217 0.73% 99.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 53 0.18% 99.93% # Number of insts issued each cycle @@ -350,7 +350,7 @@ system.cpu.iq.issued_per_cycle::8 22 0.07% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 29553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 29555 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9 4.86% 4.86% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available @@ -421,36 +421,36 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10800 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7137 65.92% 65.94% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.95% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.95% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2587 23.90% 89.87% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7138 65.93% 65.95% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.96% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.96% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2586 23.89% 89.87% # Type of FU issued system.cpu.iq.FU_type_1::MemWrite 1097 10.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued @@ -463,9 +463,9 @@ system.cpu.iq.fu_busy_cnt::total 185 # FU system.cpu.iq.fu_busy_rate::0 0.004069 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate::1 0.004485 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate::total 0.008555 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 73079 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 73081 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 38962 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18683 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 18684 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses @@ -483,34 +483,34 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 1 # system.cpu.iew.lsq.thread0.cacheBlocked 350 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1852 # Number of loads squashed +system.cpu.iew.lsq.thread1.squashedLoads 1851 # Number of loads squashed system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations system.cpu.iew.lsq.thread1.squashedStores 517 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 408 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2736 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 2737 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 2954 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 26599 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 599 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6005 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 6004 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 2728 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1303 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20164 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 20163 # Number of executed instructions system.cpu.iew.iewExecLoadInsts::0 2351 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2366 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4717 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1462 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts::1 2365 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed @@ -518,47 +518,47 @@ system.cpu.iew.exec_nop::0 109 # nu system.cpu.iew.exec_nop::1 90 # number of nop insts executed system.cpu.iew.exec_nop::total 199 # number of nop insts executed system.cpu.iew.exec_refs::0 3417 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3414 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6831 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3412 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6829 # number of memory reference insts executed system.cpu.iew.exec_branches::0 1584 # Number of branches executed system.cpu.iew.exec_branches::1 1595 # Number of branches executed system.cpu.iew.exec_branches::total 3179 # Number of branches executed system.cpu.iew.exec_stores::0 1066 # Number of stores executed -system.cpu.iew.exec_stores::1 1048 # Number of stores executed -system.cpu.iew.exec_stores::total 2114 # Number of stores executed -system.cpu.iew.exec_rate 0.416096 # Inst execution rate +system.cpu.iew.exec_stores::1 1047 # Number of stores executed +system.cpu.iew.exec_stores::total 2113 # Number of stores executed +system.cpu.iew.exec_rate 0.416075 # Inst execution rate system.cpu.iew.wb_sent::0 9509 # cumulative count of insts sent to commit system.cpu.iew.wb_sent::1 9507 # cumulative count of insts sent to commit system.cpu.iew.wb_sent::total 19016 # cumulative count of insts sent to commit system.cpu.iew.wb_count::0 9333 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9370 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18703 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9371 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18704 # cumulative count of insts written-back system.cpu.iew.wb_producers::0 4798 # num instructions producing a value -system.cpu.iew.wb_producers::1 4829 # num instructions producing a value -system.cpu.iew.wb_producers::total 9627 # num instructions producing a value +system.cpu.iew.wb_producers::1 4830 # num instructions producing a value +system.cpu.iew.wb_producers::total 9628 # num instructions producing a value system.cpu.iew.wb_consumers::0 6247 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6319 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12566 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6320 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12567 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate::0 0.192592 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.193355 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.385947 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.193376 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.385968 # insts written-back per cycle system.cpu.iew.wb_fanout::0 0.768049 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.764203 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.766115 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.764241 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.766134 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 13828 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1125 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29486 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.433392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.196069 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 29488 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433363 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.196034 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23745 80.53% 80.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23747 80.53% 80.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 3040 10.31% 90.84% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 1123 3.81% 94.65% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 504 1.71% 96.36% # Number of insts commited each cycle @@ -570,7 +570,7 @@ system.cpu.commit.committed_per_cycle::8 211 0.72% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29486 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29488 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6390 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -605,10 +605,10 @@ system.cpu.commit.bw_lim_events 211 # nu system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132694 # The number of ROB reads -system.cpu.rob.rob_writes 55968 # The number of ROB writes +system.cpu.rob.rob_reads 132697 # The number of ROB reads +system.cpu.rob.rob_writes 55969 # The number of ROB writes system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18907 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 18905 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6373 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated @@ -620,8 +620,8 @@ system.cpu.cpi_total 3.802275 # CP system.cpu.ipc::0 0.131511 # IPC: Instructions Per Cycle system.cpu.ipc::1 0.131490 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.263000 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25291 # number of integer regfile reads -system.cpu.int_regfile_writes 14128 # number of integer regfile writes +system.cpu.int_regfile_reads 25289 # number of integer regfile reads +system.cpu.int_regfile_writes 14129 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -649,19 +649,19 @@ system.cpu.icache.tags.replacements::0 6 # nu system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 6 # number of replacements system.cpu.icache.tags.tagsinuse 312.493120 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4319 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 4320 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.899361 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.900958 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4319 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4319 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4319 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4319 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4319 # number of overall hits -system.cpu.icache.overall_hits::total 4319 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 4320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4320 # number of overall hits +system.cpu.icache.overall_hits::total 4320 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses @@ -674,18 +674,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 69934495 system.cpu.icache.demand_miss_latency::total 69934495 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 69934495 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 69934495 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5368 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5368 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5368 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5368 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195417 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195417 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195417 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195417 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195417 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195417 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 5369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5369 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5369 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5369 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5369 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195381 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195381 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195381 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195381 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195381 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195381 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66667.774071 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 66667.774071 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency @@ -718,12 +718,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46953746 system.cpu.icache.demand_mshr_miss_latency::total 46953746 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46953746 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 46953746 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116617 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116617 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116617 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116617 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75005.984026 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75005.984026 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 80c73e0c8..de3e77970 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bu boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,21 +518,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu0.isa] type=SparcISA +eventq_index=0 [system.cpu0.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu0.workload] type=LiveProcess @@ -487,7 +547,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +eventq_index=0 +executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -527,6 +588,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -591,6 +654,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -606,6 +670,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -628,26 +693,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -656,16 +726,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -674,22 +747,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -698,22 +775,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -722,10 +803,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -734,124 +817,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -860,10 +964,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -872,16 +978,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -890,10 +999,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -904,6 +1015,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -926,21 +1038,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu1.isa] type=SparcISA +eventq_index=0 [system.cpu1.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -971,6 +1088,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -1035,6 +1154,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -1050,6 +1170,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -1072,26 +1193,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu2.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -1100,16 +1226,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -1118,22 +1247,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -1142,22 +1275,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -1166,10 +1303,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -1178,124 +1317,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -1304,10 +1464,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -1316,16 +1478,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -1334,10 +1499,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -1348,6 +1515,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -1370,21 +1538,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu2.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu2.isa] type=SparcISA +eventq_index=0 [system.cpu2.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu3] type=DerivO3CPU @@ -1415,6 +1588,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu3.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -1479,6 +1654,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -1494,6 +1670,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -1516,26 +1693,31 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu3.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 +eventq_index=0 [system.cpu3.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu3.fuPool.FUList0.opList [system.cpu3.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -1544,16 +1726,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 [system.cpu3.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu3.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -1562,22 +1747,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 [system.cpu3.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu3.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu3.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -1586,22 +1775,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 [system.cpu3.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu3.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu3.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -1610,10 +1803,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu3.fuPool.FUList4.opList [system.cpu3.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -1622,124 +1817,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 [system.cpu3.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu3.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu3.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu3.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu3.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu3.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu3.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu3.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu3.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu3.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu3.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu3.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu3.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu3.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu3.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu3.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu3.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu3.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu3.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu3.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -1748,10 +1964,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu3.fuPool.FUList6.opList [system.cpu3.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -1760,16 +1978,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 [system.cpu3.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu3.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -1778,10 +1999,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu3.fuPool.FUList8.opList [system.cpu3.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -1792,6 +2015,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -1814,25 +2038,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu3.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu3.isa] type=SparcISA +eventq_index=0 [system.cpu3.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.l2c] @@ -1841,6 +2071,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1863,12 +2094,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1888,6 +2121,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1899,19 +2133,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1921,5 +2159,6 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index b78a3e4ce..34d426284 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000111 # Nu sim_ticks 111025500 # Number of ticks simulated final_tick 111025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119782 # Simulator instruction rate (inst/s) -host_op_rate 119782 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12747983 # Simulator tick rate (ticks/s) -host_mem_usage 275656 # Number of bytes of host memory used -host_seconds 8.71 # Real time elapsed on the host +host_inst_rate 77886 # Simulator instruction rate (inst/s) +host_op_rate 77886 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8289137 # Simulator tick rate (ticks/s) +host_mem_usage 295244 # Number of bytes of host memory used +host_seconds 13.39 # Real time elapsed on the host sim_insts 1043212 # Number of instructions simulated sim_ops 1043212 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory @@ -204,14 +204,14 @@ system.physmem.bytesPerActivate::1152 1 0.66% 98.68% # By system.physmem.bytesPerActivate::1536 1 0.66% 99.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984 1 0.66% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 151 # Bytes accessed per row activation -system.physmem.totQLat 4010250 # Total ticks spent queuing -system.physmem.totMemAccLat 18159000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4008250 # Total ticks spent queuing +system.physmem.totMemAccLat 18157000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers system.physmem.totBankLat 10848750 # Total ticks spent accessing banks -system.physmem.avgQLat 6076.14 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6073.11 # Average queueing delay per DRAM burst system.physmem.avgBankLat 16437.50 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27513.64 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27510.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 380.45 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 380.45 # Average system read bandwidth in MiByte/s @@ -242,19 +242,19 @@ system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 931500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 932000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6289925 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 6290425 # Layer occupancy (ticks) system.membus.respLayer1.utilization 5.7 # Layer utilization (%) system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 417.165472 # Cycle average of tags in use +system.l2c.tags.tagsinuse 417.163639 # Cycle average of tags in use system.l2c.tags.total_refs 1442 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 2.741445 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 0.799798 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 285.088059 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.417692 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 285.086488 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.417431 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 7.543236 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 0.694746 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.inst 55.417060 # Average occupied blocks per requestor @@ -339,38 +339,38 @@ system.l2c.overall_misses::cpu2.data 20 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 674 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24801500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 24802000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 5612000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 1162500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.inst 5361500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 584250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 583750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 38166000 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 6725000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 958250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9622500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 24801500 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 957750 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9622000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 24802000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 12337000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 1162500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.inst 5361500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 584250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 1032750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 47788500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 24801500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu3.inst 583750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1032250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 47788000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 24802000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 12337000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 1162500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.inst 5361500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 584250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 1032750 # number of overall miss cycles -system.l2c.overall_miss_latency::total 47788500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 583750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1032250 # number of overall miss cycles +system.l2c.overall_miss_latency::total 47788000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) @@ -447,38 +447,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.800000 # mi system.l2c.overall_miss_rate::cpu3.inst 0.020979 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.318526 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69084.958217 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69086.350975 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72656.250000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70546.052632 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64916.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64861.111111 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 70287.292818 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71542.553191 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79854.166667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73454.198473 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79812.500000 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73450.381679 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 69086.350975 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70902.818991 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 69084.958217 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 64861.111111 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 79403.846154 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 70902.077151 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 69086.350975 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 73434.523810 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 72656.250000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 70546.052632 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 64916.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 79442.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70902.818991 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 64861.111111 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 79403.846154 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 70902.077151 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,9 +545,9 @@ system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 676500 system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4287250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 408750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 369750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 369250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 30807000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 30806500 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 210021 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 217519 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 170017 # number of UpgradeReq MSHR miss cycles @@ -556,26 +556,26 @@ system.l2c.UpgradeReq_mshr_miss_latency::total 777575 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5552000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701750 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 928000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807750 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7989500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 807250 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7989000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 20238250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 10253500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 676500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 764250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 4287250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 1336750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 369750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 870250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 38796500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 369250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 869750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 38795500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 20238250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 10253500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 676500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 764250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 4287250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 1336750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 369750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 870250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 38796500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 369250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 869750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 38795500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses @@ -619,9 +619,9 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67650 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 58236.294896 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 58235.349716 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10875.950000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency @@ -630,26 +630,26 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59063.829787 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67312.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60988.549618 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67270.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60984.732824 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67650 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66942.307692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58782.575758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61541.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66903.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58781.060606 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 1689557804 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2542 # Transaction distribution @@ -710,7 +710,7 @@ system.cpu0.workload.num_syscalls 89 # Nu system.cpu0.numCycles 222052 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17258 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.icacheStallCycles 17259 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 493192 # Number of instructions fetch has processed system.cpu0.fetch.Branches 83087 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 78844 # Number of branches that fetch has predicted taken @@ -720,12 +720,12 @@ system.cpu0.fetch.BlockedCycles 13993 # Nu system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5869 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 489 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 197037 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503043 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.216869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 488 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 197038 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503030 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216871 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35208 17.87% 17.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35209 17.87% 17.87% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::1 80150 40.68% 58.55% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 582 0.30% 58.84% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::3 988 0.50% 59.34% # Number of instructions fetched each cycle (Total) @@ -737,17 +737,17 @@ system.cpu0.fetch.rateDist::8 2505 1.27% 100.00% # Nu system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 197037 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 197038 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.374178 # Number of branch fetches per cycle system.cpu0.fetch.rate 2.221065 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17850 # Number of cycles decode is idle +system.cpu0.decode.IdleCycles 17851 # Number of cycles decode is idle system.cpu0.decode.BlockedCycles 15597 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 160862 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 288 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 2440 # Number of cycles decode is squashing system.cpu0.decode.DecodedInsts 490280 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 2440 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18506 # Number of cycles rename is idle +system.cpu0.rename.IdleCycles 18507 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 827 # Number of cycles rename is blocking system.cpu0.rename.serializeStallCycles 14176 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 160527 # Number of cycles rename is running @@ -769,20 +769,20 @@ system.cpu0.memDep0.conflictingLoads 76026 # Nu system.cpu0.memDep0.conflictingStores 75860 # Number of conflicting stores. system.cpu0.iq.iqInstsAdded 407640 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 405049 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued +system.cpu0.iq.iqInstsIssued 405044 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued system.cpu0.iq.iqSquashedInstsExamined 10720 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedOperandsExamined 9396 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 197037 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055700 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097210 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 197038 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055664 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097184 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34075 17.29% 17.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34076 17.29% 17.29% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::1 4941 2.51% 19.80% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::2 78065 39.62% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77366 39.26% 98.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1557 0.79% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77371 39.27% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1552 0.79% 99.48% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 667 0.34% 99.81% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle @@ -790,7 +790,7 @@ system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Nu system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 197037 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 197038 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 57 27.01% 27.01% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 0 0.00% 27.01% # attempts to use FU when none available @@ -855,21 +855,21 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155510 38.39% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155505 38.39% 80.69% # Type of FU issued system.cpu0.iq.FU_type_0::MemWrite 78231 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 405049 # Type of FU issued -system.cpu0.iq.rate 1.824118 # Inst issue rate +system.cpu0.iq.FU_type_0::total 405044 # Type of FU issued +system.cpu0.iq.rate 1.824095 # Inst issue rate system.cpu0.iq.fu_busy_cnt 211 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.000521 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1007474 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_reads 1007470 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 419326 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 403236 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_wakeup_accesses 403231 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 405260 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 405255 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 75609 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -898,29 +898,29 @@ system.cpu0.iew.predictedNotTakenIncorrect 1114 # system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 403978 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 155175 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecSquashedInsts 1066 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 76577 # number of nop insts executed system.cpu0.iew.exec_refs 233309 # number of memory reference insts executed system.cpu0.iew.exec_branches 80250 # Number of branches executed system.cpu0.iew.exec_stores 78134 # Number of stores executed system.cpu0.iew.exec_rate 1.819295 # Inst execution rate -system.cpu0.iew.wb_sent 403577 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 403236 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238895 # num instructions producing a value -system.cpu0.iew.wb_consumers 241362 # num instructions consuming a value +system.cpu0.iew.wb_sent 403557 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 403231 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238890 # num instructions producing a value +system.cpu0.iew.wb_consumers 241357 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.815953 # insts written-back per cycle +system.cpu0.iew.wb_rate 1.815931 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.989779 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitSquashedInsts 12132 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1219 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 194597 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430500 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136019 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 194598 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430487 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136021 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34534 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34535 17.75% 17.75% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::1 80010 41.12% 58.86% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::2 2413 1.24% 60.10% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 690 0.35% 60.46% # Number of insts commited each cycle @@ -932,7 +932,7 @@ system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # N system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 194597 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 194598 # Number of insts commited each cycle system.cpu0.commit.committedInsts 472968 # Number of instructions committed system.cpu0.commit.committedOps 472968 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed @@ -945,10 +945,10 @@ system.cpu0.commit.int_insts 318742 # Nu system.cpu0.commit.function_calls 223 # Number of function calls committed. system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 678234 # The number of ROB reads +system.cpu0.rob.rob_reads 678235 # The number of ROB reads system.cpu0.rob.rob_writes 972657 # The number of ROB writes system.cpu0.timesIdled 325 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25015 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.idleCycles 25014 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.committedInsts 396861 # Number of Instructions Simulated system.cpu0.committedOps 396861 # Number of Ops (including micro ops) Simulated system.cpu0.committedInsts_total 396861 # Number of Instructions Simulated @@ -957,19 +957,19 @@ system.cpu0.cpi_total 0.559521 # CP system.cpu0.ipc 1.787244 # IPC: Instructions Per Cycle system.cpu0.ipc_total 1.787244 # IPC: Total IPC of All Threads system.cpu0.int_regfile_reads 722661 # number of integer regfile reads -system.cpu0.int_regfile_writes 325773 # number of integer regfile writes +system.cpu0.int_regfile_writes 325753 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads system.cpu0.misc_regfile_reads 235146 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.tags.replacements 297 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.313735 # Cycle average of tags in use +system.cpu0.icache.tags.tagsinuse 241.312438 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 5113 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 8.710392 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.313735 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471316 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471316 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.312438 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471313 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471313 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 5113 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5113 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 5113 # number of demand (read+write) hits @@ -982,12 +982,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 756 # system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses system.cpu0.icache.overall_misses::total 756 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35940245 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 35940245 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 35940245 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 35940245 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 35940245 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 35940245 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35939745 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 35939745 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 35939745 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 35939745 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 35939745 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 35939745 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 5869 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 5869 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 5869 # number of demand (read+write) accesses @@ -1000,12 +1000,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.128812 system.cpu0.icache.demand_miss_rate::total 0.128812 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.128812 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.128812 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47540.006614 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 47540.006614 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 47540.006614 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47540.006614 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 47540.006614 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47539.345238 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47539.345238 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47539.345238 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47539.345238 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47539.345238 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1026,34 +1026,34 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686252 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27686252 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686252 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27686252 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27686752 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27686752 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27686752 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27686752 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27686752 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27686752 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100187 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.100187 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100187 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.100187 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47085.462585 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47085.462585 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 47085.462585 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47086.312925 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47086.312925 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 47086.312925 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.026994 # Cycle average of tags in use +system.cpu0.dcache.tags.tagsinuse 142.026071 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 155821 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 916.594118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026994 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026071 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277395 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277395 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 79085 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 79085 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 76817 # number of WriteReq hits @@ -1245,20 +1245,20 @@ system.cpu1.memDep0.conflictingLoads 34021 # Nu system.cpu1.memDep0.conflictingStores 26934 # Number of conflicting stores. system.cpu1.iq.iqInstsAdded 208112 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 8163 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 211924 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued +system.cpu1.iq.iqInstsIssued 211912 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued system.cpu1.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10911 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedOperandsExamined 10947 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed system.cpu1.iq.issued_per_cycle::samples 175722 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.206019 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.291588 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.205950 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.291467 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::0 78073 44.43% 44.43% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::1 27855 15.85% 60.28% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::2 32175 18.31% 78.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 32801 18.67% 97.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3291 1.87% 99.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 32813 18.67% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3279 1.87% 99.13% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 1173 0.67% 99.80% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 248 0.14% 99.94% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle @@ -1331,21 +1331,21 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.43% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.43% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 75900 35.81% 85.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 75888 35.81% 85.24% # Type of FU issued system.cpu1.iq.FU_type_0::MemWrite 31278 14.76% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 211924 # Type of FU issued -system.cpu1.iq.rate 1.191033 # Inst issue rate +system.cpu1.iq.FU_type_0::total 211912 # Type of FU issued +system.cpu1.iq.rate 1.190965 # Inst issue rate system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.001255 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 599908 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_reads 599896 # Number of integer instruction queue reads system.cpu1.iq.int_inst_queue_writes 227186 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 210080 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_wakeup_accesses 210068 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 212190 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 212178 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu1.iew.lsq.thread0.forwLoads 26664 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -1374,20 +1374,20 @@ system.cpu1.iew.predictedNotTakenIncorrect 919 # system.cpu1.iew.branchMispredicts 1389 # Number of branch mispredicts detected at execute system.cpu1.iew.iewExecutedInsts 210729 # Number of executed instructions system.cpu1.iew.iewExecLoadInsts 68768 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecSquashedInsts 1183 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed system.cpu1.iew.exec_nop 34927 # number of nop insts executed system.cpu1.iew.exec_refs 99964 # number of memory reference insts executed system.cpu1.iew.exec_branches 44131 # Number of branches executed system.cpu1.iew.exec_stores 31196 # Number of stores executed system.cpu1.iew.exec_rate 1.184317 # Inst execution rate -system.cpu1.iew.wb_sent 210404 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 210080 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 116723 # num instructions producing a value -system.cpu1.iew.wb_consumers 121388 # num instructions consuming a value +system.cpu1.iew.wb_sent 210356 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 210068 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 116711 # num instructions producing a value +system.cpu1.iew.wb_consumers 121376 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.180669 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.961570 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.180602 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.961566 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitSquashedInsts 12479 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 7561 # The number of times commit has been forced to stall to communicate backwards @@ -1434,17 +1434,17 @@ system.cpu1.cpi_total 0.899810 # CP system.cpu1.ipc 1.111345 # IPC: Instructions Per Cycle system.cpu1.ipc_total 1.111345 # IPC: Total IPC of All Threads system.cpu1.int_regfile_reads 358439 # number of integer regfile reads -system.cpu1.int_regfile_writes 167816 # number of integer regfile writes +system.cpu1.int_regfile_writes 167768 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes system.cpu1.misc_regfile_reads 101509 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.tags.replacements 318 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.730522 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 76.730517 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 22903 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 53.511682 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730522 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.730517 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149864 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.149864 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 22903 # number of ReadReq hits @@ -1459,12 +1459,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 476 # system.cpu1.icache.demand_misses::total 476 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 476 # number of overall misses system.cpu1.icache.overall_misses::total 476 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7185993 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7185993 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7185993 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7185993 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7185993 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7185993 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7186493 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7186493 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7186493 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7186493 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7186493 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7186493 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 23379 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 23379 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 23379 # number of demand (read+write) accesses @@ -1477,12 +1477,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.020360 system.cpu1.icache.demand_miss_rate::total 0.020360 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.020360 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.020360 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15096.623950 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15096.623950 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15096.623950 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15096.623950 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15096.623950 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15097.674370 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15097.674370 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15097.674370 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15097.674370 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15097.674370 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1503,24 +1503,24 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726006 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5726006 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726006 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5726006 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5726506 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5726506 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5726506 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5726506 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5726506 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5726506 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018307 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.018307 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018307 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.018307 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13378.518692 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13378.518692 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13378.518692 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13379.686916 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13379.686916 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13379.686916 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements system.cpu1.dcache.tags.tagsinuse 23.664777 # Cycle average of tags in use @@ -1648,66 +1648,66 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9043.246324 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9043.246324 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9043.246324 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51290 # Number of BP lookups +system.cpu2.branchPred.lookups 51289 # Number of BP lookups system.cpu2.branchPred.condPredicted 48575 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 1303 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 45092 # Number of BTB lookups +system.cpu2.branchPred.BTBLookups 45091 # Number of BTB lookups system.cpu2.branchPred.BTBHits 44400 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.465360 # BTB Hit Percentage +system.cpu2.branchPred.BTBHitPct 98.467543 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu2.numCycles 177568 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28807 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 286591 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51290 # Number of branches that fetch encountered +system.cpu2.fetch.icacheStallCycles 28811 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 286582 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51289 # Number of branches that fetch encountered system.cpu2.fetch.predictedBranches 45084 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 100996 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.Cycles 100994 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.SquashCycles 3797 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 31176 # Number of cycles fetch has spent blocked +system.cpu2.fetch.BlockedCycles 31174 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 7777 # Number of stall cycles due to no active thread to fetch from system.cpu2.fetch.PendingTrapStallCycles 828 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 19752 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.CacheLines 19751 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.rateDist::samples 172005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.666178 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.140016 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.666126 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.139968 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 71009 41.28% 41.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51379 29.87% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 71011 41.28% 41.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51378 29.87% 71.15% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 6118 3.56% 74.71% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::3 3176 1.85% 76.56% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::4 688 0.40% 76.96% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::5 34434 20.02% 96.98% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::6 1153 0.67% 97.65% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::7 776 0.45% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3272 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3271 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::total 172005 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.288847 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.613979 # Number of inst fetches per cycle +system.cpu2.fetch.branchRate 0.288841 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.613928 # Number of inst fetches per cycle system.cpu2.decode.IdleCycles 33784 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 27885 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 95101 # Number of cycles decode is running +system.cpu2.decode.BlockedCycles 27886 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 95100 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 5041 # Number of cycles decode is unblocking system.cpu2.decode.SquashCycles 2417 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 283083 # Number of instructions handled by decode +system.cpu2.decode.DecodedInsts 283075 # Number of instructions handled by decode system.cpu2.rename.SquashCycles 2417 # Number of cycles rename is squashing system.cpu2.rename.IdleCycles 34494 # Number of cycles rename is idle system.cpu2.rename.BlockCycles 14868 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12251 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90316 # Number of cycles rename is running +system.cpu2.rename.serializeStallCycles 12252 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90315 # Number of cycles rename is running system.cpu2.rename.UnblockCycles 9882 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 280840 # Number of instructions processed by rename +system.cpu2.rename.RenamedInsts 280839 # Number of instructions processed by rename system.cpu2.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full system.cpu2.rename.RenamedOperands 196811 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 538434 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 418653 # Number of integer rename lookups +system.cpu2.rename.RenameLookups 538430 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 418650 # Number of integer rename lookups system.cpu2.rename.CommittedMaps 183802 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 13009 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 1113 # count of serializing insts renamed @@ -1719,20 +1719,20 @@ system.cpu2.memDep0.conflictingLoads 37867 # Nu system.cpu2.memDep0.conflictingStores 32593 # Number of conflicting stores. system.cpu2.iq.iqInstsAdded 232899 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqNonSpecInstsAdded 6340 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234909 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu2.iq.iqInstsIssued 234900 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued system.cpu2.iq.iqSquashedInstsExamined 11011 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedOperandsExamined 10850 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed system.cpu2.iq.issued_per_cycle::samples 172005 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.365710 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.313889 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.365658 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.313804 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::0 68443 39.79% 39.79% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::1 22432 13.04% 52.83% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::2 37853 22.01% 74.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38461 22.36% 97.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3256 1.89% 99.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38470 22.37% 97.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3247 1.89% 99.09% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::5 1167 0.68% 99.77% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::6 279 0.16% 99.93% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 57 0.03% 99.97% # Number of insts issued each cycle @@ -1805,21 +1805,21 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.68% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.68% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.68% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.68% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83601 35.59% 84.27% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83592 35.59% 84.27% # Type of FU issued system.cpu2.iq.FU_type_0::MemWrite 36958 15.73% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234909 # Type of FU issued -system.cpu2.iq.rate 1.322924 # Inst issue rate +system.cpu2.iq.FU_type_0::total 234900 # Type of FU issued +system.cpu2.iq.rate 1.322873 # Inst issue rate system.cpu2.iq.fu_busy_cnt 283 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.001205 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 642198 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_reads 642189 # Number of integer instruction queue reads system.cpu2.iq.int_inst_queue_writes 250297 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 233108 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.int_inst_queue_wakeup_accesses 233099 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 235192 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 235183 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu2.iew.lsq.thread0.forwLoads 32324 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -1848,20 +1848,20 @@ system.cpu2.iew.predictedNotTakenIncorrect 973 # system.cpu2.iew.branchMispredicts 1430 # Number of branch mispredicts detected at execute system.cpu2.iew.iewExecutedInsts 233765 # Number of executed instructions system.cpu2.iew.iewExecLoadInsts 78300 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1144 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecSquashedInsts 1135 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 38771 # number of nop insts executed system.cpu2.iew.exec_refs 115173 # number of memory reference insts executed system.cpu2.iew.exec_branches 48001 # Number of branches executed system.cpu2.iew.exec_stores 36873 # Number of stores executed system.cpu2.iew.exec_rate 1.316482 # Inst execution rate -system.cpu2.iew.wb_sent 233421 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 233108 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 131942 # num instructions producing a value -system.cpu2.iew.wb_consumers 136650 # num instructions consuming a value +system.cpu2.iew.wb_sent 233385 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 233099 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131933 # num instructions producing a value +system.cpu2.iew.wb_consumers 136641 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.312782 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.965547 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.312731 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965545 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitSquashedInsts 12656 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 5738 # The number of times commit has been forced to stall to communicate backwards @@ -1908,55 +1908,55 @@ system.cpu2.cpi_total 0.798482 # CP system.cpu2.ipc 1.252377 # IPC: Instructions Per Cycle system.cpu2.ipc_total 1.252377 # IPC: Total IPC of All Threads system.cpu2.int_regfile_reads 404230 # number of integer regfile reads -system.cpu2.int_regfile_writes 188808 # number of integer regfile writes +system.cpu2.int_regfile_writes 188772 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes system.cpu2.misc_regfile_reads 116736 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.tags.replacements 317 # number of replacements -system.cpu2.icache.tags.tagsinuse 82.236622 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19259 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 82.236554 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19258 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 45.315294 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.312941 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236622 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236554 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160618 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.160618 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 19259 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19259 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19259 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19259 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19259 # number of overall hits -system.cpu2.icache.overall_hits::total 19259 # number of overall hits +system.cpu2.icache.ReadReq_hits::cpu2.inst 19258 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19258 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19258 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19258 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19258 # number of overall hits +system.cpu2.icache.overall_hits::total 19258 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses system.cpu2.icache.overall_misses::total 493 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11620241 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11620241 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11620241 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11620241 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11620241 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11620241 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19752 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19752 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19752 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19752 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19752 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19752 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024959 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024959 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024959 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024959 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024959 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024959 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23570.468560 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23570.468560 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23570.468560 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23570.468560 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23570.468560 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11621241 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11621241 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11621241 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11621241 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11621241 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11621241 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19751 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19751 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19751 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19751 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19751 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19751 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024961 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024961 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024961 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23572.496957 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23572.496957 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23572.496957 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23572.496957 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23572.496957 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1977,32 +1977,32 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9299505 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 9299505 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9299505 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 9299505 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9299505 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 9299505 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021517 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021517 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021517 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021517 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21881.188235 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21881.188235 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21881.188235 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9301005 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 9301005 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9301005 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 9301005 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9301005 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 9301005 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021518 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021518 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021518 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021518 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21884.717647 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21884.717647 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21884.717647 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.142582 # Cycle average of tags in use +system.cpu2.dcache.tags.tagsinuse 26.142591 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 42207 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. system.cpu2.dcache.tags.avg_refs 1507.392857 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142582 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.142591 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051060 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_percent::total 0.051060 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 45613 # number of ReadReq hits @@ -2025,16 +2025,16 @@ system.cpu2.dcache.demand_misses::cpu2.data 485 # system.cpu2.dcache.demand_misses::total 485 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 485 # number of overall misses system.cpu2.dcache.overall_misses::total 485 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5531640 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5531640 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5532140 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5532140 # number of ReadReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3131011 # number of WriteReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::total 3131011 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 555006 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 555006 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8662651 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8662651 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8662651 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8662651 # number of overall miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8663151 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8663151 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8663151 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8663151 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 45959 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 45959 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 36105 # number of WriteReq accesses(hits+misses) @@ -2055,16 +2055,16 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005910 system.cpu2.dcache.demand_miss_rate::total 0.005910 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005910 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.005910 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15987.398844 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 15987.398844 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15988.843931 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 15988.843931 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993 # average WriteReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9736.947368 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 9736.947368 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17861.136082 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17861.136082 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17861.136082 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17862.167010 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17862.167010 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17862.167010 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2134,13 +2134,13 @@ system.cpu3.branchPred.RASInCorrect 232 # Nu system.cpu3.numCycles 177222 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 28850 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.icacheStallCycles 28851 # Number of cycles fetch is stalled on an Icache miss system.cpu3.fetch.Insts 291591 # Number of instructions fetch has processed system.cpu3.fetch.Branches 52302 # Number of branches that fetch encountered system.cpu3.fetch.predictedBranches 46126 # Number of branches that fetch has predicted taken system.cpu3.fetch.Cycles 103443 # Number of cycles fetch has run and was not squashing or blocked system.cpu3.fetch.SquashCycles 3689 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 32602 # Number of cycles fetch has spent blocked +system.cpu3.fetch.BlockedCycles 32601 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 7775 # Number of stall cycles due to no active thread to fetch from system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps @@ -2165,16 +2165,16 @@ system.cpu3.fetch.rateDist::max_value 8 # Nu system.cpu3.fetch.rateDist::total 175820 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.branchRate 0.295121 # Number of branch fetches per cycle system.cpu3.fetch.rate 1.645343 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 34476 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 28632 # Number of cycles decode is blocked +system.cpu3.decode.IdleCycles 34477 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28631 # Number of cycles decode is blocked system.cpu3.decode.RunCycles 97078 # Number of cycles decode is running system.cpu3.decode.UnblockCycles 5513 # Number of cycles decode is unblocking system.cpu3.decode.SquashCycles 2346 # Number of cycles decode is squashing system.cpu3.decode.DecodedInsts 288057 # Number of instructions handled by decode system.cpu3.rename.SquashCycles 2346 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 35171 # Number of cycles rename is idle +system.cpu3.rename.IdleCycles 35172 # Number of cycles rename is idle system.cpu3.rename.BlockCycles 16067 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11805 # count of cycles rename stalled for serializing inst +system.cpu3.rename.serializeStallCycles 11804 # count of cycles rename stalled for serializing inst system.cpu3.rename.RunCycles 91834 # Number of cycles rename is running system.cpu3.rename.UnblockCycles 10822 # Number of cycles rename is unblocking system.cpu3.rename.RenamedInsts 285905 # Number of instructions processed by rename @@ -2194,20 +2194,20 @@ system.cpu3.memDep0.conflictingLoads 38893 # Nu system.cpu3.memDep0.conflictingStores 33161 # Number of conflicting stores. system.cpu3.iq.iqInstsAdded 236458 # Number of instructions added to the IQ (excludes non-spec) system.cpu3.iq.iqNonSpecInstsAdded 6797 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 239002 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued +system.cpu3.iq.iqInstsIssued 238990 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued system.cpu3.iq.iqSquashedInstsExamined 10736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10694 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedOperandsExamined 10730 # Number of squashed operands that are examined and possibly removed from graph system.cpu3.iq.iqSquashedNonSpecRemoved 584 # Number of squashed non-spec instructions that were removed system.cpu3.iq.issued_per_cycle::samples 175820 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.359356 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.308484 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.359288 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.308373 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::0 69781 39.69% 39.69% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::1 23810 13.54% 53.23% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::2 38390 21.83% 75.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 39034 22.20% 97.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3259 1.85% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 39046 22.21% 97.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3247 1.85% 99.12% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::5 1173 0.67% 99.79% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle @@ -2280,21 +2280,21 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Ty system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 85680 35.85% 84.31% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 85668 35.85% 84.31% # Type of FU issued system.cpu3.iq.FU_type_0::MemWrite 37507 15.69% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 239002 # Type of FU issued -system.cpu3.iq.rate 1.348602 # Inst issue rate +system.cpu3.iq.FU_type_0::total 238990 # Type of FU issued +system.cpu3.iq.rate 1.348535 # Inst issue rate system.cpu3.iq.fu_busy_cnt 274 # FU busy when requested system.cpu3.iq.fu_busy_rate 0.001146 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 654188 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_reads 654176 # Number of integer instruction queue reads system.cpu3.iq.int_inst_queue_writes 254038 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 237209 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.int_inst_queue_wakeup_accesses 237197 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 239276 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 239264 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu3.iew.lsq.thread0.forwLoads 32896 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -2323,20 +2323,20 @@ system.cpu3.iew.predictedNotTakenIncorrect 929 # system.cpu3.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute system.cpu3.iew.iewExecutedInsts 237848 # Number of executed instructions system.cpu3.iew.iewExecLoadInsts 79902 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed system.cpu3.iew.exec_nop 39788 # number of nop insts executed system.cpu3.iew.exec_refs 117326 # number of memory reference insts executed system.cpu3.iew.exec_branches 49028 # Number of branches executed system.cpu3.iew.exec_stores 37424 # Number of stores executed system.cpu3.iew.exec_rate 1.342091 # Inst execution rate -system.cpu3.iew.wb_sent 237529 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 237209 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 134044 # num instructions producing a value -system.cpu3.iew.wb_consumers 138720 # num instructions consuming a value +system.cpu3.iew.wb_sent 237481 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 237197 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 134032 # num instructions producing a value +system.cpu3.iew.wb_consumers 138708 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.338485 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.966292 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.338417 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.966289 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu3.commit.commitSquashedInsts 12298 # The number of squashed insts skipped by commit system.cpu3.commit.commitNonSpecStalls 6213 # The number of times commit has been forced to stall to communicate backwards @@ -2383,17 +2383,17 @@ system.cpu3.cpi_total 0.783392 # CP system.cpu3.ipc 1.276501 # IPC: Instructions Per Cycle system.cpu3.ipc_total 1.276501 # IPC: Total IPC of All Threads system.cpu3.int_regfile_reads 410473 # number of integer regfile reads -system.cpu3.int_regfile_writes 191401 # number of integer regfile writes +system.cpu3.int_regfile_writes 191353 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes system.cpu3.misc_regfile_reads 118878 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.tags.replacements 319 # number of replacements -system.cpu3.icache.tags.tagsinuse 79.942849 # Cycle average of tags in use +system.cpu3.icache.tags.tagsinuse 79.942822 # Cycle average of tags in use system.cpu3.icache.tags.total_refs 20090 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 429 # Sample count of references to valid blocks. system.cpu3.icache.tags.avg_refs 46.829837 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942849 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_blocks::cpu3.inst 79.942822 # Average occupied blocks per requestor system.cpu3.icache.tags.occ_percent::cpu3.inst 0.156138 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_percent::total 0.156138 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 20090 # number of ReadReq hits @@ -2408,12 +2408,12 @@ system.cpu3.icache.demand_misses::cpu3.inst 475 # system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses system.cpu3.icache.overall_misses::total 475 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449245 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6449245 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6449245 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6449245 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6449245 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6449245 # number of overall miss cycles +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6449745 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6449745 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6449745 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6449745 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6449745 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6449745 # number of overall miss cycles system.cpu3.icache.ReadReq_accesses::cpu3.inst 20565 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_accesses::total 20565 # number of ReadReq accesses(hits+misses) system.cpu3.icache.demand_accesses::cpu3.inst 20565 # number of demand (read+write) accesses @@ -2426,12 +2426,12 @@ system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023097 system.cpu3.icache.demand_miss_rate::total 0.023097 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023097 # miss rate for overall accesses system.cpu3.icache.overall_miss_rate::total 0.023097 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13577.357895 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13577.357895 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13577.357895 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13577.357895 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13577.357895 # average overall miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13578.410526 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13578.410526 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13578.410526 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13578.410526 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13578.410526 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2452,32 +2452,32 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223255 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223255 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223255 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5223255 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223255 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5223255 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5223755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5223755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5223755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5223755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5223755 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5223755 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020861 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_miss_rate::total 0.020861 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020861 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_miss_rate::total 0.020861 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12175.419580 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12175.419580 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12175.419580 # average overall mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12176.585082 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12176.585082 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12176.585082 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.692253 # Cycle average of tags in use +system.cpu3.dcache.tags.tagsinuse 24.692248 # Cycle average of tags in use system.cpu3.dcache.tags.total_refs 42769 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. system.cpu3.dcache.tags.avg_refs 1527.464286 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692253 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.692248 # Average occupied blocks per requestor system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048227 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_percent::total 0.048227 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 46656 # number of ReadReq hits @@ -2500,16 +2500,16 @@ system.cpu3.dcache.demand_misses::cpu3.data 464 # system.cpu3.dcache.demand_misses::total 464 # number of demand (read+write) misses system.cpu3.dcache.overall_misses::cpu3.data 464 # number of overall misses system.cpu3.dcache.overall_misses::total 464 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4249100 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 4249100 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3352512 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3352512 # number of WriteReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4248100 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4248100 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3351512 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3351512 # number of WriteReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 492006 # number of SwapReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::total 492006 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7601612 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7601612 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7601612 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7601612 # number of overall miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7599612 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7599612 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7599612 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7599612 # number of overall miss cycles system.cpu3.dcache.ReadReq_accesses::cpu3.data 46989 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 46989 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 36684 # number of WriteReq accesses(hits+misses) @@ -2530,16 +2530,16 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005545 system.cpu3.dcache.demand_miss_rate::total 0.005545 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005545 # miss rate for overall accesses system.cpu3.dcache.overall_miss_rate::total 0.005545 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12760.060060 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12760.060060 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25591.694656 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 25591.694656 # average WriteReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12757.057057 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12757.057057 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25584.061069 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 25584.061069 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9111.222222 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 9111.222222 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 16382.784483 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16382.784483 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 16382.784483 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16378.474138 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16378.474138 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16378.474138 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2568,14 +2568,14 @@ system.cpu3.dcache.overall_mshr_misses::cpu3.data 252 system.cpu3.dcache.overall_mshr_misses::total 252 # number of overall MSHR misses system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1002524 # number of ReadReq MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1002524 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408738 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408738 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1408238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1408238 # number of WriteReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 383994 # number of SwapReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::total 383994 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2411262 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2411262 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2411262 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2411262 # number of overall MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2410762 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2410762 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2410762 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2410762 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003235 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003235 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002726 # mshr miss rate for WriteReq accesses @@ -2588,14 +2588,14 @@ system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003012 system.cpu3.dcache.overall_mshr_miss_rate::total 0.003012 # mshr miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6595.552632 # average ReadReq mshr miss latency system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6595.552632 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14087.380000 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14087.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14082.380000 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14082.380000 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7111 # average SwapReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7111 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9568.500000 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9568.500000 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9566.515873 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9566.515873 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 51f67db18..fc54ba8f2 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bu boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -93,11 +99,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.icache] @@ -106,6 +114,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -128,21 +137,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu0.isa] type=SparcISA +eventq_index=0 [system.cpu0.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu0.workload] type=LiveProcess @@ -152,7 +166,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +eventq_index=0 +executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -173,6 +188,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts @@ -199,6 +215,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -221,11 +238,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.icache] @@ -234,6 +253,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -256,21 +276,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu1.isa] type=SparcISA +eventq_index=0 [system.cpu1.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=TimingSimpleCPU @@ -282,6 +307,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu2.interrupts @@ -308,6 +334,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -330,11 +357,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu2.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.icache] @@ -343,6 +372,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -365,21 +395,26 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu2.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu2.isa] type=SparcISA +eventq_index=0 [system.cpu2.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu3] type=TimingSimpleCPU @@ -391,6 +426,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu3.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu3.interrupts @@ -417,6 +453,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -439,11 +476,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu3.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.icache] @@ -452,6 +491,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -474,25 +514,31 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu3.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu3.isa] type=SparcISA +eventq_index=0 [system.cpu3.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu3.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.l2c] @@ -501,6 +547,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -523,12 +570,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -541,6 +590,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -551,6 +601,7 @@ port=system.membus.master[0] [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -560,5 +611,6 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 8ba84a629..8d5cb3498 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000263 # Nu sim_ticks 262794500 # Number of ticks simulated final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 681070 # Simulator instruction rate (inst/s) -host_op_rate 681053 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 269712940 # Simulator tick rate (ticks/s) -host_mem_usage 243700 # Number of bytes of host memory used -host_seconds 0.97 # Real time elapsed on the host +host_inst_rate 200508 # Simulator instruction rate (inst/s) +host_op_rate 200507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79406810 # Simulator tick rate (ticks/s) +host_mem_usage 291148 # Number of bytes of host memory used +host_seconds 3.31 # Real time elapsed on the host sim_insts 663567 # Number of instructions simulated sim_ops 663567 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory @@ -169,36 +169,36 @@ system.l2c.overall_misses::cpu3.data 16 # nu system.l2c.overall_misses::total 592 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3436500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 418500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 597500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 103500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3434500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23504000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 23498500 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 801000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 747000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3.data 730000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7452000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7450500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3436500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1219500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 597500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 850500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3434500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.data 834500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30956000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30949000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3436500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1219500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 597500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 850500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3434500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.data 834500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30956000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30949000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) @@ -277,36 +277,36 @@ system.l2c.overall_miss_rate::cpu3.data 0.640000 # mi system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52037.878788 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52231.111111 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52218.888889 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52262.626263 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53400 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53357.142857 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52478.873239 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52468.309859 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52290.540541 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52278.716216 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52275.757576 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52068.181818 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 53021.739130 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 49791.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53156.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52037.878788 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.data 52156.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52290.540541 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52278.716216 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,28 +385,28 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5719000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5717500 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 6604000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 897500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 617500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22942000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22940500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 6604000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 897500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 617500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22942000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22940500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses @@ -459,28 +459,28 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.084507 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40105.769231 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.toL2Bus.throughput 646588875 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution @@ -767,17 +767,17 @@ system.cpu1.num_fp_register_writes 0 # nu system.cpu1.num_mem_refs 58020 # number of memory refs system.cpu1.num_load_insts 41540 # Number of load instructions system.cpu1.num_store_insts 16480 # Number of store instructions -system.cpu1.num_idle_cycles 69347.869793 # Number of idle cycles -system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles +system.cpu1.num_idle_cycles 69346.869795 # Number of idle cycles +system.cpu1.num_busy_cycles 456241.130205 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use +system.cpu1.icache.tags.tagsinuse 70.017504 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017504 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits @@ -792,12 +792,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 366 # system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544988 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7544988 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7544988 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7544988 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7544988 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7544988 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses @@ -810,12 +810,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20614.721311 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20614.721311 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20614.721311 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20614.721311 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20614.721311 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -830,24 +830,24 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6808012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6808012 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6808012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6808012 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6808012 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6808012 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6806012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806012 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6806012 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18595.661202 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18595.661202 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18595.661202 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use @@ -878,16 +878,16 @@ system.cpu1.dcache.demand_misses::cpu1.data 263 # system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses system.cpu1.dcache.overall_misses::total 263 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) @@ -908,16 +908,16 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -936,16 +936,16 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses @@ -956,16 +956,16 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 525588 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -985,17 +985,17 @@ system.cpu2.num_fp_register_writes 0 # nu system.cpu2.num_mem_refs 59208 # number of memory refs system.cpu2.num_load_insts 42171 # Number of load instructions system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles -system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles +system.cpu2.num_idle_cycles 69603.869305 # Number of idle cycles +system.cpu2.num_busy_cycles 455984.130695 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867570 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132430 # Percentage of idle cycles system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use +system.cpu2.icache.tags.tagsinuse 67.624960 # Cycle average of tags in use system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624960 # Average occupied blocks per requestor system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits @@ -1010,12 +1010,12 @@ system.cpu2.icache.demand_misses::cpu2.inst 366 # system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5255488 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5255488 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5255488 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5255488 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5255488 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5255488 # number of overall miss cycles +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5252488 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5252488 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5252488 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5252488 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5252488 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5252488 # number of overall miss cycles system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses @@ -1028,12 +1028,12 @@ system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14359.256831 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14359.256831 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14359.256831 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14359.256831 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14359.256831 # average overall miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14351.060109 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14351.060109 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14351.060109 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14351.060109 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14351.060109 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1048,32 +1048,32 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4513512 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4513512 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4513512 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4513512 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4513512 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4513512 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510512 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510512 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510512 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4510512 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510512 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4510512 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12332 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12332 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12332 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12332 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12323.803279 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12323.803279 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12323.803279 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.763892 # Cycle average of tags in use +system.cpu2.dcache.tags.tagsinuse 26.763890 # Cycle average of tags in use system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763892 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763890 # Average occupied blocks per requestor system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits @@ -1096,16 +1096,16 @@ system.cpu2.dcache.demand_misses::cpu2.data 262 # system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses system.cpu2.dcache.overall_misses::total 262 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2129481 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2129481 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1930500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1930500 # number of WriteReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4059981 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4059981 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4059981 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4059981 # number of overall miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses) @@ -1126,16 +1126,16 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14009.743421 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 14009.743421 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17550 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17550 # average WriteReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 15496.110687 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15496.110687 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 15496.110687 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1154,16 +1154,16 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1710500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1710500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3520019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520019 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3520019 # number of overall MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses @@ -1174,16 +1174,16 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15550 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15550 # average WriteReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 525588 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started |